JPS56143054A - Microprogram control system - Google Patents
Microprogram control systemInfo
- Publication number
- JPS56143054A JPS56143054A JP4611680A JP4611680A JPS56143054A JP S56143054 A JPS56143054 A JP S56143054A JP 4611680 A JP4611680 A JP 4611680A JP 4611680 A JP4611680 A JP 4611680A JP S56143054 A JPS56143054 A JP S56143054A
- Authority
- JP
- Japan
- Prior art keywords
- halt
- error
- retrial
- informed
- diagnostic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To improve the through-put with a countermeasure to an intermittent failure, by avoiding the halt of self-diagnostic error which does not require the halt of micro mu program PG and making other devices informed of it. CONSTITUTION:The mu processor PC1 reads out the mu instruction code from the muPG memory 2 for command processing and self diagnosis processing and the like. If an error is detected during the self diagnosis of other hardware 5, the diagnostic retrial bit 41 stored in the sense information memory 4 is set and retried by n-times at the counter 42. If retrial is failed, the halt signal is fed from the halt register RG3 to PC1 for halt, and the halt is informed to other controller. If retrial is successuful, error display is set to the interruption status RG10 to PC1 and informed as the error. When the other controller reads in the error from RG10, the sense command is given to seek the cause of the error.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4611680A JPS6052459B2 (en) | 1980-04-08 | 1980-04-08 | Microprogram control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4611680A JPS6052459B2 (en) | 1980-04-08 | 1980-04-08 | Microprogram control method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56143054A true JPS56143054A (en) | 1981-11-07 |
| JPS6052459B2 JPS6052459B2 (en) | 1985-11-19 |
Family
ID=12738022
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4611680A Expired JPS6052459B2 (en) | 1980-04-08 | 1980-04-08 | Microprogram control method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052459B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5613066A (en) * | 1993-10-01 | 1997-03-18 | Fujitsu Limited | Disk controlling method and apparatus for transferring a record from a disk to a host via an intermediate buffer |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6972738B2 (en) | 2017-07-28 | 2021-11-24 | 富士フイルムビジネスイノベーション株式会社 | Information processing equipment and programs |
| JP6493466B2 (en) | 2017-07-28 | 2019-04-03 | 富士ゼロックス株式会社 | Information processing apparatus and program |
| JP6447689B1 (en) | 2017-09-11 | 2019-01-09 | 富士ゼロックス株式会社 | Information processing apparatus and program |
| JP7087363B2 (en) | 2017-12-01 | 2022-06-21 | 富士フイルムビジネスイノベーション株式会社 | Information processing equipment and programs |
-
1980
- 1980-04-08 JP JP4611680A patent/JPS6052459B2/en not_active Expired
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5613066A (en) * | 1993-10-01 | 1997-03-18 | Fujitsu Limited | Disk controlling method and apparatus for transferring a record from a disk to a host via an intermediate buffer |
| US5878204A (en) * | 1993-10-01 | 1999-03-02 | Fujitsu Limited | Disk controlling method and apparatus for transferring a record from a disk to a host via an intermediate buffer |
| US6092216A (en) * | 1993-10-01 | 2000-07-18 | Fujitsu Limited | Disk controlling apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6052459B2 (en) | 1985-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP0056060B1 (en) | Data processing system | |
| EP0201356A3 (en) | High level self-checking intelligent i/o controller | |
| FR2609340B1 (en) | ||
| JPS56143054A (en) | Microprogram control system | |
| FR2170659A5 (en) | ||
| JPS61141001A (en) | Structure diagnosis system of process control system | |
| JPS5938852A (en) | Fault processing system | |
| JPH0496832A (en) | Fault information gathering device | |
| JPS57143646A (en) | Error recovery system for logical device | |
| JP3481301B2 (en) | Processor control unit | |
| JPS6288047A (en) | Interface controller | |
| JPS57143669A (en) | Debugging device for multiprocessor system | |
| JPS573148A (en) | Diagnostic system for other system | |
| SU813430A1 (en) | Logic unit testing device | |
| JPS56145434A (en) | Error processing system of microcomputer | |
| JPS6323598B2 (en) | ||
| JPS5896353A (en) | Malfunction detector of information processor | |
| JPS5616956A (en) | Magnetic tape processing system | |
| JPS6250841B2 (en) | ||
| JPH01161172A (en) | Interpreter processing system for ic testing device | |
| JPH07104822A (en) | Numerical control system | |
| JPH053016B2 (en) | ||
| JPS57147758A (en) | Memory error controlling system | |
| JPS6330660B2 (en) | ||
| JPS6414650A (en) | Fault diagnostic method for input/output controller in computer system |