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JPS56133823A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS56133823A
JPS56133823A JP3583080A JP3583080A JPS56133823A JP S56133823 A JPS56133823 A JP S56133823A JP 3583080 A JP3583080 A JP 3583080A JP 3583080 A JP3583080 A JP 3583080A JP S56133823 A JPS56133823 A JP S56133823A
Authority
JP
Japan
Prior art keywords
type
polycrystal
film
becoming
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3583080A
Other languages
Japanese (ja)
Inventor
Akihiko Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3583080A priority Critical patent/JPS56133823A/en
Publication of JPS56133823A publication Critical patent/JPS56133823A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a minuted and high-integrated semiconductor element by applying thermal oxidation to the unnecessary part of the wirings of a polycrystal silicon film for patterning wherein an impurity in the polycrystal is diffused to a substrate as well. CONSTITUTION:n<+> type buried layers 2, n type epitaxial layers 3 and p<+> type isolation regions 4 are formed on a p type Si substrate 1 to make a p type layer 51 becoming as a base and a p type layer 52 becoming the isolation layer of a resistance. Next, silicon oxide films 6 are selectively formed to pile up a polycrystal silicon film 8 on the whole surface. Next, a silicon nitride film 9 is formed at a part reserves as wiring. Next, thermal oxidation is applied to convert the exposed polycrystal part into a silicon oxide film and also to diffuse an n type impurity into the surface from the opening sections of the oxide films 6. The surface is flat and the stepped breakage of Al wiring is prevented and there is the small number of masks. Therefore, flitch error will be reduced.
JP3583080A 1980-03-21 1980-03-21 Manufacture of semiconductor device Pending JPS56133823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3583080A JPS56133823A (en) 1980-03-21 1980-03-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3583080A JPS56133823A (en) 1980-03-21 1980-03-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS56133823A true JPS56133823A (en) 1981-10-20

Family

ID=12452870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3583080A Pending JPS56133823A (en) 1980-03-21 1980-03-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS56133823A (en)

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