JPS56129348A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS56129348A JPS56129348A JP3252880A JP3252880A JPS56129348A JP S56129348 A JPS56129348 A JP S56129348A JP 3252880 A JP3252880 A JP 3252880A JP 3252880 A JP3252880 A JP 3252880A JP S56129348 A JPS56129348 A JP S56129348A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- printed
- metallized
- layers
- high reliability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
PURPOSE:To obtain the cheaper device with high reliability by an arrangement wherein capacitors are formed between the laminated layers of a ceramic substrate in a sandwich structure where an oxide dielectric layer is interposed between metal layers. CONSTITUTION:A W metallized layer 13b is printed at the first layer of a ceramic substrate 1b, one end of which is connected with an external lead 15b and the other end of which is connected with other lead. Then, an oxcide dielectric layer 14b is printed on the W metallized layer 13b and another metallized layer 13b is printed thereon. Next, similar printing is effected at the second layer of the substrate 1b and both terminals thereof are connected in parallel with respect to the metallized layers of the first layer. After forming the similar laminated layers in the desired number and then calcinating, an IC chip 2b is mounted on a mount portion 3b of thus obtained package. In such a manner, by laminating a plurality of sandwich structures, it becomes possible to freely change the electrostatic capacity and to obtain the cheaper device with high reliability.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3252880A JPS56129348A (en) | 1980-03-14 | 1980-03-14 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3252880A JPS56129348A (en) | 1980-03-14 | 1980-03-14 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56129348A true JPS56129348A (en) | 1981-10-09 |
Family
ID=12361439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3252880A Pending JPS56129348A (en) | 1980-03-14 | 1980-03-14 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56129348A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5994856A (en) * | 1982-11-24 | 1984-05-31 | Matsushita Electric Ind Co Ltd | Composite circuit device and mounting method thereof |
FR2550009A1 (en) * | 1983-07-29 | 1985-02-01 | Inf Milit Spatiale Aeronaut | ELECTRONIC COMPONENT HOUSING PROVIDED WITH A CAPACITOR |
EP0145694A2 (en) * | 1983-12-14 | 1985-06-19 | Jean-Marie Bonameau | Protection device against the perturbations and/or interferences in the vicinity of integrated circuits |
JPS60148148A (en) * | 1984-01-13 | 1985-08-05 | Nec Corp | Semiconductor device |
US4714952A (en) * | 1984-11-01 | 1987-12-22 | Nec Corporation | Capacitor built-in integrated circuit packaged unit and process of fabrication thereof |
FR2609841A1 (en) * | 1987-01-20 | 1988-07-22 | Toshiba Kk | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
JPH0513066U (en) * | 1991-07-26 | 1993-02-19 | 京セラ株式会社 | Package for storing semiconductor devices |
-
1980
- 1980-03-14 JP JP3252880A patent/JPS56129348A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5994856A (en) * | 1982-11-24 | 1984-05-31 | Matsushita Electric Ind Co Ltd | Composite circuit device and mounting method thereof |
FR2550009A1 (en) * | 1983-07-29 | 1985-02-01 | Inf Milit Spatiale Aeronaut | ELECTRONIC COMPONENT HOUSING PROVIDED WITH A CAPACITOR |
US4654694A (en) * | 1983-07-29 | 1987-03-31 | Compagnie D'informatique Militaire Spatiale Et Aeronautique | Electronic component box supplied with a capacitor |
EP0145694A2 (en) * | 1983-12-14 | 1985-06-19 | Jean-Marie Bonameau | Protection device against the perturbations and/or interferences in the vicinity of integrated circuits |
JPS60148148A (en) * | 1984-01-13 | 1985-08-05 | Nec Corp | Semiconductor device |
JPH0160941B2 (en) * | 1984-01-13 | 1989-12-26 | Nippon Electric Co | |
US4714952A (en) * | 1984-11-01 | 1987-12-22 | Nec Corporation | Capacitor built-in integrated circuit packaged unit and process of fabrication thereof |
FR2609841A1 (en) * | 1987-01-20 | 1988-07-22 | Toshiba Kk | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
JPH0513066U (en) * | 1991-07-26 | 1993-02-19 | 京セラ株式会社 | Package for storing semiconductor devices |
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