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JPS56115565A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS56115565A
JPS56115565A JP1939180A JP1939180A JPS56115565A JP S56115565 A JPS56115565 A JP S56115565A JP 1939180 A JP1939180 A JP 1939180A JP 1939180 A JP1939180 A JP 1939180A JP S56115565 A JPS56115565 A JP S56115565A
Authority
JP
Japan
Prior art keywords
layer
base
forming
base layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1939180A
Other languages
Japanese (ja)
Inventor
Junji Sakurai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP1939180A priority Critical patent/JPS56115565A/en
Publication of JPS56115565A publication Critical patent/JPS56115565A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004Base region of bipolar transistors
    • H01L29/1008Base region of bipolar transistors of lateral transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a base having narrow width in the horizontal transistor by forming a base layer in contact with a buried diffused layer having low specific resistance to reduce the external base resistance and forming a base layer and an emitter layer through the same forming window. CONSTITUTION:A base layer 15 reaching a P<+> type buried diffused layer 13 at the bottom is formed in contact with a field SiO2 film 12 at the three sides at a collector layer 14 insulated from the substrate via a P<+> type buried diffused layer (external base layer) 13 formed to make contact with the bottom of the film 12 in the substrate 11. An emitter layer 18 self-aligned with the base layer 15 via the SiO2 film 17 on the field film 12 and the collector layer 14 used as a mask when forming the base layer 15 in the region in the vicinity of the layer 14 of the layer 15 is formed.
JP1939180A 1980-02-19 1980-02-19 Semiconductor device Pending JPS56115565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1939180A JPS56115565A (en) 1980-02-19 1980-02-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1939180A JPS56115565A (en) 1980-02-19 1980-02-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS56115565A true JPS56115565A (en) 1981-09-10

Family

ID=11997978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1939180A Pending JPS56115565A (en) 1980-02-19 1980-02-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS56115565A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59104166A (en) * 1982-11-22 1984-06-15 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Control of injecting substrate in lateral bipolar transistor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017584A (en) * 1973-05-07 1975-02-24

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5017584A (en) * 1973-05-07 1975-02-24

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59104166A (en) * 1982-11-22 1984-06-15 フエアチアイルド・カメラ・アンド・インストルメント・コ−ポレ−シヨン Control of injecting substrate in lateral bipolar transistor
JPH0362015B2 (en) * 1982-11-22 1991-09-24 Fueachairudo Kamera Endo Insutsurumento Corp

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