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JPS56115541A - Metallizing method of back surface of semiconductor wafer - Google Patents

Metallizing method of back surface of semiconductor wafer

Info

Publication number
JPS56115541A
JPS56115541A JP1869580A JP1869580A JPS56115541A JP S56115541 A JPS56115541 A JP S56115541A JP 1869580 A JP1869580 A JP 1869580A JP 1869580 A JP1869580 A JP 1869580A JP S56115541 A JPS56115541 A JP S56115541A
Authority
JP
Japan
Prior art keywords
gold
back surface
wafer
semiconductor wafer
evaporated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1869580A
Other languages
Japanese (ja)
Inventor
Yutaka Maruyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1869580A priority Critical patent/JPS56115541A/en
Publication of JPS56115541A publication Critical patent/JPS56115541A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve the reliability of the semiconductor wafer by setting the temperature of evaporating gold on the back surface of the wafer lower then the gold- silicon eutectic temperature, thereby preventing the deterioration of the characteristics thereof. CONSTITUTION:The gold 12 is evaporated on the back surface of the silicon wafer 11, and the temperature is set lower than the gold-Si eutectic temperature 370 deg.C, such as, for example, 350 deg.C and the like. After the wafer 11 thus evaporated with the gold 12 is isolated from the chip, it is mounted on the ceramic substrate plated with the gold. Thus, the Si is not exposed on the surface evaporated with the gold on the wafer, but the oxidation of the back surface of the wafer can be prevented, and the reliability can be improved without deterioration of the characteristics thereof.
JP1869580A 1980-02-18 1980-02-18 Metallizing method of back surface of semiconductor wafer Pending JPS56115541A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1869580A JPS56115541A (en) 1980-02-18 1980-02-18 Metallizing method of back surface of semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1869580A JPS56115541A (en) 1980-02-18 1980-02-18 Metallizing method of back surface of semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS56115541A true JPS56115541A (en) 1981-09-10

Family

ID=11978755

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1869580A Pending JPS56115541A (en) 1980-02-18 1980-02-18 Metallizing method of back surface of semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS56115541A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296727A (en) * 1985-06-25 1986-12-27 Yokogawa Electric Corp Fixing of silicon pellet

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61296727A (en) * 1985-06-25 1986-12-27 Yokogawa Electric Corp Fixing of silicon pellet

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