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JPS56108242A - Master slice semiconductor device - Google Patents

Master slice semiconductor device

Info

Publication number
JPS56108242A
JPS56108242A JP1028180A JP1028180A JPS56108242A JP S56108242 A JPS56108242 A JP S56108242A JP 1028180 A JP1028180 A JP 1028180A JP 1028180 A JP1028180 A JP 1028180A JP S56108242 A JPS56108242 A JP S56108242A
Authority
JP
Japan
Prior art keywords
wiring
polycrystalline
master slice
layer
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1028180A
Other languages
Japanese (ja)
Other versions
JPH0120537B2 (en
Inventor
Soichi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1028180A priority Critical patent/JPS56108242A/en
Publication of JPS56108242A publication Critical patent/JPS56108242A/en
Publication of JPH0120537B2 publication Critical patent/JPH0120537B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To lighten the burden on the second and third layer wirings and reduce the manufacturing period of each individual kind by forming the polycrystalline Si wiring into a shape common to all kinds and prescribing the shape effectively. CONSTITUTION:Transistors 1 and 2 are located in portions of a master slice substrate, and the electrode wirings 3 and 6, 4 and 7, and 5 and 8 for their bases, emitters and collectors respectively are provided by using a polycrystalline Si layer. Separately, the second wiring layer 9 of polycrystalline Si is provided and connecting windows 17-20 are arranged so as to be adjacent and opposed to electrode windows 10-12 and 14-16 for the electrode wirings 3-8. Moreover, a resisting film having a width (w) and a length (l) can be formed in each of the wiring layers 5 and 8. Even if a specific connecting relationship has more effective arrangement in reduction in the wiring area, such arrangement will be disadvantageous to the other connections. Accordingly, by said constitution, a master slice substrate wherein the wiring area has been most effectively reduced can be obtained, and by multilayer interconnection a semiconductor device can be obtained.
JP1028180A 1980-01-31 1980-01-31 Master slice semiconductor device Granted JPS56108242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1028180A JPS56108242A (en) 1980-01-31 1980-01-31 Master slice semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1028180A JPS56108242A (en) 1980-01-31 1980-01-31 Master slice semiconductor device

Publications (2)

Publication Number Publication Date
JPS56108242A true JPS56108242A (en) 1981-08-27
JPH0120537B2 JPH0120537B2 (en) 1989-04-17

Family

ID=11745921

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1028180A Granted JPS56108242A (en) 1980-01-31 1980-01-31 Master slice semiconductor device

Country Status (1)

Country Link
JP (1) JPS56108242A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5874052A (en) * 1981-10-29 1983-05-04 Nec Corp Master slice semiconductor integrated circuit device
JPS58139445A (en) * 1982-02-15 1983-08-18 Nec Corp Semiconductor integrated circuit device
JPH06112447A (en) * 1992-11-13 1994-04-22 Seiko Epson Corp Semiconductor device
US8407539B2 (en) 2009-03-03 2013-03-26 Renesas Electronics Corporation Semiconductor device test circuit, semiconductor device, and its manufacturing method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024597A (en) * 1973-03-14 1975-03-15
JPS5120268A (en) * 1974-08-08 1976-02-18 Takashi Ishikawa Taika * tainetsusei goseijushi
JPS5493344A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor integrated circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024597A (en) * 1973-03-14 1975-03-15
JPS5120268A (en) * 1974-08-08 1976-02-18 Takashi Ishikawa Taika * tainetsusei goseijushi
JPS5493344A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Semiconductor integrated circuit

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5874052A (en) * 1981-10-29 1983-05-04 Nec Corp Master slice semiconductor integrated circuit device
JPH0140499B2 (en) * 1981-10-29 1989-08-29 Nippon Electric Co
JPS58139445A (en) * 1982-02-15 1983-08-18 Nec Corp Semiconductor integrated circuit device
JPH0250626B2 (en) * 1982-02-15 1990-11-02 Nippon Electric Co
JPH06112447A (en) * 1992-11-13 1994-04-22 Seiko Epson Corp Semiconductor device
US8407539B2 (en) 2009-03-03 2013-03-26 Renesas Electronics Corporation Semiconductor device test circuit, semiconductor device, and its manufacturing method

Also Published As

Publication number Publication date
JPH0120537B2 (en) 1989-04-17

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