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JPS5593343A - Multi-frame synchronizing system - Google Patents

Multi-frame synchronizing system

Info

Publication number
JPS5593343A
JPS5593343A JP90979A JP90979A JPS5593343A JP S5593343 A JPS5593343 A JP S5593343A JP 90979 A JP90979 A JP 90979A JP 90979 A JP90979 A JP 90979A JP S5593343 A JPS5593343 A JP S5593343A
Authority
JP
Japan
Prior art keywords
error
signal line
csep
delivered
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP90979A
Other languages
Japanese (ja)
Other versions
JPS5911222B2 (en
Inventor
Satoru Kawarada
Kouichi Banmoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP90979A priority Critical patent/JPS5911222B2/en
Publication of JPS5593343A publication Critical patent/JPS5593343A/en
Publication of JPS5911222B2 publication Critical patent/JPS5911222B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To avoid to reduce the effective capacity of transmission, by performing recognition of multi-frame section through the use of error judgement result of reception message, after the establishment of synchronism at the reception side. CONSTITUTION:The time sharing multiplex transmission line Hs is connected to the digital interface DTL, and the information pulse train reproduced is delivered to the time sharing exchanger switch frame TD-SWF and the control signal separation circuit CSEP via the signal line S1. The data message and error detection code separated in the separation circuit CSEP are delivered to the shift register SR in 40 bits sequentially via the signal line S2. The output of the error detection circuit FDE is inputted to the control processor CCP and the data message if judged as error presence, is abolished and if the judgement of error presence is continued, the shift register transfer pulse is delayed by one frame via the signal line S5 to take synchronism.
JP90979A 1979-01-06 1979-01-06 Multi-frame synchronization method Expired JPS5911222B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP90979A JPS5911222B2 (en) 1979-01-06 1979-01-06 Multi-frame synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP90979A JPS5911222B2 (en) 1979-01-06 1979-01-06 Multi-frame synchronization method

Publications (2)

Publication Number Publication Date
JPS5593343A true JPS5593343A (en) 1980-07-15
JPS5911222B2 JPS5911222B2 (en) 1984-03-14

Family

ID=11486795

Family Applications (1)

Application Number Title Priority Date Filing Date
JP90979A Expired JPS5911222B2 (en) 1979-01-06 1979-01-06 Multi-frame synchronization method

Country Status (1)

Country Link
JP (1) JPS5911222B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5791052A (en) * 1980-09-11 1982-06-07 Western Electric Co Fleming circuit
JPS5791053A (en) * 1980-09-11 1982-06-07 Western Electric Co Fleming circuit
JPH01160138A (en) * 1987-12-17 1989-06-23 Fujitsu Ltd Channel transmission system for message in exchange

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5791052A (en) * 1980-09-11 1982-06-07 Western Electric Co Fleming circuit
JPS5791053A (en) * 1980-09-11 1982-06-07 Western Electric Co Fleming circuit
JPH0288352U (en) * 1980-09-11 1990-07-12
JPH0288353U (en) * 1980-09-11 1990-07-12
JPH01160138A (en) * 1987-12-17 1989-06-23 Fujitsu Ltd Channel transmission system for message in exchange

Also Published As

Publication number Publication date
JPS5911222B2 (en) 1984-03-14

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