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JPS5582358A - Error collection system of central processing unit - Google Patents

Error collection system of central processing unit

Info

Publication number
JPS5582358A
JPS5582358A JP13829178A JP13829178A JPS5582358A JP S5582358 A JPS5582358 A JP S5582358A JP 13829178 A JP13829178 A JP 13829178A JP 13829178 A JP13829178 A JP 13829178A JP S5582358 A JPS5582358 A JP S5582358A
Authority
JP
Japan
Prior art keywords
cpu1
cpu
memory
latch
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13829178A
Other languages
Japanese (ja)
Other versions
JPS603223B2 (en
Inventor
Yasuo Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53138291A priority Critical patent/JPS603223B2/en
Publication of JPS5582358A publication Critical patent/JPS5582358A/en
Publication of JPS603223B2 publication Critical patent/JPS603223B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To perform log-out of a CPU in a simple method by providing an interface mechanism, which connects the CPU and a service processor, independently of the CPU and writing the state of the CPU in a memory provided in this mechanism.
CONSTITUTION: Between one or plural CPUs1 and service processor 3 for system control and maintenance service, interface mechanism 2 is provided independently of CPU1. This mechanism 2 is provided with memory 6 and address register 7. When CPU1 generates a error, CPU1 reports occurrence to mechanism 2 and stops its own clock. Then, address register 7 in mechanism 2 transmits a write address to memory 6 and a latch selection address and writes one-byte information from CPU1 into a position designated in memory 6 and writes latch information successively and reports the latch information write completion to CPU1 when the write of latch information is completed.
COPYRIGHT: (C)1980,JPO&Japio
JP53138291A 1978-11-09 1978-11-09 Central processing unit error collection method Expired JPS603223B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53138291A JPS603223B2 (en) 1978-11-09 1978-11-09 Central processing unit error collection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53138291A JPS603223B2 (en) 1978-11-09 1978-11-09 Central processing unit error collection method

Publications (2)

Publication Number Publication Date
JPS5582358A true JPS5582358A (en) 1980-06-21
JPS603223B2 JPS603223B2 (en) 1985-01-26

Family

ID=15218449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53138291A Expired JPS603223B2 (en) 1978-11-09 1978-11-09 Central processing unit error collection method

Country Status (1)

Country Link
JP (1) JPS603223B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994153A (en) * 1982-11-22 1984-05-30 Fujitsu Ltd Computer device
JPS6273341A (en) * 1985-09-27 1987-04-04 Hitachi Ltd Information processor
JPS6425254A (en) * 1987-07-21 1989-01-27 Hitachi Ltd Trouble information collecting device for processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0370808A (en) * 1989-08-08 1991-03-26 Nippondenso Co Ltd Exhaust gas purifying facility for diesel engine

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5994153A (en) * 1982-11-22 1984-05-30 Fujitsu Ltd Computer device
JPS6273341A (en) * 1985-09-27 1987-04-04 Hitachi Ltd Information processor
JPS6425254A (en) * 1987-07-21 1989-01-27 Hitachi Ltd Trouble information collecting device for processor

Also Published As

Publication number Publication date
JPS603223B2 (en) 1985-01-26

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