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JPS556667A - Data transfer system with buffer register - Google Patents

Data transfer system with buffer register

Info

Publication number
JPS556667A
JPS556667A JP7956578A JP7956578A JPS556667A JP S556667 A JPS556667 A JP S556667A JP 7956578 A JP7956578 A JP 7956578A JP 7956578 A JP7956578 A JP 7956578A JP S556667 A JPS556667 A JP S556667A
Authority
JP
Japan
Prior art keywords
banks
buffer register
byte
address information
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7956578A
Other languages
Japanese (ja)
Inventor
Takashi Owaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7956578A priority Critical patent/JPS556667A/en
Publication of JPS556667A publication Critical patent/JPS556667A/en
Pending legal-status Critical Current

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  • Memory System (AREA)

Abstract

PURPOSE:To simplify a process by sectioning a buffer register into banks to which independent access is attainable, by reading each bank by word address information inputted via a gate circuit and by aligning byte data by a byte alignment circuit. CONSTITUTION:Buffer register 1 of channel 5 which reads P-type data, aligns bytes by byte alignment circuit 7 and then transfers the data to main memory unit 4 via transfer bus 14 with bus width equivalent to P bytes is sectioned into buffer register banks 1-0 to 1-3 to which independent access is attainable. Further, gates 9 to 12 which put selectively the word address information of word address register 8 in a through state, plus-''1'' state or minus-''1'' state are provided corresponding to banks 1-0 to 1-3, the address information is applied to banks 1-0 to 1-3 via gates 9 to 12 for access, and byte data read out are byte-aligned by circuit 7.
JP7956578A 1978-06-30 1978-06-30 Data transfer system with buffer register Pending JPS556667A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7956578A JPS556667A (en) 1978-06-30 1978-06-30 Data transfer system with buffer register

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7956578A JPS556667A (en) 1978-06-30 1978-06-30 Data transfer system with buffer register

Publications (1)

Publication Number Publication Date
JPS556667A true JPS556667A (en) 1980-01-18

Family

ID=13693523

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7956578A Pending JPS556667A (en) 1978-06-30 1978-06-30 Data transfer system with buffer register

Country Status (1)

Country Link
JP (1) JPS556667A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043742A (en) * 1983-08-19 1985-03-08 Toshiba Corp Reading circuit of variable length data
JPS6285326A (en) * 1985-10-09 1987-04-18 Nec Corp Register file system
JPS6288031A (en) * 1985-10-14 1987-04-22 Nec Corp Register filing system
EP1282862B1 (en) * 1999-12-28 2010-04-14 Intel Corporation Distributed memory control and bandwidth optimization

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423439A (en) * 1977-07-25 1979-02-22 Ibm Channel data buffer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5423439A (en) * 1977-07-25 1979-02-22 Ibm Channel data buffer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043742A (en) * 1983-08-19 1985-03-08 Toshiba Corp Reading circuit of variable length data
JPS6285326A (en) * 1985-10-09 1987-04-18 Nec Corp Register file system
JPS6288031A (en) * 1985-10-14 1987-04-22 Nec Corp Register filing system
EP1282862B1 (en) * 1999-12-28 2010-04-14 Intel Corporation Distributed memory control and bandwidth optimization

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