JPS555542A - Rewritable program logic array - Google Patents
Rewritable program logic arrayInfo
- Publication number
- JPS555542A JPS555542A JP7841178A JP7841178A JPS555542A JP S555542 A JPS555542 A JP S555542A JP 7841178 A JP7841178 A JP 7841178A JP 7841178 A JP7841178 A JP 7841178A JP S555542 A JPS555542 A JP S555542A
- Authority
- JP
- Japan
- Prior art keywords
- row
- write
- pattern
- row line
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
- H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
Landscapes
- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To realize the rewritable programmable logic array constituted with rewritable memory cell groups located at the cross points of row and column lines and connected on the both lines. CONSTITUTION:On the cross points of the row and column lines, the memory cell group 12 of current switching type are located. When write-in is made on the cross points on the row lines W2<(1)>, the write-in pattern 11011111 is given from the decoder circuit 114 to the row line 112. This logic pattern is the address designating the row line W2<(1)> in the array. Next, the pattern to be written in is stored in the write-in and readout circuit 14 to write in to the address given with the activation of the decoder circuit 114. At readout, the row line 112 is activated via the decode circuit 111 and it is performed by taking logic 0 for one row line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7841178A JPS555542A (en) | 1978-06-27 | 1978-06-27 | Rewritable program logic array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7841178A JPS555542A (en) | 1978-06-27 | 1978-06-27 | Rewritable program logic array |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS555542A true JPS555542A (en) | 1980-01-16 |
Family
ID=13661287
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7841178A Pending JPS555542A (en) | 1978-06-27 | 1978-06-27 | Rewritable program logic array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS555542A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0038947A2 (en) * | 1980-04-25 | 1981-11-04 | Ibm Deutschland Gmbh | Programmable logic array |
JPS57132426A (en) * | 1980-12-29 | 1982-08-16 | Ibm | Dynamically reprogrammable logic array system |
US4499238A (en) * | 1981-05-23 | 1985-02-12 | Nippon Steel Chemical Co., Ltd. | Thermoplastic resin products having pearl-like luster |
JPH0628152A (en) * | 1992-07-06 | 1994-02-04 | Nec Corp | Data input type logical operation unit |
-
1978
- 1978-06-27 JP JP7841178A patent/JPS555542A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0038947A2 (en) * | 1980-04-25 | 1981-11-04 | Ibm Deutschland Gmbh | Programmable logic array |
JPS57132426A (en) * | 1980-12-29 | 1982-08-16 | Ibm | Dynamically reprogrammable logic array system |
JPH022172B2 (en) * | 1980-12-29 | 1990-01-17 | Intaanashonaru Bijinesu Mashiinzu Corp | |
US4499238A (en) * | 1981-05-23 | 1985-02-12 | Nippon Steel Chemical Co., Ltd. | Thermoplastic resin products having pearl-like luster |
JPH0628152A (en) * | 1992-07-06 | 1994-02-04 | Nec Corp | Data input type logical operation unit |
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