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JPS554191A - Binary/quad conversion system - Google Patents

Binary/quad conversion system

Info

Publication number
JPS554191A
JPS554191A JP7790578A JP7790578A JPS554191A JP S554191 A JPS554191 A JP S554191A JP 7790578 A JP7790578 A JP 7790578A JP 7790578 A JP7790578 A JP 7790578A JP S554191 A JPS554191 A JP S554191A
Authority
JP
Japan
Prior art keywords
signal
binary
circuit
quad
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7790578A
Other languages
Japanese (ja)
Other versions
JPS6049388B2 (en
Inventor
Koichi Honma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP53077905A priority Critical patent/JPS6049388B2/en
Publication of JPS554191A publication Critical patent/JPS554191A/en
Publication of JPS6049388B2 publication Critical patent/JPS6049388B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To attain easily bit synchronization at a demodulator side by modulating signals at a half clock frequency before binary/quad conversion.
CONSTITUTION: An input signal applied to input terminal 11 has unneeded components removed by filter circuir 12 and is applied to comparator 13 and bit synchronizous regenerating circuit 14. Synchronizing signals regenerated by this regenerating circuit 14 are applied to comparator 13, where they are synchronized and quad values are discriminated. This signal is applied to converter circuit 15 and converted into a binary signal. This binary signal and the bit synchronizing signal divided by FF16 are both applied to OR-ELSE circuit 17, so that a delta-modulated signal will be extracted. This signal is applied to demodulation circuit 18, where it is demodulated into an analog signal. Synchronization can therefore be attained easily by the demodulator.
COPYRIGHT: (C)1980,JPO&Japio
JP53077905A 1978-06-26 1978-06-26 Signal conversion method Expired JPS6049388B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53077905A JPS6049388B2 (en) 1978-06-26 1978-06-26 Signal conversion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53077905A JPS6049388B2 (en) 1978-06-26 1978-06-26 Signal conversion method

Publications (2)

Publication Number Publication Date
JPS554191A true JPS554191A (en) 1980-01-12
JPS6049388B2 JPS6049388B2 (en) 1985-11-01

Family

ID=13647082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53077905A Expired JPS6049388B2 (en) 1978-06-26 1978-06-26 Signal conversion method

Country Status (1)

Country Link
JP (1) JPS6049388B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388979A (en) * 1986-10-01 1988-04-20 Pioneer Electronic Corp Video disk recording and reproducing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6388979A (en) * 1986-10-01 1988-04-20 Pioneer Electronic Corp Video disk recording and reproducing device

Also Published As

Publication number Publication date
JPS6049388B2 (en) 1985-11-01

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