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JPS5523677A - Selection circuit for delay time - Google Patents

Selection circuit for delay time

Info

Publication number
JPS5523677A
JPS5523677A JP9706278A JP9706278A JPS5523677A JP S5523677 A JPS5523677 A JP S5523677A JP 9706278 A JP9706278 A JP 9706278A JP 9706278 A JP9706278 A JP 9706278A JP S5523677 A JPS5523677 A JP S5523677A
Authority
JP
Japan
Prior art keywords
signal
signals
delay
phase difference
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9706278A
Other languages
Japanese (ja)
Inventor
Yoshinori Chiwaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9706278A priority Critical patent/JPS5523677A/en
Publication of JPS5523677A publication Critical patent/JPS5523677A/en
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To enable to select an arbitrary delay time, by providing the delay signal generation means, means selecting one of the delay signals with the designation externally, and means detecting the phase difference between the selected signal and the reference signal.
CONSTITUTION: The circuit consists of the delay circuit 1 outputting delay signals D1 to D8 to the input signal S1, selection signal 2 selecting one of the eight delay signals with the selection signals S1 to S4 externally, and phase difference detection and hold circuit 10 which detects the phase difference between the reference signal S5 and the output signal S8 from the circuit 2 by the signal S1, and outputs arbitrary delay signals S9 to S12 in the combination of the signals S2 to S4. In the circuit 10, the signal S7 of the exclusive logical sum 3 between the signals S5 and S8 indicates the phase difference between the signals S5 and S8 in pulse width, and the clock S6 outputted with the clock timing signal S12 in the state of logic 1 is given to the count signal of the counter 5 via the AND circuits 6 and 4 to count the signal S7 and the output signals S9 to S12 of the phase difference with the reference signal S5.
COPYRIGHT: (C)1980,JPO&Japio
JP9706278A 1978-08-08 1978-08-08 Selection circuit for delay time Pending JPS5523677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9706278A JPS5523677A (en) 1978-08-08 1978-08-08 Selection circuit for delay time

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9706278A JPS5523677A (en) 1978-08-08 1978-08-08 Selection circuit for delay time

Publications (1)

Publication Number Publication Date
JPS5523677A true JPS5523677A (en) 1980-02-20

Family

ID=14182154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9706278A Pending JPS5523677A (en) 1978-08-08 1978-08-08 Selection circuit for delay time

Country Status (1)

Country Link
JP (1) JPS5523677A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62253223A (en) * 1986-04-25 1987-11-05 Toshiba Corp Counter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62253223A (en) * 1986-04-25 1987-11-05 Toshiba Corp Counter

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