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JPS55162101A - Signal setter - Google Patents

Signal setter

Info

Publication number
JPS55162101A
JPS55162101A JP6894379A JP6894379A JPS55162101A JP S55162101 A JPS55162101 A JP S55162101A JP 6894379 A JP6894379 A JP 6894379A JP 6894379 A JP6894379 A JP 6894379A JP S55162101 A JPS55162101 A JP S55162101A
Authority
JP
Japan
Prior art keywords
frequency
output
value
increase
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6894379A
Other languages
Japanese (ja)
Inventor
Shunji Mori
Yoshimasa Asada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6894379A priority Critical patent/JPS55162101A/en
Publication of JPS55162101A publication Critical patent/JPS55162101A/en
Pending legal-status Critical Current

Links

Landscapes

  • Feedback Control In General (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE: To make it possible to set the frequency of a signal automatically without using a mechanical part by adding or subtracting the output of a pulse oscillator to or from the contents of a reversible counter, by comparing an output signal frequency to a set frequency, and by exercising control so that the output frequency will be below the set value.
CONSTITUTION: With increase switch 14 ON, reversible counter 19 is applied with a pulse signal from pulse oscillator 17 and the output of D/A converter 23 increases. The increase speed at that time depends upon the oscillation frequency of pulse oscillator 17, an increase or decrease in speed can be set by frequency setter 18 and comparator 22A checks whether the output signal is within the upper limit of the set value or not. When exceeding the set value, the output value is set to its upper limit value by reversible counter 19 without reference to an input via increase switch 14. With decrease switch 15 ON, the output signal, when exceeding the set value, is similarly set to its lower limit value. Consequently, limit-frequency setting and moving speeds can freely be set without using a mechanical part and automatic frequency setting comes into effect.
COPYRIGHT: (C)1980,JPO&Japio
JP6894379A 1979-06-04 1979-06-04 Signal setter Pending JPS55162101A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6894379A JPS55162101A (en) 1979-06-04 1979-06-04 Signal setter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6894379A JPS55162101A (en) 1979-06-04 1979-06-04 Signal setter

Publications (1)

Publication Number Publication Date
JPS55162101A true JPS55162101A (en) 1980-12-17

Family

ID=13388248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6894379A Pending JPS55162101A (en) 1979-06-04 1979-06-04 Signal setter

Country Status (1)

Country Link
JP (1) JPS55162101A (en)

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