JPS551623A - Digital signal processing unit - Google Patents

Abstract

PURPOSE:To change the arrangement of digital signals in a simple constitution by controlling a matrix RAM so that address advancing methods at a write time and a read time are performed by different operations. CONSTITUTION:Bit counter CB counts bit clocks to generate work clocks, and l- bit binary counter CW1 generates an X address code counted up one by one. Meanwhile, m-bit and (k-m)-bit binary counters CW2 and CW3 are connected in series to counter CW1, and word clocks of counter CB and carry signals from counter CW1 are applied to counter CW3, and the Y address code dependent upon counters CW2 and CW3 is counted up at every 2<m> interval, and a matrix address of a RAM is addressed after a prescribed time interval delay, thus writing the work code. When this RAM is read out while counting up successively address information, the PCM code, etc., are compressed and read out, so that the arrangement of PCM signals such as a compression arrangement can be changed easily by a simple constitution where many shift registers are not required.