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JPS551676A - Memory protect system - Google Patents

Memory protect system

Info

Publication number
JPS551676A
JPS551676A JP7520978A JP7520978A JPS551676A JP S551676 A JPS551676 A JP S551676A JP 7520978 A JP7520978 A JP 7520978A JP 7520978 A JP7520978 A JP 7520978A JP S551676 A JPS551676 A JP S551676A
Authority
JP
Japan
Prior art keywords
address
upper rank
register
memory
rank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7520978A
Other languages
Japanese (ja)
Inventor
Nobuyuki Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP7520978A priority Critical patent/JPS551676A/en
Publication of JPS551676A publication Critical patent/JPS551676A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B9/00—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor
    • G11B9/06—Recording or reproducing using a method not covered by one of the main groups G11B3/00 - G11B7/00; Record carriers therefor using record carriers having variable electrical capacitance; Record carriers therefor
    • G11B9/061—Record carriers characterised by their structure or form or by the selection of the material; Apparatus or processes specially adapted for the manufacture of record carriers

Landscapes

  • Storage Device Security (AREA)

Abstract

PURPOSE:To protect the content area, by fixing the upper rank of the memory address at specific program so that only specific memory area can be accessed and other areas can not be accessed. CONSTITUTION:The address registers 1, 2 respectively output the upper rank A and the upper rank B of the memory address to the selector 4, and the address register 3 outputs the lower rank of the memory address. With this state, when a priority instruction is transferred to the flip flop 5(FF) and set in normal memory access for adjustment or the like, the selector 4 is operated and the upper rank A of the register 1 is outputted. When the adjustment is finished, FF5 is reset and upper rank B is selected and outputted from the register 2. In this case, the address register 2 is fixed and the address upper rank bit is fixed until the execution of the specific program is finished.
JP7520978A 1978-06-21 1978-06-21 Memory protect system Pending JPS551676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7520978A JPS551676A (en) 1978-06-21 1978-06-21 Memory protect system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7520978A JPS551676A (en) 1978-06-21 1978-06-21 Memory protect system

Publications (1)

Publication Number Publication Date
JPS551676A true JPS551676A (en) 1980-01-08

Family

ID=13569568

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7520978A Pending JPS551676A (en) 1978-06-21 1978-06-21 Memory protect system

Country Status (1)

Country Link
JP (1) JPS551676A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227838A (en) * 1985-07-29 1987-02-05 Nec Corp Buffer controller of information processor
JPS6246356A (en) * 1985-08-26 1987-02-28 Hitachi Ltd Cpu board
JPS62126448A (en) * 1985-11-27 1987-06-08 Fuji Electric Co Ltd Memory management/protection method
JPH01140255A (en) * 1987-11-26 1989-06-01 Matsushita Electric Ind Co Ltd Memory protecting method
JPH036685A (en) * 1989-06-02 1991-01-14 Omron Corp Article discriminating system

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227838A (en) * 1985-07-29 1987-02-05 Nec Corp Buffer controller of information processor
JPS6246356A (en) * 1985-08-26 1987-02-28 Hitachi Ltd Cpu board
JPS62126448A (en) * 1985-11-27 1987-06-08 Fuji Electric Co Ltd Memory management/protection method
JPH01140255A (en) * 1987-11-26 1989-06-01 Matsushita Electric Ind Co Ltd Memory protecting method
JPH036685A (en) * 1989-06-02 1991-01-14 Omron Corp Article discriminating system

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