JPS55164942A - Division circuit - Google Patents

Abstract

PURPOSE: To speed up the operation and to make small the size of division circuit, by performing the operation of n bits by n-times clock and limiting the division of an integer in several-bits.

CONSTITUTION: Dividend (a) is input to the A register 1 and the divider (b) is to the B register 2, so that 2ⁿ,^b, 2^n-1,^b...2⁰,^b can be input respectively to the gate groups 3_nW3₀ connected to the register 2. The gate groups 3_nW3₀ are sequentially open in the order of input for output, they are respectively compared with the dividend (a) in the register 1, and when a ≥2ⁿ,^b, 2^n-1,^b...2⁰,^b is established, 1 is set to the shift register 6 with the output of the circuit 4, and the subtraction circuit 5 is operated to execute the respective operations and the results are fed to the register 1. On the other hand, in case of n<2ⁿ,^b, 2^n-1,^b...2⁰,^b, 0 is set to the register 6, the dividend (a) is fed again to the register 1 via the circuit 5 as it is, this operation is repeated each digit, quotinents P_n, P_n-1...P₀ are set to the register 6, and residual is fed to the register 1.

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