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JPS55158760A - Signal sampling system - Google Patents

Signal sampling system

Info

Publication number
JPS55158760A
JPS55158760A JP6564979A JP6564979A JPS55158760A JP S55158760 A JPS55158760 A JP S55158760A JP 6564979 A JP6564979 A JP 6564979A JP 6564979 A JP6564979 A JP 6564979A JP S55158760 A JPS55158760 A JP S55158760A
Authority
JP
Japan
Prior art keywords
signal
comparator
integrator
output
integral value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6564979A
Other languages
Japanese (ja)
Inventor
Kunihiro Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6564979A priority Critical patent/JPS55158760A/en
Publication of JPS55158760A publication Critical patent/JPS55158760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—DC level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To ensure the assured sampling although the state of the signal is not good, by integrating the sampled digital signal and then deciding the presence of the signal in case the integral value exceeds the fixed threshold level. CONSTITUTION:Demodulation signal B is converted into binary coded signal C via comparator 9a and then integrated through integrator 9f. Integrator 9f performs the integration only while signal C is at the high level. And the output of comparator 9g is set to the high level only when the integral value exceeds the threshold level. And the integral value is reset by sampling pulse D which is delivered first and only when the output of comparator 9g is at the high level. Thus output F of integrator 9f varies according to the relation between signal C and pulse D. In this connection, both the upper and lower limits are selected properly for the pulse duration and against the isolated bit information, and at the same time integrator 9f and the comparator are constituted properly. As a result, sampling output E' which corresponds accurately the binary coded signal is obtained from D-type FF9d.
JP6564979A 1979-05-29 1979-05-29 Signal sampling system Pending JPS55158760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6564979A JPS55158760A (en) 1979-05-29 1979-05-29 Signal sampling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6564979A JPS55158760A (en) 1979-05-29 1979-05-29 Signal sampling system

Publications (1)

Publication Number Publication Date
JPS55158760A true JPS55158760A (en) 1980-12-10

Family

ID=13293058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6564979A Pending JPS55158760A (en) 1979-05-29 1979-05-29 Signal sampling system

Country Status (1)

Country Link
JP (1) JPS55158760A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042964A (en) * 1983-08-19 1985-03-07 Futaba Corp Code regenerating device
WO2020235090A1 (en) * 2019-05-23 2020-11-26 三菱電機株式会社 Reception circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6042964A (en) * 1983-08-19 1985-03-07 Futaba Corp Code regenerating device
WO2020235090A1 (en) * 2019-05-23 2020-11-26 三菱電機株式会社 Reception circuit

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