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JPS55157180A - Cash memory - Google Patents

Cash memory

Info

Publication number
JPS55157180A
JPS55157180A JP6472979A JP6472979A JPS55157180A JP S55157180 A JPS55157180 A JP S55157180A JP 6472979 A JP6472979 A JP 6472979A JP 6472979 A JP6472979 A JP 6472979A JP S55157180 A JPS55157180 A JP S55157180A
Authority
JP
Japan
Prior art keywords
memory
data
address
cash
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6472979A
Other languages
Japanese (ja)
Inventor
Eiichi Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP6472979A priority Critical patent/JPS55157180A/en
Publication of JPS55157180A publication Critical patent/JPS55157180A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To obtain a cash memory which can perform the operation test in the normal operation, by permitting only the read operation of the cash memory by a monitor enable signal when test sequence is required.
CONSTITUTION: When monitor enable signal MTE2 from CPU11 is turned off, data-in signal DIN output from address circuit 26 of cash memory 14 is inverted to the low level, and cash memory control unit 22 and data memory 21 are controlled by this signal DIN, and write and rewrite of data into memory 21 are inhibited, and only read is permitted. Consequently, even if data of address C in memory 13 is rewritten to address A through CPU11, this data is not stored in memory 21, and data before rewrite of address A read from address B of memory 13 is compared with the same data simultaneously with the read of data of address A memory 13 before rewrite stored in memory 21 by CPU11, and thus, the operation test of the cash memory is performed completely while performing the normal operation.
COPYRIGHT: (C)1980,JPO&Japio
JP6472979A 1979-05-25 1979-05-25 Cash memory Pending JPS55157180A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6472979A JPS55157180A (en) 1979-05-25 1979-05-25 Cash memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6472979A JPS55157180A (en) 1979-05-25 1979-05-25 Cash memory

Publications (1)

Publication Number Publication Date
JPS55157180A true JPS55157180A (en) 1980-12-06

Family

ID=13266521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6472979A Pending JPS55157180A (en) 1979-05-25 1979-05-25 Cash memory

Country Status (1)

Country Link
JP (1) JPS55157180A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450142A (en) * 1987-08-19 1989-02-27 Nec Corp Information processor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6450142A (en) * 1987-08-19 1989-02-27 Nec Corp Information processor

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