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JPS55127737A - Noise elimination circuit - Google Patents

Noise elimination circuit

Info

Publication number
JPS55127737A
JPS55127737A JP3528679A JP3528679A JPS55127737A JP S55127737 A JPS55127737 A JP S55127737A JP 3528679 A JP3528679 A JP 3528679A JP 3528679 A JP3528679 A JP 3528679A JP S55127737 A JPS55127737 A JP S55127737A
Authority
JP
Japan
Prior art keywords
level
signal
components
limiter
waveform distortion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3528679A
Other languages
Japanese (ja)
Other versions
JPS6214967B2 (en
Inventor
Takafumi Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP3528679A priority Critical patent/JPS55127737A/en
Publication of JPS55127737A publication Critical patent/JPS55127737A/en
Publication of JPS6214967B2 publication Critical patent/JPS6214967B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Noise Elimination (AREA)

Abstract

PURPOSE: To restrain waveform distortion of the output signal to a minimum to eliminate noise maximally, by varying a prescribed level according to the level of the input signal in case that components over the prescribed level out of high- band components are added to low-band components of the input signal.
CONSTITUTION: In the noise elimination circuit to reduce waveform distortion of signal components, input level ±V is varied according to the level of input signal SI by the I/O characteristic of limiter 5. That is, when the level of signal SI is large, level ±V1 of limiter 5 is made small. In this case, small-level signal components out of high-band components SH1 pass through limiter 5 and are synthesized with components SL of signal SL, which passed through LPF2, by 3, so that waveform distortion of output signal SO can be restrained. Meanwhile, when the level of signal SI is small, the level of ±V1 of limiter 5 is made large to eliminate sufficiently noise components of high-band components SH1. As a result, waveform distortion of the output signal is restrained to a minimum to eliminate noise maxiamlly.
COPYRIGHT: (C)1980,JPO&Japio
JP3528679A 1979-03-26 1979-03-26 Noise elimination circuit Granted JPS55127737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3528679A JPS55127737A (en) 1979-03-26 1979-03-26 Noise elimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3528679A JPS55127737A (en) 1979-03-26 1979-03-26 Noise elimination circuit

Publications (2)

Publication Number Publication Date
JPS55127737A true JPS55127737A (en) 1980-10-02
JPS6214967B2 JPS6214967B2 (en) 1987-04-04

Family

ID=12437521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3528679A Granted JPS55127737A (en) 1979-03-26 1979-03-26 Noise elimination circuit

Country Status (1)

Country Link
JP (1) JPS55127737A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58188939A (en) * 1982-02-19 1983-11-04 ア−ウイン・ドウナス Receiver intensified in selection degree
JPS60143028A (en) * 1983-12-29 1985-07-29 Matsushita Electric Ind Co Ltd Noise reducing device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318124A (en) * 1972-06-19 1978-02-20 Sargent Industries Refuse collecting apparatus

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5318124A (en) * 1972-06-19 1978-02-20 Sargent Industries Refuse collecting apparatus

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58188939A (en) * 1982-02-19 1983-11-04 ア−ウイン・ドウナス Receiver intensified in selection degree
JPH0580847B2 (en) * 1982-02-19 1993-11-10 Donath Erwin
JPS60143028A (en) * 1983-12-29 1985-07-29 Matsushita Electric Ind Co Ltd Noise reducing device
JPH0556051B2 (en) * 1983-12-29 1993-08-18 Matsushita Electric Ind Co Ltd

Also Published As

Publication number Publication date
JPS6214967B2 (en) 1987-04-04

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