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JPS5483724A - Processor for display - Google Patents

Processor for display

Info

Publication number
JPS5483724A
JPS5483724A JP15155277A JP15155277A JPS5483724A JP S5483724 A JPS5483724 A JP S5483724A JP 15155277 A JP15155277 A JP 15155277A JP 15155277 A JP15155277 A JP 15155277A JP S5483724 A JPS5483724 A JP S5483724A
Authority
JP
Japan
Prior art keywords
output
computing
switch
alu
function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15155277A
Other languages
Japanese (ja)
Inventor
Takeyasu Morigami
Yoshikatsu Matsui
Eiji Yonemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15155277A priority Critical patent/JPS5483724A/en
Publication of JPS5483724A publication Critical patent/JPS5483724A/en
Pending legal-status Critical Current

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  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To shorten a computing time by dividing the computing unit of an arithmetic part controlled by microprograms and by operating them in parallel independently.
CONSTITUTION: To compute coordinate positions Xn and Yn of a display point, the display processor is operated with switch 24 opened when variables X and Y can be separated completely. In this case, since microprogram 30 can assign different kinds of arithmetic by signals L1 and L2, computing units ALU(1)23, and ALU(2)232 function as two independent processors and Xn and Yn are calculated independently. Further, when switch 24 is closed through the assignment of carrier control signal L3, the outputs of the computing units are mixed into a (m+n)-bit output, the function of a (m+n)-bit processor becomes effective, and its output is sent out to output buffer 14 and register 21.
COPYRIGHT: (C)1979,JPO&Japio
JP15155277A 1977-12-16 1977-12-16 Processor for display Pending JPS5483724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15155277A JPS5483724A (en) 1977-12-16 1977-12-16 Processor for display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15155277A JPS5483724A (en) 1977-12-16 1977-12-16 Processor for display

Publications (1)

Publication Number Publication Date
JPS5483724A true JPS5483724A (en) 1979-07-04

Family

ID=15521005

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15155277A Pending JPS5483724A (en) 1977-12-16 1977-12-16 Processor for display

Country Status (1)

Country Link
JP (1) JPS5483724A (en)

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