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JPS5467337A - Video memory unit - Google Patents

Video memory unit

Info

Publication number
JPS5467337A
JPS5467337A JP13449377A JP13449377A JPS5467337A JP S5467337 A JPS5467337 A JP S5467337A JP 13449377 A JP13449377 A JP 13449377A JP 13449377 A JP13449377 A JP 13449377A JP S5467337 A JPS5467337 A JP S5467337A
Authority
JP
Japan
Prior art keywords
data
memory
signal
address
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13449377A
Other languages
Japanese (ja)
Other versions
JPS6040053B2 (en
Inventor
Takeshi Arakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP52134493A priority Critical patent/JPS6040053B2/en
Publication of JPS5467337A publication Critical patent/JPS5467337A/en
Publication of JPS6040053B2 publication Critical patent/JPS6040053B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Image Input (AREA)
  • Digital Computer Display Output (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To perform write-in and readout of the video memory in high speed and with a simple circuit constitution, by locating the memory card so that the card address is different each other and reading out the data output and outputting it to the data bus with the readoud data register.
CONSTITUTION: The AND circuit 20 receives the signal of the card address bus 200 and generates the card selection signal with the card address signal corresponded. Further, the memory 10 memorizes the output signal 204 of the write-in data register to the address designated with the signal 201 of the address bus and sets the memory data designated and read out with the address signal of the memory 10 with the readout data set signal 104 of the control bus 206. Then, the memory cards are located so that the card address is different each other, and the readout data reigster 12 outputs the data output to the readout data bus. Accordingly, the write-in and readout of the video memory can be made with a simple circuit constitution and in high speed.
COPYRIGHT: (C)1979,JPO&Japio
JP52134493A 1977-11-08 1977-11-08 image storage device Expired JPS6040053B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52134493A JPS6040053B2 (en) 1977-11-08 1977-11-08 image storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52134493A JPS6040053B2 (en) 1977-11-08 1977-11-08 image storage device

Publications (2)

Publication Number Publication Date
JPS5467337A true JPS5467337A (en) 1979-05-30
JPS6040053B2 JPS6040053B2 (en) 1985-09-09

Family

ID=15129600

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52134493A Expired JPS6040053B2 (en) 1977-11-08 1977-11-08 image storage device

Country Status (1)

Country Link
JP (1) JPS6040053B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574670A (en) * 1980-06-11 1982-01-11 Chubu Nippon Hoso Kk Picture memory control system
JPS5880737A (en) * 1981-10-20 1983-05-14 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Interactive text processing system
JPH05205477A (en) * 1991-05-20 1993-08-13 Motorola Inc Randomly accessible memory having time overlap memory-access
JP2009531742A (en) * 2006-03-29 2009-09-03 テクトロニクス・インコーポレイテッド High speed rasterizer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574670A (en) * 1980-06-11 1982-01-11 Chubu Nippon Hoso Kk Picture memory control system
JPS5880737A (en) * 1981-10-20 1983-05-14 インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション Interactive text processing system
JPH05205477A (en) * 1991-05-20 1993-08-13 Motorola Inc Randomly accessible memory having time overlap memory-access
JP2009531742A (en) * 2006-03-29 2009-09-03 テクトロニクス・インコーポレイテッド High speed rasterizer

Also Published As

Publication number Publication date
JPS6040053B2 (en) 1985-09-09

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