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JPS5451340A - Data transmitter - Google Patents

Data transmitter

Info

Publication number
JPS5451340A
JPS5451340A JP11713377A JP11713377A JPS5451340A JP S5451340 A JPS5451340 A JP S5451340A JP 11713377 A JP11713377 A JP 11713377A JP 11713377 A JP11713377 A JP 11713377A JP S5451340 A JPS5451340 A JP S5451340A
Authority
JP
Japan
Prior art keywords
received
signal
clock
clock signal
long
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11713377A
Other languages
Japanese (ja)
Inventor
Hideaki Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11713377A priority Critical patent/JPS5451340A/en
Publication of JPS5451340A publication Critical patent/JPS5451340A/en
Pending legal-status Critical Current

Links

Landscapes

  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To correct the delay of a received clock and received data signal due to a long-distance cable, by inserting a delay circuit to the transmission clock signal at a terminal side.
CONSTITUTION: A clock signal received from electronic computer 1 arrives at terminal 3 while being delayed through long-distance cable 3. Transmitted data is outputted synchronizing with the rise signal of transmitted clock signal 10 outputted from delay circuit 8, and received data is sampled by the fall signal of the received clock inside electronic computer 1, so that the time lag due to the cable length will be eliminated artificially
COPYRIGHT: (C)1979,JPO&Japio
JP11713377A 1977-09-29 1977-09-29 Data transmitter Pending JPS5451340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11713377A JPS5451340A (en) 1977-09-29 1977-09-29 Data transmitter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11713377A JPS5451340A (en) 1977-09-29 1977-09-29 Data transmitter

Publications (1)

Publication Number Publication Date
JPS5451340A true JPS5451340A (en) 1979-04-23

Family

ID=14704255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11713377A Pending JPS5451340A (en) 1977-09-29 1977-09-29 Data transmitter

Country Status (1)

Country Link
JP (1) JPS5451340A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694858A (en) * 1979-12-28 1981-07-31 Mitsubishi Electric Corp Pulse duration time-division multiplex transmitter
JPS59221045A (en) * 1983-05-30 1984-12-12 Toshiba Corp Timing control system of data transmission and reception
JPS62145948A (en) * 1985-12-20 1987-06-30 Fujitsu Ltd Data sampling method
FR2635933A1 (en) * 1988-08-31 1990-03-02 Bull Sa METHOD FOR TRANSMITTING INFORMATION ON A BIDIRECTIONAL LINK AND DEVICE FOR IMPLEMENTING SAID METHOD

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694858A (en) * 1979-12-28 1981-07-31 Mitsubishi Electric Corp Pulse duration time-division multiplex transmitter
JPS59221045A (en) * 1983-05-30 1984-12-12 Toshiba Corp Timing control system of data transmission and reception
JPS62145948A (en) * 1985-12-20 1987-06-30 Fujitsu Ltd Data sampling method
FR2635933A1 (en) * 1988-08-31 1990-03-02 Bull Sa METHOD FOR TRANSMITTING INFORMATION ON A BIDIRECTIONAL LINK AND DEVICE FOR IMPLEMENTING SAID METHOD

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