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JPS5447537A - Bus data hysteresis storage system - Google Patents

Bus data hysteresis storage system

Info

Publication number
JPS5447537A
JPS5447537A JP11419977A JP11419977A JPS5447537A JP S5447537 A JPS5447537 A JP S5447537A JP 11419977 A JP11419977 A JP 11419977A JP 11419977 A JP11419977 A JP 11419977A JP S5447537 A JPS5447537 A JP S5447537A
Authority
JP
Japan
Prior art keywords
bus
data
memory
common
common bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11419977A
Other languages
Japanese (ja)
Inventor
Yasushi Ikeda
Junichi Tanahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11419977A priority Critical patent/JPS5447537A/en
Publication of JPS5447537A publication Critical patent/JPS5447537A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To secure and assured execution of the fault diagnosis or the fault repair by installing the data bus memory in correspondence to the common bus of the data processor and writing the information to indicate to or not to use the register address and the common bus which supplies and delivers the data into the region designated by the memory.
CONSTITUTION: Bus data memories 4-1 and 4-2 are installed corresponding to internal common buses 1-1 and 1-2 of the data processor; arithmetic unit 2 plus input/output register 3-1 and 3-2 are connected to common bus 1-1 and 1-2; and memory 4-1 and 4-2 are connected to bus 1-1 and 1-2. Then the information, indicating to or not to use bus 1-1 and 1-2 at the address and the microstep of the register which supplies and delivers the data obtained by decording the microorder given from control memory 5 through decorder 7, is written into memory 4-1 and 4-2. The contents of 4-1 and 4-2 are then read out through the diagnosis device, and the diagnosis is carried out via the hysteresis of common bus data
COPYRIGHT: (C)1979,JPO&Japio
JP11419977A 1977-09-22 1977-09-22 Bus data hysteresis storage system Pending JPS5447537A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11419977A JPS5447537A (en) 1977-09-22 1977-09-22 Bus data hysteresis storage system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11419977A JPS5447537A (en) 1977-09-22 1977-09-22 Bus data hysteresis storage system

Publications (1)

Publication Number Publication Date
JPS5447537A true JPS5447537A (en) 1979-04-14

Family

ID=14631676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11419977A Pending JPS5447537A (en) 1977-09-22 1977-09-22 Bus data hysteresis storage system

Country Status (1)

Country Link
JP (1) JPS5447537A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59133623A (en) * 1983-01-20 1984-08-01 Toshiba Corp Storage system of bus information log

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59133623A (en) * 1983-01-20 1984-08-01 Toshiba Corp Storage system of bus information log

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