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JPS54147765A - Frequency division circuit - Google Patents

Frequency division circuit

Info

Publication number
JPS54147765A
JPS54147765A JP5595278A JP5595278A JPS54147765A JP S54147765 A JPS54147765 A JP S54147765A JP 5595278 A JP5595278 A JP 5595278A JP 5595278 A JP5595278 A JP 5595278A JP S54147765 A JPS54147765 A JP S54147765A
Authority
JP
Japan
Prior art keywords
circuit
gate
frequency
signals
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5595278A
Other languages
Japanese (ja)
Inventor
Yasoji Suzuki
Minoru Takada
Yoshihiro Iwamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5595278A priority Critical patent/JPS54147765A/en
Publication of JPS54147765A publication Critical patent/JPS54147765A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses

Landscapes

  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To enable stable high speed operation independently of operation speed of the OR circuit, by selectively supplying the count output of the counter circuit integrated to the OR circuit. CONSTITUTION:The clock pulse CK is inputted, and either one of the count output signals consisting of 10-bit of Q0 to Q9 is parallelly fed to the NOR gate 21 incorporated in the different integrated circuit from the counter circuit 20 integrated, e.g., Q3 and Q8. Accordingly, the output signal of the NOR gate is not set during only the presence of the signals Q3 and Q8, that is, once every five CK's, and no CK is frequency-divided. In this case, the frequency of the signals Q3 and Q8 is sufficiently lower than the frequency of CK. Even if the wiring capacitance between the circuit 20 and the NOR gate 21 is greater, the NOR gate is stably operated. Further, by changing the frequency dividing ratio of CK, the count output signal of the circuit 20 inputted to the NOR gate 21 can arbitrarily be selected.
JP5595278A 1978-05-11 1978-05-11 Frequency division circuit Pending JPS54147765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5595278A JPS54147765A (en) 1978-05-11 1978-05-11 Frequency division circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5595278A JPS54147765A (en) 1978-05-11 1978-05-11 Frequency division circuit

Publications (1)

Publication Number Publication Date
JPS54147765A true JPS54147765A (en) 1979-11-19

Family

ID=13013401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5595278A Pending JPS54147765A (en) 1978-05-11 1978-05-11 Frequency division circuit

Country Status (1)

Country Link
JP (1) JPS54147765A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158325A (en) * 1984-08-29 1986-03-25 Shimadzu Corp D/a converter
FR2587568A1 (en) * 1985-09-19 1987-03-20 France Etat DIGITAL FREQUENCY DIVIDER CIRCUIT

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6158325A (en) * 1984-08-29 1986-03-25 Shimadzu Corp D/a converter
FR2587568A1 (en) * 1985-09-19 1987-03-20 France Etat DIGITAL FREQUENCY DIVIDER CIRCUIT

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