JPH1187702A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device such as IGBT, and its manufacturing method, wherein a gate oxide film in a channel region of which latch-up is easy to oxide is locally made thicker to increase a negative current which is controlled by a gate voltage, with an input capacity reduced. SOLUTION: A p<+> -layer 3 selectively formed on a surface part of an n<-> -layer 2, an n<+> -layer 4 formed in a ladder-form, on a surface part of the p<+> -layer 3, a gate electrode 5 formed, via a gate insulating film 6. on the surface of p<+> -layer 3 which is between the n<-> -layer 2 and the n<+> -layer 4. A source electrode 7 so formed as to contact a rung 8 of a ladder of the n<+> -layer 4, are provided, and an gate insulating film 6A at a ladder rung vicinity A of the n<+> -layer 4 is locally thicker than a gate insulating film 6B at a ladder opening part vicinity B, so that a Hall current value Jh at a channel region 10 at the vicinity A of a ladder rung 8 is low, resulting in a structure which is hard to be distracted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an insulated gate, and more particularly to a gate insulated bipolar transistor suitable as a power switching element.

[0002]

2. Description of the Related Art In recent years, as a power switching element,
Insulated gate bipolar transistor (hereinafter IGBT)
) Is attracting attention. FIG. 4 is a diagram showing a plane and a cross section of a basic configuration of a conventional IGBT,
4A is a plan view, FIG. 4B is a cross-sectional view of a portion I in FIG. 4A, and FIG. 4C is a cross-sectional view of a II portion in FIG. 4A.

4A to 4C, reference numeral 1 denotes a p + layer as a first region of a first conductivity type having a high impurity concentration, and 2 denotes a p + layer 1.
The n− layer 3 as a second region of the second conductivity type with a low impurity concentration formed thereon is formed with a high impurity concentration of the first conductivity type selectively formed in a band on the surface portion of the n− layer 2. Layer 4 as a third region, and n + as a fourth region of the second conductivity type with a high impurity concentration selectively formed in a ladder shape when viewed from the surface. Layer.

Reference numeral 5 denotes a gate electrode, 6 denotes a gate oxide film as a gate insulating film, and the n− layer 2 and the n− layer 2 and the n + layer 4
A band-shaped gate electrode 5 is formed on the surface of the p + layer 3 and the surface of the n − layer 2 with the gate oxide film 6 interposed therebetween. Reference numeral 7 denotes a source electrode. The source electrode 7 comes into contact with and covers both the portion of the ladder bar 8 in the ladder-shaped n + layer 4 and the p + layer 3 exposed in the opening 9 of the ladder. It is formed in a belt shape. Reference numeral 10 denotes a channel region, and the vicinity of the surface of the p + layer 3 sandwiched between the n − layer 2 and the n + layer 4 becomes a channel region 10. 11
Is a collector electrode formed on the other surface of the p + layer 1. The structure of the IGBT is as described above, and the vertical DMOS
N which becomes the drain region of the power MOSFET
It can be said that the layer is replaced with a p-layer.

Hereinafter, the operation of the IGBT shown in FIG. 4 will be described. When a positive voltage is applied to the gate electrode 5 and the collector electrode 11 with the source electrode 7 being grounded, the gate electrode 5
Since the surface portion of the p + layer 3 immediately below is inverted to form an n-type channel, a current flows through the channel region 10 and the IGBT is turned on. At this time, the collector electrode 1
Due to the effect of conductivity modulation caused by the injection of holes from the p + layer 1 on the one side to the n − layer 2, the resistance in the region of the n − layer 2 decreases. This IGBT exhibits such a low on-resistance in the on state, but on the other hand, its structure has a serious drawback of a latching phenomenon based on a parasitic thyristor structure.

When the IGBT is turned on as described above, holes are injected from the p + layer 1 on the collector electrode 11 side to the n − layer 2. Some of the holes recombine with electrons injected from the n + layer 4 through the channel into the n − layer 2 and disappear, but a part passes through the pinch resistance portion of the p + layer 3 and the source electrode 7. Get out. At this time, the holes cannot pass through the n + layer 4 because of the built-in voltage generated between the p + layer 3 and the n + layer 4.

The pinch resistance of the portion of the p + layer 3 through which the hole current passes is Rb, and the value of the passing hole current is J.
h, the voltage expressed by the product of Rb and Jh is equal to p + layer 3 and n
+ Occurs between layers 4. When this voltage becomes higher than the built-in voltage, holes are injected into the n + layer 4, and accordingly, electrons are injected from the n + layer 4. That is, n +
An npn transistor formed by the layer 4, the p + layer 3, and the n− layer 2 is turned on, and a parasitic npnp formed by the n + layer 4, the p + layer 3, the n− layer 2, and the p + layer 1 is turned on. The thyristor latches up, making it impossible to control the current and leading to destruction. In order to prevent breakdown, it is effective to lower the value of the pinch resistance Rb or the hole current Jh.

[0008]

In a conventional IGBT as a semiconductor device, an n @ + layer 4 is formed in a ladder shape, and a source electrode 7 is in contact with a ladder bar 8 but a gate electrode is formed. In the state where a positive voltage is applied to the gate electrode 5 and the collector electrode 11 to form the channel region 10 on the surface of the p + layer 3 immediately below the gate electrode 5, the portion close to the source electrode 7, that is, the ladder rail 8 The closer the portion is, the smaller the source resistance is.
Many electron currents flow through.

That is, in the ON state, the amount of electron current injected from the n + layer 4 to the n − layer 2 through the channel region 10 of the p + layer 3 becomes smaller as the distance from the source electrode 7 becomes shorter. Becomes large because the diffusion resistance is small. Since there are many holes in the region where the number of electrons is large, the value of the hole current Jh in the ladder bar 8 of the n + layer 4 is large, and the ladder of the n + layer 4 in the channel region 10 of the p + layer 3 is large. A near the pier 8
Other parts, for example, near the ladder opening 9 of the n + layer 4 B
There is a problem that latch-up is easier than in the above.

The present invention has been made in order to solve the above-mentioned problems, and makes it difficult to latch up without increasing the number of manufacturing steps as compared with the prior art, that is, it enables a sufficiently large latching current. It is another object of the present invention to provide a high-frequency compatible semiconductor device having a reduced gate input capacitance and a method of manufacturing the same.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device having a low impurity concentration second conductivity type second region provided on a high impurity concentration first conductivity type first region. Second
A third region of the first conductivity type selectively formed on the surface of the region, a fourth region of the second impurity type having a high impurity concentration and having a plurality of openings formed on the surface of the third region, A gate electrode formed on the surface of the third region sandwiched between the second region and the fourth region via a gate insulating film, formed so as to contact a region between the plurality of openings in the fourth region; A gate electrode in a third region between the second region and the fourth region near the region between the plurality of openings in the fourth region. Formed thicker than the gate insulating film.

A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the fourth region has a plurality of ladder-shaped openings, and the source electrode has a ladder in the fourth region. The gate insulating film of the third region sandwiched between the second region and the fourth region in the vicinity of the ladder of the fourth region is formed so as to be in contact with the portion of the ladder of the fourth region. It is formed thicker than the gate insulating film in the third region.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first or second aspect.
Forming a gate insulating film in a third region sandwiched between the second region and the fourth region near the region between the openings of the fourth region and a gate insulating film in the second region continuous with the gate insulating film in the same step; It is formed by.

According to a fourth aspect of the present invention, there is provided a semiconductor device having a second region of a low impurity concentration and a second conductivity type provided on a first region of a high impurity concentration and a first conductivity type. A third region of the first conductivity type selectively formed, a second conductivity type with a high impurity concentration, having an opening formed in the surface of the third region, and having a protrusion on the inner periphery of the opening; A fourth region, a gate electrode formed in a third region sandwiched between the second region and the fourth region via a gate insulating film, formed so as to be in contact with a protrusion on the inner periphery of the opening of the fourth region; A gate electrode in a third region between the second region and the fourth region in the vicinity of the protrusion of the fourth region, and a gate insulation film in the third region excluding the vicinity of the protrusion. It is formed thicker than the film.

A method of manufacturing a semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the fourth aspect, wherein the opening of the fourth region on the surface of the third region sandwiched between the second and fourth regions. Forming a gate insulating film in the vicinity of the protruding portion on the inner periphery and a gate insulating film on the surface of the second region continuous with the gate insulating film in the vicinity of the protruding portion in the same step;

According to a sixth aspect of the present invention, there is provided a semiconductor device having a second region of a low impurity concentration and a second conductivity type provided on a first region of a first conductivity type with a high impurity concentration and a second region of the second region having a low impurity concentration. A third region of the first conductivity type having a polygonal shape formed selectively;
On the surface of the fourth region of the second conductivity type having a high impurity concentration and having a polygonal opening formed on the surface of the third region, and on the surface of the third region sandwiched between the second region and the fourth region. A gate electrode formed via a gate insulating film, a source electrode formed to be in contact with the inner periphery of the fourth region, and the second region and the fourth region in the vicinity of a corner of the fourth region; The gate insulating film in the third region sandwiched therebetween is formed to be thicker than the gate insulating film in the third region near the side excluding the corner.

The method of manufacturing a semiconductor device according to a seventh aspect of the present invention is directed to the semiconductor device according to the fifth aspect, wherein the third device sandwiched between the second region and the fourth region near the corner of the fourth region is provided.
The gate insulating film in the region and the gate insulating film in the second region continuous with the gate insulating film are formed in the same step.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. FIG. 1 shows an embodiment of the first to third inventions.
This will be described below. 1A and 1B are a plan view and a cross-sectional view, respectively, of a basic configuration of an IGBT as a semiconductor device. FIG. 1A is a plan view, FIG. 1B is a cross-sectional view of a portion I in FIG.
c shows a sectional view of II part in FIG. 1a. In the figure, those denoted by the same reference numerals as those of the conventional example indicate the same or equivalent parts as those of the conventional example.

Hereinafter, the operation of the IGBT shown in FIG. 1 will be described. As in the case of the IGBT described in the conventional example, when a positive current is applied to the gate electrode 5 and the collector electrode 11 with the source electrode 7 being grounded, p
Since the surface portion of + layer 3 is inverted to form an n-type channel, current flows through channel region 10, but p + layer 3
Is larger than the built-in voltage generated between the p + layer 3 and the n + layer 4 by the product of the pinch resistance Rb of the portion through which the hole current passes and the value Jh of the passing hole current. Then, the parasitic npnp thyristor formed by the n + layer 4, the p + layer 3, the n− layer 2, and the p + layer 1 latches up.

When the voltage applied to the collector electrode 11 and the gate electrode 5 is constant, the value of the current flowing through the IGBT is n
Gate voltage required to form a channel of
Vth), the current hardly flows when Vth is high, but the factors that determine Vth are the channel length in the channel region 10, the impurity concentration of the p + layer 3 where the channel is formed, and the gate insulating film. Thickness and the like.

The IGBT according to the first and second inventions is
As shown in FIGS. 1B and 1C, in the n + layer 4 having a plurality of openings 9 formed in a ladder shape, the gate oxide film 6A in the vicinity of the ladder bar 8 which is a region between the openings 9 is separated from the other. By forming a portion thicker than the gate oxide film 6B in the vicinity of the opening 9 of the ladder of the n + layer 4, the V +
The th is higher. As a result, the value Jh of the hole current in the channel region 10 in the vicinity A of the ladder bar 8 of the n + layer 4 where the latch-up is apt to occur conventionally becomes low, and the structure is hardly broken.

As described above, by forming at least a portion of the gate oxide film on the surface of the channel region near the n + layer 4 in contact with the source electrode 7 to be thicker than the other portions, Vth is locally increased. As a result, it is difficult to cause a current to flow, a latching phenomenon is less likely to occur and a high breakdown strength is obtained, and the input capacitance Cies of the gate electrode 5 is reduced, thereby enabling operation at a high frequency.

In the embodiment shown in FIG. 1, the n + layer 4 has a ladder shape, but the n + layer 4 as the fourth region is not limited to the ladder shape. 4 has a plurality of openings of any shape, and the source electrode 7 has n +
P is formed so as to be in contact with a region between openings in layer 4 and is sandwiched between n + layers 2 and 4 in the vicinity of a region between openings in n + layer 4 that is in contact with source electrode 7.
The gate insulating film on the surface of the + layer 3 (channel region) is the n + layer 4
A similar effect can be obtained even if the gate insulating film is formed thicker than the gate insulating film on the surface of the p + layer 3 (channel region) near the opening.

Next, a method of manufacturing a semiconductor device according to the third invention will be described. In the manufacturing process of the IGBT shown in FIG. 1, the gate oxide film 6A on the surface of the p + layer 3 in the vicinity A of the ladder bar 8 as a region between the plurality of openings 9 in the n + layer 4 P + layer 3 in
When locally and selectively forming a gate oxide film 6A thicker than the gate oxide film 6B on the surface, the gate oxide film 6A in the vicinity A of the ladder bar 8 is formed on the surface of the n− layer 2 in contact with the p + layer 3. It is formed in the same step as the oxide film 6C. Since the gate oxide film 6A and the gate oxide film 6C are formed with substantially the same insulating thickness, according to this manufacturing method, the channel of the p + layer 3 can be formed without increasing the number of manufacturing steps as compared with the conventional manufacturing method. The gate oxide film on the surface of the region 10 can be locally and selectively formed thick.

Embodiment 2 Next, one embodiment of the fourth and fifth inventions will be described with reference to FIG. 2A and 2B are a plan view and a sectional view, respectively, showing the basic structure of an IGBT as a semiconductor device. FIG. 2A is a plan view, and FIG.
FIG. 2c is a cross-sectional view of the portion II in FIG. 2a.

In FIGS. 2A to 2C, reference numeral 3 denotes a p + layer 3 as a third region of the first conductivity type having a high impurity concentration and selectively formed on the surface portion of the n − layer 2, and has a hexagonal shape. Is formed.

Reference numeral 4 denotes a high impurity concentration selectively formed on the surface of the p + layer 3 and an n + as a fourth region of the second conductivity type.
A layer 7 is a source electrode, and a hexagonal opening 9 having a pair of projecting portions 12 is formed in the n + layer 4 at a position facing each other when viewed from the surface. The source electrode 7 is located at the center of the opening 9 of the n + layer 4 and is formed so as to be in contact with both the protrusion 12 and the p + layer 3 exposed at the opening 9. Reference numeral 5 denotes a gate electrode, and reference numeral 6 denotes a gate oxide film as a gate insulating film. The vicinity of the surface of the p + layer 3 sandwiched between the n − layer 2 and the n + layer 4 becomes a channel region 10.

The IGBT according to the fourth invention is shown in FIG.
As shown in FIG. 2c, n + in contact with the source electrode 7
The gate oxide film 6A on the surface of the p + layer 3 (channel region 10) in the vicinity A of the protruding portion 12 of the layer 4 is
That is, the p + layer 3 remote from the vicinity A of the protruding portion 12 of the n + layer 4
It is formed thicker than the gate oxide film 6B on the surface of the (channel region 10). As a result, similarly to the first and second embodiments of the invention shown in FIG. 1, Vth can be locally increased, and the channel in the vicinity of the protruding portion 12 of the n + layer 4 which is liable to cause latch-up. The hole current value Jh in the region 10 can be reduced, and a structure that is not easily broken can be obtained.

As described above, even when the n + layer 4 is not formed in a ladder shape, at least a portion of the gate oxide film on the surface of the channel region near the contact between the n + layer 4 and the source electrode 7 is removed. By increasing the thickness locally, the Vth is locally increased to make it difficult for current to flow, the latching phenomenon is less likely to occur and a high breakdown strength is obtained, and the input capacitance of the gate electrode 5 is reduced, and Operation enabled.

In the above embodiment, the n + as the fourth region
The layer 4 has a hexagonal shape, and the paired protrusions 12 are located inside the corners. However, the present invention is not limited to the hexagonal shape, and any other polygons, rounds, elongated shapes, etc. Applicable to shaped cells. For example, in the embodiment shown in FIG. 1, the ladder bar 8 in the ladder-shaped n + layer 4 is formed.
Instead of the embodiment, a plurality of pairs of protrusions 12 are formed, and the plurality of pairs of protrusions 12 are in contact with the source electrode 7 in the same manner as in the embodiment shown in FIG. Effects can be obtained.

In the above example, the plurality of protruding portions 12 do not necessarily have to form a pair, and even if they protrude arbitrarily, the plurality of protruding portions 12 are formed, for example, in a staggered manner on the inner peripheral portion of the elongated opening. Thus, even if the plurality of protrusions 12 are in contact with the source electrode 7, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

The embodiment shown in FIG. 2 in which the pair of projecting portions 12 are integrally joined at the center corresponds to the first invention, and naturally, the embodiment shown in FIG. The same effect can be obtained.

Next, a method of manufacturing a semiconductor device according to the fifth invention will be described. In the step of forming the gate oxide film 6 of the IGBT shown in FIG.
Except for the surface B of the p + layer 3 (channel region 10) remote from the vicinity A, the gate oxide film 6A of the channel region 10 and the gate oxide film 6A in the vicinity A of the protrusion 12 of the n + layer 4 in contact with the source electrode 7 N− in contact with + layer 3 (channel region 10)
A gate oxide film 6C on the surface of layer 2 is formed simultaneously and in the same step.

According to the above-described manufacturing method, as in the method of manufacturing a semiconductor device according to the third aspect, the manufacturing method is different from the conventional manufacturing method.
Channel region 1 of p + layer 3 without increasing the number of manufacturing steps
The thickness of the gate oxide film on the surface 0 can be locally and selectively increased.

Embodiment 3 FIG. One embodiment of the sixth and seventh inventions will be described with reference to FIG. FIG. 3 is a plan view of the basic configuration of the IGBT. In the figure, reference numeral 3 denotes a p + layer as a third region of the first conductivity type having a high impurity concentration selectively formed on the surface portion of the n − layer 2 and is formed in a square shape. Reference numeral 4 denotes an n-layer having a high impurity concentration selectively formed on the surface of the p + layer 3 and having a high impurity concentration as a second region of the second conductivity type, and has a quadrangular shape as viewed from the surface. And the p + layer 3 is exposed from the opening 9.

Reference numeral 7 denotes a source electrode, which has a square shape,
The outer periphery thereof is formed so as to be in contact with the entire periphery of the inner periphery of the opening 9 of the n + layer 4 and also to contact the p + layer 3 exposed from the opening 9. 5 is a gate electrode, 6
Denotes a gate oxide film as a gate insulating film, and the n-
The vicinity of the surface of the p + layer 3 sandwiched between the layer 2 and the n + layer 4 is a channel region 10.

In the IGBT according to the sixth invention,
As is clear from FIG. 3, the source electrode 7 is in contact with the entire periphery of the n + layer 4, but the gate oxide film 6 A on the surface of the channel region 10 near the corner 13 of the n + layer 4 is That is, near the side B away from the corner of the n + layer 4
Is formed thicker than the gate oxide film 6B on the surface of the channel region 10 in FIG.

That is, even if the entire periphery of the n + layer 4 and the source electrode 7 are in uniform contact with each other, the diffusion concentration of the third region becomes non-uniform if the cell structure is square. That is, the diffusion density in the vicinity of the corner 13 decreases. For this reason, Vth of the angular portion becomes lower than that of the other regions, and Jh increases due to the concentration of current, which makes the cell more likely to be broken. However, in the present invention, the angular portion of the cell (the region surrounded by the dotted line in FIG. 3) 4) The gate oxide film 6A is thicker than the gate oxide film 6B in the other region, and the Vth is locally increased to prevent current concentration and increase the breakdown strength.

FIG. 3 shows a square cell.
A similar effect can be obtained for polygonal cells having more than a square. Also, even if the corners of the cell are slightly rounded, substantially the same effect can be obtained.

Next, a method of manufacturing a semiconductor device according to the seventh invention will be described. In the step of forming the gate oxide film 6 of the IGBT shown in FIG. 3, the gate oxide film 6A on the channel region 10 near the corner A of the n + layer 4 and the gate oxide film on the surface of the n − layer 2 in contact with the channel region 10 6B are simultaneously formed. According to this manufacturing method, the gate oxide film on the surface of the channel region 10 of the p + layer 3 can be locally and selectively thickened without increasing the number of manufacturing steps as compared with the conventional manufacturing method.

Although the embodiment shown in FIGS. 1 to 3 relates to an n-channel IGBT, the same effect can be obtained when applied to a p-channel IGBT in which n and p are inverted. can get. Similar effects can be obtained when the invention is applied to all devices having a parasitic thyristor structure other than the IGBT.

In a normal IGBT, a plurality of p + layers 3 as third regions are selectively formed on the surface of the n − layer 2 as second regions, and an IGBT cell is formed on each p + layer 3. Is formed, but also in this case, the above embodiment can be applied. Further, in the step of forming the gate oxide film in this case, the gate oxide film in the channel region portion of the p + layer 3 and the gate oxide film on the surface of the n − layer 2 in contact with the channel region, that is, the latching phenomenon is likely to occur. By simultaneously forming the gate oxide film on the surface of the n − layer 2 as the second region between the third region and the third region in the same step, the number of manufacturing steps can be increased as compared with the conventional manufacturing method. In addition, the gate oxide film on the surface of the channel region 10 of the p + layer 3 can be locally and selectively formed thick.

[0043]

According to the first, second, fourth and sixth aspects of the present invention, the gate oxide film in the portion where the latching phenomenon is likely to occur in the semiconductor device is locally thickened so that the current does not easily flow. An element having a sufficiently large latching current can be produced, an element having a large load current controlled by the gate voltage can be obtained, and the input capacitance Cies can be reduced by increasing the thick portion of the gate oxide film. The element can be a high-frequency element.

According to the third, fifth and seventh aspects of the present invention,
In a step of forming a gate oxide film of a semiconductor device, a gate oxide film in a channel region portion of a p + layer which is liable to cause a latching phenomenon and a gate oxide film on the surface of an n− layer in contact with the channel region are formed simultaneously. Therefore, as compared with the conventional manufacturing method, there is an effect that the gate oxide film on the surface of the channel region of the p + layer can be locally and selectively formed thick without increasing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a plan view and a sectional view of a semiconductor device according to an embodiment of the first and third inventions.

FIG. 2 is a diagram showing a plane and a cross section of a semiconductor device according to an embodiment of the fourth and fifth inventions.

FIG. 3 is a diagram showing a plane and a cross section of a semiconductor device according to an embodiment of the sixth and seventh inventions.

FIG. 4 is a diagram showing a plane and a cross section of a conventional semiconductor device.

[Explanation of symbols]

1 p layer (first region), 2 n layer (second region), 3 p layer
Diffusion layer (third region), 4n diffusion layer (fourth region), 5
Gate electrode, 6 Gate oxide film, 7 Source electrode, 8
Ladder beam, 9 opening, 10 channel area, 1
1 collector electrode, 12 protrusion, 13 corner

Claims (7)

[Claims] 1. A low impurity concentration second conductivity type second region provided on a high impurity concentration first conductivity type first region, and a first region selectively formed on a surface of the second region. Third of conductivity type
A region, a fourth region of a second conductivity type having a high impurity concentration and having a plurality of openings formed in a surface portion of the third region, and a surface of the third region sandwiched between the second region and the fourth region A gate electrode formed thereon with a gate insulating film interposed therebetween, a source electrode formed so as to contact a region between the plurality of openings in the fourth region, and a source electrode formed between the plurality of openings in the fourth region. A semiconductor device, wherein a gate insulating film in a third region near the region between the second region and the fourth region is formed thicker than a gate insulating film in the third region near the opening. 2. The semiconductor device according to claim 1, wherein
The fourth region has a plurality of openings formed in a ladder shape, and the source electrode is formed so as to be in contact with the ladder bar in the fourth region, and the fourth region has a ladder bar near the ladder bar in the fourth region. A semiconductor device in which a gate insulating film in a third region sandwiched between two regions and the fourth region is formed to be thicker than the gate insulating film in the third region near an opening of a ladder. 3. The semiconductor device according to claim 1, wherein a gate insulating film in a third region sandwiched between the second region and the fourth region in the vicinity of the region between the openings in the fourth region, and A method for manufacturing a semiconductor device, comprising: forming a gate insulating film in the second region that is continuous with a gate insulating film in the same step. 4. A second region of a second conductivity type having a low impurity concentration provided on a first region of a first conductivity type having a high impurity concentration, and a first region selectively formed on a surface portion of the second region. Third of conductivity type
A fourth region of high impurity concentration and a second conductivity type having a region, an opening formed in the surface of the third region and a protrusion on the inner periphery of the opening, and the second region and the fourth region; A gate electrode formed via a gate insulating film in a third region sandwiched by
A source electrode formed so as to be in contact with a protrusion on the inner periphery of the opening of the fourth region; and a third region sandwiched between the second region and the fourth region in the vicinity of the protrusion of the fourth region. A semiconductor device in which a gate insulating film is formed thicker than a gate insulating film in the third region excluding the vicinity of the protrusion. 5. The semiconductor device according to claim 4, wherein the gate insulating film is formed on the surface of the third region sandwiched between the second region and the fourth region, near the protruding portion on the inner periphery of the opening of the fourth region. A method for manufacturing a semiconductor device, comprising: forming a gate insulating film on a surface of the second region which is continuous with a gate insulating film in the vicinity of a protrusion in the same step. 6. A low impurity concentration second region of a second conductivity type provided on the first region of the first conductivity type with a high impurity concentration, and a polygonal shape selectively formed on the surface of the second region. A third region of the first conductivity type, a fourth region of the second conductivity type with a high impurity concentration and a polygonal opening formed in the surface of the third region, and the second and fourth regions. A gate electrode formed on the surface of the third region sandwiched by the gate insulating film via a gate insulating film, and a source electrode formed so as to be in contact with the inner periphery of the fourth region, and near a corner of the fourth region. In the semiconductor device, the gate insulating film in the third region sandwiched between the second region and the fourth region is formed thicker than the gate insulating film in the third region near the side excluding the corner. 7. The semiconductor device according to claim 5, wherein a gate insulating film in a third region between the second region and the fourth region in the vicinity of a corner of the fourth region and the first region continuous with the gate insulating film. A method for manufacturing a semiconductor device, comprising forming two regions of a gate insulating film in the same step.