JPH1187530A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of a built-in MOS-type capacitor of a semiconductor device, whose epitaxial layer is formed in the upper layer part of a semiconductor substrate, and whose substrate resistance is low, and whose latch-up strength is satisfactory. SOLUTION: A P-type epitaxial layer 12 whose conductivity type is the same as the conductivity type of a semiconductor layer 11 is formed in the upper layer part of the semiconductor substrate 11. The thickness of the part of the epitaxial layer 12 in a MOS-type capacitor 19 forming a region is thicker than the thicknesses of the parts of the epitaxial layer 12 in the forming regions of MOS transistors 15a and 15b. With this arrangement, the junction capacitance between the N<+> -type diffused layer 22 and the semiconductor substrate 11 (epitaxial layer 12) can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor integrated circuit device having a MOS capacitor and a MOS transistor.

[0002]

2. Description of the Related Art In recent years, with the remarkable miniaturization of semiconductor devices, the latch-up resistance has been reduced. To prevent this, a semiconductor substrate having an epitaxial layer formed in an upper layer and having a low substrate resistance has been used. ing.

FIG. 8 is a sectional view showing a structure of a conventional semiconductor device having a MOS capacitor. In the figure,
Reference numeral 1 denotes a semiconductor substrate (hereinafter, referred to as a substrate 1) made of a P ⁺ type silicon single crystal or the like, 2 denotes a P-type epitaxial layer formed in an upper layer portion of the substrate 1, 3 denotes a field insulating film for separating elements, 4 denotes N ⁺ formed on the epitaxial layer 2
Diffusion layer 5 is formed in the diffusion layer 4, an N ⁺⁺ type diffusion layer serving as an electrode extraction layer of the diffusion layer 4, 6 is an insulating film formed on the surface of the diffusion layer 4, and 7 is on the insulating film 6. Is a MOS type capacitor constituting a lower electrode, a dielectric film and an upper electrode by the diffusion layer 4, the insulating film 6 and the conductive film 7, and 9 is an insulating film formed on the side wall of the conductive film 7. It is a side wall.

[0004] The MOS type capacitor as described above usually has M
A semiconductor device is constituted by being arranged on the same substrate 1 together with other elements such as an OS type transistor. In general, the conductive film 7 is formed simultaneously with the gate electrode (not shown) of the MOS transistor, the insulating film 6 is formed simultaneously with the gate insulating film (not shown), and the N ⁺⁺ type diffusion layer 5 is formed simultaneously. It is formed simultaneously with the source / drain region (not shown).

[0005]

Since the conventional semiconductor device is constructed as described above, boron as an impurity in the substrate 1 is diffused toward the surface of the substrate 1 by the heat treatment in the manufacturing process, and a diffusion layer is formed. 4 and the substrate 1 (epitaxial layer 2) have a higher boron concentration near the junction. For this reason, the junction capacitance increases, and as shown in the equivalent circuit diagram of FIG. 9, a junction capacitance 10 which becomes a large parasitic capacitance other than the MOS capacitor 8 is inserted in parallel with the MOS capacitor 8. Due to such an increase in the parasitic capacitance, there is a problem that the reliability is deteriorated due to an increase in power consumption and a change in characteristics.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a structure of a semiconductor device having a MOS type capacitor having good latch-up resistance and a reduced parasitic capacitance, and manufacturing suitable for the structure. The aim is to provide a method.

[0007]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a diffusion layer on a semiconductor substrate; an insulating film formed on the surface of the diffusion layer; and a conductive layer formed on the insulating film. A device configuration having a MOS capacitor formed of a film and a MOS transistor, wherein the semiconductor substrate has an epitaxial layer of the same conductivity type as the semiconductor substrate in an upper layer portion, and the MOS capacitor formation region Wherein the epitaxial layer is formed thicker than that in the MOS transistor formation region.

According to a second aspect of the present invention, there is provided a semiconductor device comprising: a MOS transistor comprising a diffusion layer, an insulating film formed on a surface of the diffusion layer, and a conductive film formed on the insulating film. Wherein the semiconductor substrate has an epitaxial layer of the same conductivity type as the semiconductor substrate in an upper layer portion, and the epitaxial layer below a diffusion layer of the MOS capacitor. A buried oxide film is formed therein.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, a buried oxide film is formed below the diffusion layer and in contact with the diffusion layer.

According to a fourth aspect of the present invention, there is provided the semiconductor device according to the second or third aspect, wherein the buried oxide film is formed when a reverse bias is applied at a junction between the diffusion layer forming the MOS capacitor and the semiconductor substrate. Is formed thicker than the width of the depletion layer.

According to a fifth aspect of the present invention, there is provided a semiconductor device comprising: a MOS transistor comprising a diffusion layer on a semiconductor substrate, an insulating film formed on the surface of the diffusion layer, and a conductive film formed on the insulating film. A semiconductor device having a type capacitor and a MOS transistor, wherein the semiconductor substrate has an epitaxial layer of an opposite conductivity type to the semiconductor substrate in an upper layer portion.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device, the epitaxial layer is selectively further grown in a predetermined region on a semiconductor substrate having an upper layer composed of an epitaxial layer of the same conductivity type. Form, then
A MOS capacitor is formed in the predetermined region where the epitaxial layer is grown thick, and a MOS transistor is formed in a thin region of the epitaxial layer.

According to a seventh aspect of the present invention, in a method of manufacturing a semiconductor device, a semiconductor substrate having an upper layer portion formed of an epitaxial layer of the same conductivity type is selectively etched to define a predetermined region of the epitaxial layer. After removing by a predetermined thickness to reduce the thickness, a MOS transistor is formed in the predetermined region where the epitaxial layer is thin, and a MOS capacitor is formed in a region where the epitaxial layer is thick.

According to a eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a buried oxide film is formed by heat treatment after injecting oxygen ions into a semiconductor substrate whose upper layer is formed of an epitaxial layer of the same conductivity type. It is.

According to a ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eighth aspect, oxygen ions are implanted by ion implantation for forming a diffusion layer forming a MOS capacitor. And using the same mask.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention. In the figure, 11
Denotes a semiconductor substrate (hereinafter, referred to as a substrate 11) made of P ⁺ -type silicon single crystal or the like, 12 denotes a P-type epitaxial layer of the same conductivity type as the substrate 11 formed in an upper layer portion of the substrate 11,
13 is a field insulating film for separating the elements, 14a, 1
4b is an N-type well region and a P-type well region formed in the epitaxial layer 2, and 15a and 15b are P-type MOS transistors and N-type MOS transistors formed in the N-type well region 14a and the P-type well region 14b, respectively. The gate insulating films 16a, 16b, the gate electrodes 17a, 17b, and the source / drain regions 18a,
8b. Reference numeral 19 denotes a MOS-type capacitor, which includes a dielectric film 20 as an insulating film, an upper electrode 21 as a conductive film, and an N ⁺ -type diffusion layer 22, and 22 a is formed in the N ⁺ -type diffusion layer 22. An N ⁺⁺ type diffusion layer 23a serving as an electrode take-out layer of the N ⁺ type diffusion layer 22;
23b and 23c are MOS transistors 15a and 15b
Are formed on the side walls of the gate electrodes 17a, 17b and the upper electrode 21 of the MOS capacitor 19, respectively.

As shown in the figure, a substrate 11 has a P-type epitaxial layer 12 whose upper layer has the same conductivity type as the substrate 11.
It consists of. The epitaxial layer 12 has a relatively thick region and a thin region, and the MOS capacitor 19 is formed in the thick region, and the MOS transistors 15a and 15b are formed in the thin region. .

A method of manufacturing the semiconductor device having the above structure will be described below with reference to FIG. First, as shown in FIG. 2A, an upper P-type epitaxial layer
As shown in FIG. 2B, an oxide film 24 is formed on the P ⁺ type substrate 11 having a thickness of μm and then patterned, and the epitaxial film 12 in a predetermined region is selectively formed using the oxide film 24 as a mask. Further growth is performed, and the epitaxial layer 12 in that region is grown to a thickness of about 5.0 μm. Next, as shown in FIG. 2C, the oxide film 24 is removed.
Thereafter, a field insulating film 13 is formed, and a MOS capacitor 19 is formed in a thick region of the epitaxial layer 12.
MOS transistors 15a and 15b are formed in a thin region of the epitaxial layer 12. The formation of the MOS capacitor 19 and the MOS transistors 15a and 15b
First, well regions 14a and 14b are formed in regions where MOS transistors 15a and 15b are to be formed, respectively, and gate insulating films 16a and 16b made of an oxide film and a dielectric film 20 are simultaneously formed. Next, after the N ⁺ type diffusion layer 22 is formed by ion implantation using a resist mask, the gate electrodes 17 a and 17 b made of, for example, a polysilicon film are formed.
And the upper electrode 21 are simultaneously formed. Thereafter, insulating film side walls 23a, 23b and 23c are formed on the side walls of the gate electrodes 17a and 17b and the upper electrode 21, and the source / drain regions 18a and 18b and the N ⁺⁺ type diffusion layer 22a are simultaneously formed by ion implantation. (See FIG. 1), a predetermined process is performed to complete the semiconductor device.

In this embodiment, the N ⁺ -type diffusion layer 22 and the substrate 11 (epitaxial layer 1)
The distance at which the junction with 2) separates from the P ⁺ type substrate 11 increases. For this reason, impurities such as boron diffused from the substrate 11 by the heat treatment in the manufacturing process can be prevented from reaching the vicinity of the junction. For this reason, the impurity concentration near the junction between the N ⁺ type diffusion layer 22 and the substrate 11 (epitaxial layer 12) can be reduced, and the junction capacitance can be reduced. As a result, the parasitic capacitance can be reduced and a highly reliable M
An OS-type capacitor 19 is obtained. Further, since the epitaxial layer 12 in the formation region of the MOS transistors 15a and 15b is formed thin, good latch-up resistance can be maintained without increasing the resistance of the substrate 11. As described above, a parasitic capacitance of the MOS capacitor 19 can be reduced, and a semiconductor device having good latch-up resistance can be obtained.

Embodiment 2 In the first embodiment, the epitaxial layer 12 formed on the substrate 11 is further selectively grown only in a predetermined region.
A thick epitaxial layer 12 may be formed on the substrate 1 and then selectively etched to reduce the thickness. FIG. 3 shows a manufacturing method thereof. First, as shown in FIG.
P having a thickness of about 5.0 μm
^As shown in FIG. 3B, a photoresist film 25 is formed on the ⁺ -type substrate 11 and then patterned, and the epitaxial layer 12 in a predetermined region is selectively removed by etching using the photoresist film 25 as a mask. The thickness of the epitaxial layer 12 in that region is about 2.5 μm. next,
As shown in FIG. 3C, the photoresist film 25 is removed. Thereafter, similarly to the first embodiment, a MOS capacitor 19 is placed in a thick region of the epitaxial layer 12.
MOS transistors 15a and 15b are formed in a thin region of the epitaxial layer 12. Also in this embodiment, a semiconductor device which can reduce the parasitic capacitance of MOS type capacitor 19 and has good latch-up resistance can be obtained.

Embodiment 3 Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention. As shown in the figure, a P-type epitaxial layer 12 of the same conductivity type as the substrate 11 is formed with a uniform thickness, and in the region where the MOS-type capacitor 19 is formed, the P-type epitaxial layer 12 is formed in the epitaxial layer 12 below the N ⁺ -type diffusion layer 22. A buried oxide film 26 is formed. In this case, the MOS transistors 15a, 1
Since the thickness of the epitaxial layer 12 is the same as that of the MOS capacitor 19, the illustration of the 5b formation region is omitted.

A method of manufacturing a semiconductor device having such a configuration will be described below with reference to FIG. First, as in the first embodiment, a P-type epitaxial layer 12 is
The field insulating film 13 is formed using the P ⁺ -type substrate 11 formed with the MOS transistors 15a and 15b.
Well regions 14a and 14b are formed in the formation region. Next, the gate insulating films 16a and 16b made of an oxide film and the dielectric film 20 are simultaneously formed. Next, as shown in FIG. 5, oxygen ions 26a for forming the buried oxide film 26 are implanted by ion implantation using a resist mask 27, and subsequently, an N ⁺ -type diffusion layer is formed using the same resist mask 27. An impurity implantation region 22b is formed by performing ion implantation for forming 22. The implanted oxygen ions 26a are combined with silicon in the substrate 11 by a heat treatment in a later step,
The buried oxide film 26 is transformed. Further, the impurity implantation region 22b is transformed into the N ⁺ type diffusion layer 22 by diffusion. At this time, the buried oxide film 26 becomes the N ⁺ type diffusion layer 2.
The energy at the time of implantation is set so as to be located in the two lower epitaxial layers 12. Thereafter, as in the first embodiment, after the gate electrodes 17a and 17b and the upper electrode 21 are simultaneously formed, the insulating film side walls 23a and
23b and 23c are formed, and then the source / drain regions 18a and 18b and the N ⁺⁺ type diffusion layer 2 are formed by ion implantation.
2a is simultaneously formed (see FIG. 4).

In this embodiment, since the buried oxide film 26 is formed in the epitaxial layer 12 below the N ⁺ type diffusion layer 22, impurities such as boron diffused from the substrate 11 by the heat treatment in the manufacturing process are reduced. The N ⁺ type diffusion layer 22 is segregated and absorbed by the buried oxide film 26.
Does not reach the vicinity of the junction between the substrate and the substrate 11 (epitaxial layer 12). Therefore, the impurity concentration near the junction can be reduced, and the junction capacitance can be reduced. Thereby, the parasitic capacitance can be reduced and the highly reliable MOS capacitor 19
Is obtained. Also, in order not to increase the resistance of the substrate 11,
Good latch-up resistance can be maintained. Further, since the implantation of oxygen ions 26a for forming the buried oxide film 26 uses the same resist mask 27 as the ion implantation for forming the N ⁺ -type diffusion layer 22, The parasitic capacitance of the MOS capacitor 19 can be reduced, and a semiconductor device having good latch-up resistance can be easily manufactured.

Embodiment 4 The buried oxide film 26 formed in the third embodiment may be formed below and in contact with the N ⁺ type diffusion layer 22. Figure 6 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the invention, as shown in FIG., The buried oxide film 26b is, N ⁺ -type diffusion layer 22
And is formed in the epitaxial layer 12 thereunder. In the case of a device having a design rule of 0.5 μm, the depth of the junction between the N ⁺ type diffusion layer 22 and the substrate 11 (epitaxial layer 12) is formed to about 0.9 μm. Therefore, oxygen ion 2
6a is implanted at an implantation energy of about 330 to 350 KeV.

In this embodiment, the buried oxide film 26
b is to be formed on the lower layer in contact with the N ⁺ -type diffusion layer 22, without contacting the N ⁺ -type diffusion layer 22 lower surface and the substrate 11 (epitaxial layer 12), junction capacitance, N ⁺ -type diffusion layer Since only the junction capacitance between the side surface 22 and the substrate 11 (epitaxial layer 12) is used, the junction capacitance can be greatly reduced. Thereby, the parasitic capacitance of the MOS capacitor 19 can be further reduced, and a semiconductor device having good latch-up resistance can be easily manufactured.

In the fourth and fifth embodiments, the buried oxide films 26 and 26b are formed on the N ⁺ type diffusion layer 2 in order to reduce the influence of the parasitic capacitance due to the formation of the buried oxide films 26 and 26b.
It is desirable to form the depletion layer at a junction between the substrate 2 and the substrate 11 (epitaxial layer 12) thicker than the depletion layer width at the time of reverse bias.

Embodiment 5 FIG. In the first to fourth embodiments,
Substrate 11, although the upper part used those composed of the epitaxial layer 12 P-type as the substrate 11 and the same conductivity type, not limited to this, as shown in FIG. 7, N ⁺ -type substrate 11a May be used in which a P-type epitaxial layer 12a of the opposite conductivity type to the substrate 11a is formed in the upper layer portion. In this embodiment, since there is no adverse effect due to diffusion of impurities from the substrate 11a, the N ⁺ type diffusion layer 22 and the substrate 11a
The junction capacitance with the (epitaxial layer 12a) does not increase. Therefore, the parasitic capacitance of the MOS capacitor 19 can be reduced, and a highly reliable semiconductor device can be obtained.

[0028]

As described above, according to the present invention, a semiconductor substrate has an epitaxial layer of the same conductivity type as that of the semiconductor substrate in an upper layer portion, and the epitaxial layer in a MOS capacitor forming region is formed by forming a MOS transistor. Since it is formed thicker than that in the region, the parasitic capacitance of the MOS capacitor can be reduced, and a highly reliable semiconductor device having good latch-up resistance can be provided.

According to the invention, the semiconductor substrate has an epitaxial layer of the same conductivity type as that of the semiconductor substrate in an upper layer portion, and a buried oxide film is formed in the epitaxial layer below the diffusion layer of the MOS capacitor. It is possible to provide a highly reliable semiconductor device that can reduce the parasitic capacitance of the MOS capacitor and has good latch-up resistance.

According to the present invention, since the buried oxide film is formed below the diffusion layer and in contact with the diffusion layer, the parasitic capacitance of the MOS capacitor can be further reduced, and the highly reliable semiconductor device having good latch-up resistance is provided. Can be provided.

Further, according to the present invention, the buried oxide film is formed to be thicker than the depletion layer width at the time of reverse bias at the junction between the diffusion layer constituting the MOS type capacitor and the semiconductor substrate. The influence can be reduced, the parasitic capacitance of the MOS capacitor as described above can be reduced, and a highly reliable semiconductor device with good latch-up resistance can be reliably provided.

According to the present invention, since the semiconductor substrate has an epitaxial layer of a conductivity type opposite to that of the semiconductor substrate in an upper layer portion, there is no adverse effect due to diffusion of impurities from the semiconductor substrate, and the parasitic capacitance of the MOS capacitor is reduced. A highly reliable semiconductor device can be provided.

Further, according to the present invention, the epitaxial layer is selectively grown further in a predetermined region on a semiconductor substrate having an upper layer composed of an epitaxial layer of the same conductivity type to form a thicker layer. The epitaxial layer is formed in the predetermined region where it has grown thick, and M
Since the OS-type transistor is formed in a thin region of the epitaxial layer, a method for manufacturing a highly reliable semiconductor device with reduced parasitic capacitance of a MOS-type capacitor and good latch-up resistance can be provided.

Further, according to the present invention, a semiconductor substrate whose upper layer portion is formed of an epitaxial layer of the same conductivity type is selectively etched to remove a predetermined region of the epitaxial layer by a predetermined thickness to reduce the thickness. After that, since the MOS transistor is formed in the predetermined region where the epitaxial layer is thin and the MOS capacitor is formed in the region where the epitaxial layer is thick, the parasitic capacitance of the MOS capacitor can be reduced and the latch-up resistance is good. A highly reliable semiconductor device manufacturing method can be provided.

According to the present invention, the buried oxide film is formed by heat treatment after oxygen ions are implanted into the semiconductor substrate whose upper layer is formed of the same conductivity type epitaxial layer, thereby reducing the parasitic capacitance of the MOS capacitor. And a method for manufacturing a highly reliable semiconductor device with good latch-up resistance.

Further, according to the present invention, the implantation of oxygen ions is performed using the same mask as the ion implantation for forming the diffusion layer forming the MOS type capacitor. It is possible to provide a manufacturing method capable of easily manufacturing a highly reliable semiconductor device having good up resistance.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;

FIG. 2 is a sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating a method of manufacturing a semiconductor device according to a second embodiment of the present invention;

FIG. 4 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention;

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment of the present invention;

FIG. 6 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention;

FIG. 7 is a sectional view showing a structure of a semiconductor device according to a fifth embodiment of the present invention;

FIG. 8 is a cross-sectional view showing a structure of a conventional semiconductor device having a MOS capacitor.

FIG. 9 is an equivalent circuit diagram of a conventional semiconductor device having a MOS capacitor.

[Explanation of symbols]

11, 11a semiconductor substrate, 12, 12a epitaxial layer, 15a, 15b MOS transistor, 19
MOS type capacitor, 20 dielectric film as insulating film, 21 upper electrode as conductive film, 22 N ⁺ type diffusion layer, 26, 26b buried oxide film, 26a oxygen ion, 27 resist mask.

Claims (9)

[Claims] 1. A MOS type capacitor comprising a diffusion layer, an insulating film formed on the surface of the diffusion layer, a conductive film formed on the insulating film, and a MOS transistor on a semiconductor substrate. In the semiconductor device, the semiconductor substrate has an epitaxial layer of the same conductivity type as the semiconductor substrate in an upper layer portion, and the epitaxial layer in the MOS capacitor formation region is formed thicker than that in the MOS transistor formation region. A semiconductor device characterized by the above-mentioned. 2. A MOS type capacitor comprising a diffusion layer, an insulating film formed on the surface of the diffusion layer, a conductive film formed on the insulating film, and a MOS transistor on a semiconductor substrate. In the semiconductor device, the semiconductor substrate has an epitaxial layer of the same conductivity type as the semiconductor substrate in an upper layer portion, and a buried oxide film is formed in the epitaxial layer below the diffusion layer of the MOS capacitor. Semiconductor device. 3. The semiconductor device according to claim 2, wherein the buried oxide film is formed below the diffusion layer and in contact with the diffusion layer. 4. The semiconductor according to claim 2, wherein the buried oxide film is formed thicker than a depletion layer width at the time of reverse bias at a junction between the diffusion layer forming the MOS capacitor and the semiconductor substrate. apparatus. 5. A MOS type transistor including a diffusion layer, an insulating film formed on the surface of the diffusion layer, and a conductive film formed on the insulating film, and a MOS transistor on a semiconductor substrate. 2. A semiconductor device according to claim 1, wherein the semiconductor substrate has an epitaxial layer of a conductivity type opposite to that of the semiconductor substrate in an upper layer portion. 6. An epitaxial layer is selectively grown further in a predetermined region on a semiconductor substrate having an upper layer composed of an epitaxial layer of the same conductivity type to form a thicker layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said MOS transistor is formed in said thin region of said epitaxial layer. 7. A semiconductor substrate whose upper layer portion is formed of an epitaxial layer of the same conductivity type is selectively etched to remove a predetermined region of the epitaxial layer by a predetermined thickness to reduce the thickness thereof. 2. The method according to claim 1, wherein a type transistor is formed in the predetermined region where the epitaxial layer is thin, and a MOS type capacitor is formed in a region where the epitaxial layer is thick. 8. A buried oxide film is formed by heat treatment after injecting oxygen ions into a semiconductor substrate whose upper layer portion is constituted by an epitaxial layer of the same conductivity type. The manufacturing method of the semiconductor device described in the above. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the implantation of oxygen ions is performed using the same mask as the implantation of ions for forming a diffusion layer forming the MOS capacitor.