JPH1185606A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory controller with which a CPU can perform other processing by outputting data from the CPU in a short time and releasing the CPU when writing data in a DRAM. SOLUTION: When writing plural pieces of continuous word data from a CPU 1 to a DRAM 2, first of all, the CPU 1 sends the first data of plural continuous words to a data latch 4, latches them in respective latch parts 4a-4d, outputs these address data to a data latch 3 and latches them. Afterwards, the data of plural words in the data latch 4 are outputted to the DRAM 2, and the word data are written in the area designated by the address data supplied from the data latch 3. Parallelly with this write processing, the next data of plural continuous words are outputted from the CPU 1 and latched in the data latch 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory controller for controlling writing of data to a memory such as a DRAM (Dynamic RAM).

[0002]

2. Description of the Related Art Various memories are used in electronic devices such as personal computers and printing devices. For example, a DRAM is used as a frame memory in a printing apparatus, and data is stored depending on whether charges are stored in a capacitor.

Conventionally, when data is written to such a DRAM, for example, a row address is input in the first half of one writing cycle and a column address is input in the second half, but the RAS signal (row address) is used for this address switching. (Strobe) and CAS signal (column address strobe) are required. That is, first, the RAS signal is output, then the CAS signal is output, the WE signal (write signal) is output to the area of the DRAM addressed by both signals, and the data is written.

[0004] The above-described processing is performed every time the CPU accesses the DRAM.

[0005]

In the conventional memory control, since the RAS signal and the CAS signal are used as described above, it takes time to write data to the memory (many clocks are used. In addition, the CPU has to wait while writing data to the memory, so that the CPU has a long waiting time and cannot drive the CPU efficiently.

Further, since the CPU cannot execute other processing during the data writing processing to the memory, for example, in the processing of executing a certain calculation processing and writing the calculation result to the memory, the CPU performs the calculation. The processing and the calculation result writing processing must be performed alternately, and if such an arithmetic processing is performed according to the above-described processing, much time is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem. When writing data to a memory, the CPU outputs data from the CPU in a short time and releases the CPU to perform other processing on the CPU. It is intended to provide a memory controller capable of causing the memory controller to operate.

[0008]

According to a first aspect of the present invention, there is provided a storage unit for storing data of a plurality of continuous words, a data latch unit for latching the data of a plurality of words, Address latch means for latching an address at which data is to be written to the storage means, and second continuous data during writing of a first plurality of words of data from the data latch means to the storage means.
And a memory controller that latches the data of a plurality of words in the data latch means and uses the data of the second plurality of words as the next write data to the storage means.

The data output to the data latch means is, for example, data output from a CPU.
For example, the data may be output from an external storage device or an internal ROM. The address data latched by the address latch means is also output from, for example, the CPU.

The data latch means first latches data of a continuous first plurality of words, and the address latch means stores the data of the continuous first plurality of words in the storage means. Address data is latched. Then, while writing the data of the plurality of words latched by the data latch means to the storage means, the data of the continuous second plurality of words is latched by the data latch means.

With this configuration, the data of the second plurality of words latched by the data latch means is written into the storage means after the data of the first plurality of words is stored in the storage means, and the data is written into the CPU. Before the completion of the writing of the continuous plural word data into the storage means,
Can be output to the data latch means. Therefore, the CPU is released early and the CPU can perform other different processing.

According to a second aspect of the present invention, in the first aspect of the present invention, the address latch means includes: a first address latch unit for latching the data of the first plurality of continuous words; And a second address latch unit that latches data of two multiple words.

Here, the first address latch unit latches the data of the continuous first plurality of words, and the second address latch unit latches the data of the continuous second plurality of words. Is done. Then, for example, when storing the first plurality of words of data in the storage means, a data write process is performed using the address latched in the first address latch unit, and for example, the second plurality of words of data are stored in the storage means. When the data is stored, the data writing process is performed by using the address latched in the second address latch unit, and the data writing process to the storage unit is performed alternately, thereby efficiently performing the data writing process to the storage unit. .

Incidentally, the first address latch unit does not necessarily
It is not necessary to latch the data of the first consecutive plural words and to latch the data of the second consecutive plural words in the second address latch unit. .

According to a third aspect of the present invention, in the first aspect of the present invention, the data latch means has a plurality of latch units for storing each word data of the continuous plurality of words.

As described above, the data latch means has the latch section (area) for latching the data of the continuous plural words. For example, if the data of the continuous plural words is data of four words, the data latch means has four data. It has a latch section. Therefore, for example, the above-mentioned four words of data are sequentially latched by the four latch units, and thereafter output to the storage means.

The data latched by the address latch means is not limited to 4-word data, but may be 2-word, 8-word, or other data. The description of claim 4 is based on the invention of claim 1 described above.
The memory control unit includes a first sequencer that performs data latch control on the data latch unit and an address latch control on the address latch unit, and a second sequencer that performs data write control on the storage unit. Configuration.

That is, the memory control unit includes a first sequencer and a second sequencer. The first sequencer controls the latching of data to the data latch means and the latch control of address data to the address latch means. Then, latch control is performed when a plurality of word data are stored in the storage unit. The second sequencer uses the word data and address data latched under the control of the first sequencer, and outputs, for example, a RAS signal, a CAS signal, an enable signal, and a write signal (WE signal) at a predetermined timing. And data writing control when writing data to the storage means.

For example, the first sequencer latches the first plurality of word data output from the CPU in the data latch, latches the address data in the address latch means, and informs the second latch that the latch processing has been completed. At the same time as notifying the sequencer, the second sequencer writes the word data latched by the data latch unit to the storage unit (for example, DRAM) according to the address data latched by the address latch unit. When the data latched by the data latch means is output to the storage means during the write processing, for example, an acknowledgment signal is output from the second sequencer to the first sequencer, and the first sequencer outputs the first sequencer signal. Latch processing of data of two consecutive plural words is performed. At this time, read processing of address data is also performed, and new address data is used for writing data of a second continuous word.

Thereafter, by repeating the above processing,
Using the first sequencer and the second sequencer, data can be written to a storage means (for example, a DRAM). At this time, the CPU can continuously output data of a plurality of continuous words twice. The CPU can be released after outputting the data to perform other processing.

According to a fifth aspect of the present invention, there is provided a storage unit for storing data of a single word, a data latch unit for latching the data of a single word,
Address latch means for latching an address at which the single-word data is to be written to the storage means; and a second single word during writing of the first single-word data from the data latch means to the storage means. Is latched by the data latch means, and a memory controller having the data of the second single word as the next write data to the storage means is provided.

According to the present invention, while the invention of claim 1 targets data of a plurality of continuous words,
The present invention is different in that the present invention is applied to single word data. In the case of this example as well, although there is a distinction between single word data and multiple word data, the single word data is latched in the data latch means, and the address of the single data is stored in the address latch means. The latching process is the same. The first single word is latched in the data latch means, and the second single word is output (latched) to the data latch means while the latched data is output to the storage means. , And outputs the latch data to the storage means. During this time, an empty area is created in the data latch means, and the second single word data is written into this area.

With this configuration, even in the case of single word data, the CPU outputs the second single word data to the data latch unit before the writing of the single word data to the storage unit is completed. Thus, the CPU can be released early to cause the CPU to execute another process.

According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the address latch means includes a first address latch unit for latching the data of the first single word, and the second unit. And a second address latch unit that latches one word of data.

The description of claim 6 corresponds to the description of claim 2 for the continuous plural word data. Therefore, in the above-mentioned claim, the address latch means has first and second latch portions, and the first and second latch portions are provided.
For example, the address of the single word data is alternately input to the latch section, and the single word data is written to the storage means by the address data.

According to a seventh aspect of the present invention, in the fifth aspect of the invention, the memory control unit performs a data latch control on the data latch unit and an address latch control on the address latch unit. And a second sequencer for controlling writing of data to the storage means.
This is a configuration composed of

[0027] The description of claim 7 also corresponds to the description of claim 4 for the data of the continuous plural words. Therefore, the process of writing data using the first sequencer and the second sequencer is the same as that of the fourth aspect.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. <First Embodiment> Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system configuration diagram of the memory controller of the present embodiment. In FIG. 1, a CPU 1 is a central processing unit of the system applied in this embodiment. This system corresponds to, for example, a control system in a printer, and has a configuration in which data output from a CPU 1 is written into a DRAM 2. Also, this system has an address latch 3
, A data latch 4 is also provided, and a memory control unit 5 is also provided. The memory control unit 5 further includes a CPU sequencer 6 and a RAM sequencer 7.

The address latch 3 comprises a latch section 3a as a first address latch and a latch section 3b as a second address latch, and the latch sections 3a and 3b have CPs.
The address data output from U1 is latched. The data latch 4 includes four latch units 4a to 4d, and each of the latch units 4a to 4d has
The word data is latched. Here, in this example, one-word data is described as, for example, 64-bit data. Therefore, each of the above-mentioned latch sections 4a to 4d is formed of an area which can latch 64-bit data.

The memory control unit 5 comprises the CPU sequencer 6 and the RAM sequencer 7 as described above, and the CPU sequencer 6 exchanges control signals with the CPU 1.
The CPU 1 outputs a system command (SYS-CMD) to the CPU sequencer 6 and outputs a valid out signal (ValidOut). On the other hand, the CPU sequencer 6
Outputs a valid-in signal (ValidIn) signal to the CPU 1 and a ready signal (RW-Rdy). The system command (SYS-CMD) is a command for notifying the output state of the CPU 1 to the CPU sequencer 6, and the ready signal (RW-Rdy) is a signal for notifying the CPU 1 that preparation on the CPU sequencer 6 side is completed. .

The CPU sequencer 6 determines the state of the data latch 4 from the state of the system command (SYS-CMD). From this determination result, the CPU sequencer 6 outputs the latch data from the data latch 4 at a predetermined timing.
The word data is output to the area designated by the address data output from the address latch 3.

A control signal is also transmitted and received between the CPU sequencer 6 and the RAM sequencer 7, and a write request signal (RAM-sq-rq) is output from the CPU sequencer 6 to the RAM sequencer 7, and the RAM sequencer 7 outputs the write request signal. C
An acknowledge signal (RAM-sq-ak) is output to the PU sequencer 6.

The processing operation of the memory controller having the above configuration will be described below. This example describes an example of a block write, and FIG. 2 shows a time chart thereof. FIG. 3 is a sequence diagram of the CPU sequencer 6 during block write, and FIG. 4 is a sequence diagram of the RAM sequencer 7 during block write.

First, in the initial state (timing S0 in the sequence diagram of FIG. 3 and timing T0 in the sequence diagram of FIG. 4), a valid-out signal (ValidOu) is sent from the CPU 1.
t) has not been output, and the word data write process has not yet started.

Thereafter, when a valid-out signal (ValidOut) is output from the CPU 1 and the process of writing data to the DRAM 2 is started, the CPU 1 sets the address latch 3
Outputs address data (SYS-AD) to. This address data (SYS-AD) is output to the latch units 3a and 3b of the address latch 3. The block write instruction command is output to the CPU sequencer 6 as the above-described system command (SYS-CMD).
Executes the process 1 shown in FIG. 3 and starts the block write process. Here, this example describes the processing of block write, and the processing of single write will be described in the second embodiment of the present invention.

The timing S1 shown in FIG.
2 is a processing timing when data is read from the second data. Next, the CPU sequencer 6 latches the address data (SYS-AD) supplied to the address latch 3 according to the above instruction. Note that a latch instruction from the CPU sequencer 6 to the address latch 3 is performed using a signal line (not shown). still,
This period is the timing of "A" shown in FIG.

On the other hand, when the ready signal (RW-Rdy) is supplied from the CPU sequencer 6, the CPU 1 outputs word data (Data) to the data latch 4. The output of the ready signal (RW-Rdy) is a signal output when the CPU sequencer 6 determines the state of the data latch 4 and determines that data latch is possible. The word data (Data) output from the CPU 1 is supplied to the data latch 4 and latched according to the output timing of the data latch enable signal (/ DataLatch-EN0 to 1) supplied from the CPU sequencer 6. For example, the first word data (Da
ta0) is the data latch enable signal (/ DataLatch-E
N0), the second word data (Data1) is latched by the latch section 4a of the data latch 4 according to the output timing.
Are latched by the latch unit 4b according to the output timing of the data latch enable signal (/ DataLatch-EN1).
Hereinafter, the same applies to the third and fourth word data (Data2,3), which are latched by the latch units 4c and 4d in accordance with the output timing of the corresponding data latch enable signal (/ DataLatch-EN2,3). Note that this period is the timing of "B" shown in FIG.

The above processing corresponds to timings S4 to S6 and S9 in the sequence diagram of FIG. 3 and timings T1 to T4 in the sequence diagram of FIG. As shown in the sequence diagram of FIG. 3, the CPU sequencer 6 outputs an acknowledge signal (/ RAM-sq-ak) after timing S6.
The process moves to timing S9. Further, as shown in the sequence diagram of FIG. 4, the RAM sequencer 7 outputs an acknowledge signal (/ RAM-sq-ak) and then shifts to timings T1 to T4.

On the other hand, the fourth word data (Data
3) In other words, when the last word data is output, a system command (SY
S-CMD) is output from the CPU 1 to the CPU sequencer 6, and the CPU sequencer 6 knows that the last word data has been output.

On the other hand, during this period (the period of "B" described above), the CPU sequencer 6 outputs a write request signal (/ RAM-sq-rq) to the RAM sequencer 7 as described above, and the RA
The M sequencer 7 receives the write request signal (/ RAM-sq-rq)
On the other hand, if data writing to the DRAM 2 is possible, an acknowledge signal (/ RAM-sq-ak) is returned.
Note that the acknowledge signal (/ RAM-sq-ak) is returned by the DRA
Write processing of word data (Data) to M2, DR
This signal is output when the reading process of the word data (word data (Data)) from the AM 2 is not performed.

The write enable signal (/ RAM-sq-
When ak) is supplied, the CPU sequencer 6 controls the output of the word data (Data0 to Data3) latched in the data latch 4. That is, the CPU sequencer 6 sequentially outputs four word data (Data0 to Data3) from the data latch 4 at timings indicated by "C" to "F" in FIG. For example, the first word data (Data0, SDATA0)
Is output to the DRAM 2 at the timing of S6, the second word data (Data1, SDATA1) is output to the DRAM 2 at the timing of Sb, and the third word data (Data2, SDATA2) is output at the timing of S4.
The fourth (last) word data (Data3, SDATA3) output to the RAM2 is output at the timing of S6.
Output to AM2.

On the other hand, from the RAM sequencer 7, R
An AS signal is output, a WE signal (write signal) is output, and then a CAS signal is output at a predetermined timing.
That is, the CAS signal is output at a predetermined timing,
Write word data (Data) to the DRAM 2. For example, the first word data (Data0, SDATA0) is
At the same T3 timing as the above-described S6 timing, CA
S signal is output and the first word data (Da
ta0, SDATA0). At this time, the address data is output from the latch section 3b of the data latch 3, and the first word data (Data0, SDATA0) is
The data is written in the area indicated by the address data.
Further, the next second word data (Data1, SDAT)
A1) also has the same T5 as the timing of Sb described above.
The CAS signal is output at the timing of (2), and the second word data (Data1, SDATA1) is written into the DRAM 2. Also at this time, address data for writing the second word data is output from the latch section 3b of the data latch 3, and the second word data (Data1, SDATA) is output.
1) is written in the area indicated by the address data.

The same applies to the write processing of the third and fourth (last) word data (Data2,3, SDATA2,3), and the corresponding timing T
At 7 and T9, a CAS signal is output to the DRAM 2, and word data is written to an area according to the address data output from the address latch 3 (latch unit 3b).

Therefore, the first four consecutive words of data (Data0 to 3, SDATA0 to 3) by the above-described processing.
Is written to the DRAM 2 by the RAM sequencer 7.
Is completed at a timing up to T9.

Conventionally, the process of writing the next four consecutive words of data has been started from this point of time, so that it took time to write the data and the CPU 1 could not be released early.

Therefore, in the present embodiment, as shown in the time chart of FIG. 2, the next four words of data writing processing are performed by the RAM sequencer 7 from the acknowledge signal (/ RAM-s
When (q-ak) is output (timing in FIG. 3), the ready signal (/ RW-Rdy) is activated at the next clock timing (timing in FIG. 3), and the next continuous word from the CPU 1 is output. This is a configuration that enables data output. That is, while the word data before being latched by the data latch 4 is developed in the DRAM 2, the data writing process of the next continuous 4-word data is started.

More specifically, a data write request signal (RA
When M-sq-rq) is output, the address data of the next successive block write is output to the data latch 3, and this address data is latched in the latch section 3a of the data latch 3 (in FIG. 3). timing). Then, as described above, four consecutive word data (Data0 to 3,
SDATA0 to SDATA3) are sequentially output to the data latch 4 and latched by the latch units 4a to 4d. In addition, word data (Data0 to 3, Data0 to SDATA0) output from the CPU 1
The information of 3) is supplied to the CPU sequencer 6, and the CPU sequencer 6 performs the data latch enable signal (/ DataLatch-EN0 to 3) supplied from the CPU sequencer 6 as described above.
) Is latched according to the output timing. That is,
During the output timings of S4 to S7, the data latch enable signals (/ DataLatch-EN0 to 3) are sequentially output, and the data is latched in the data latch 4.

Thereafter, when the fourth (last) word data (Data3) is output, a system command (SYS-CMD) indicating that the final data has been output is output to the CPU sequencer 6, and the CPU sequencer 6 outputs Knows that the CPU 1 has output the last word data (Data3, SDATA3). Therefore, in this example, between S4 and S7 of the CPU sequencer 6 (T7 of the RAM sequencer 7).
During the period from to Ta), the new 4-word data latching process for the data latch 4 and the previous 4-word data output process are performed simultaneously, but the data latch 4 has four latch units 4a to 4d. And the first word data (Data0
, SDATA0) and the fourth word data (Data3
, SDATA3) are latched in each area, so there is no problem.

That is, at the timing (S4 or T7) at which the CPU sequencer 6 latches new word data (Data0, SDATA0) in the latch unit 4a, the previous one word data has already been output from the latch unit 4a to the DRAM 2. Thus, new one-word data can be latched. The data of one word before being latched by the latch 4a is output to the DRAM 2 at the timing (S6 or T3). Further, the CPU sequencer 6 stores new word data (Data1) in the latch section 4b.
, SDATA1) at the timing (S5 or T8), the previous word data has already been output from the latch unit 4b to the DRAM 2, and the data of one new word can be latched. Also in this case, the data of one word before latched by the latch 4b is
It is output to the DRAM 2 at the timing of (Sb or T5).

The same applies to the latch units 4c and 4d. At the timing when new word data is latched in the latch units 4c and 4d, the previous word data has already been output to the DRAM 2, and each new word data has been output. One word of data can be latched. Then, the four words of data latched by the data latch 4 in this manner have the RAS signal, CAS signal, and WE signal together.
Is output to the DRAM 2 at the timing shown in FIG. However, FIG.
Are not shown.

As described above, the output of the word data supplied from the CPU 1 for two consecutive times is latched in the data latch 4 and then developed in the DRAM 2 so that, as shown in FIG. Can be released (see FIG. 2).

Therefore, the CPU 1 can perform other processing during this time, thereby increasing the utilization rate of the CPU 1 and performing efficient processing. For example, in a scientific calculation, when a calculation process and a process of writing the result to the DRAM 2 are continuous, the CPU 1 can perform the next calculation process during the process of writing the calculation result to the DRAM 2, and perform an extremely efficient process. It can be carried out. <Second Embodiment> Next, a second embodiment of the present invention will be described.

This embodiment relates to a single write of word data, in contrast to the embodiment described above for block write of word data. Here, FIG. 5 is a system configuration diagram illustrating this example, and FIG.
FIG. 7 is a time chart of the single write process, and FIG. 7 is a flowchart thereof.

In the single write of this embodiment, the processing is basically the same as that of the block write described above. One word data is latched in the data latch 4 and output to the DRAM 2 while the next one word data is stored in the data latch. The difference is that the latch is performed by the latch 4. Therefore, the configuration of this example is the system configuration shown in FIG. That is, the data latch 4 is constituted by one latch unit, and the CPU sequencer 6
Is a configuration that outputs a data latch enable signal (/ DataLatch-EN) to the single data latch 4 and latches data output from the CPU 1 in the data latch 4.

The configurations of the CPU 1, the DRAM 2, the address latches 3 (3a, 3b), the data latch 4, the CPU sequencer 6, and the RAM sequencer 7 are the same as those of the above-described embodiment. The difference is that it is a writing process.

Hereinafter, a specific description will be given. First, CPU1
Is the same as the above at the initial stage (timing U in FIGS. 6 and 7).
0), a standby state, and when a valid-out signal (ValidOut) is output from the CPU 1, address data (SY) for single write is written to the address latch 3.
S-AD). This address data (SYS-AD)
Latched together by the latch sections 3a and 3b of the address latch 3 (the output timing of "A '" in FIG.
1). The single write instruction command is output to the CPU sequencer 6 as the above-mentioned system command (SYS-CMD). The CPU sequencer 6 recognizes that this is a single write instruction by this signal.

Next, since the ready signal (RW-Rdy) output from the CPU sequencer 6 is at a low level, the CPU 1 outputs one-word word data to the data latch 4, and outputs a data latch enable signal (/ DataLatch). -EN
) Is latched in the data latch 4 (the output timing of "B '" in FIG. 4, timing U2).

Next, the acknowledge signal is output from the RAM sequencer 7 to the CPU sequencer 6, and the ready signal (RW-Rdy) output from the CPU sequencer 6 is still at the low level. Is output to the latch unit 3b of the data latch 3 (FIG. 4).
Output timing of “G ′”, timing U1). Next, new one-word data is supplied from the CPU 1 to the data latch 4 (the output timing of "H '" in FIG. 4, timing U2).

On the other hand, the first one-word data latched by the data latch 4 is output to the DRAM 2 at the timing "H '" where the RAS signal, CAS signal and WE signal overlap. At the same time, new one-word data is latched in the data latch 4. Then, the data latched next as described above is supplied to the DRAM 2 later, and the DRA
Written to M2.

Accordingly, by performing the above processing, the CPU 1 is released until the next two words of data are output. For example, during this time, other processing can be performed as described above, and the utilization rate of the CPU 1 is reduced. And efficient processing can be performed.

[0062]

As described above, according to the present invention, C
The PU can be released early for other processing and the CP
U can be used efficiently.

Further, it is possible to cause the CPU to perform other processing, thereby enabling quick task processing.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a memory controller according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a process in the case of a block write.

FIG. 3 is a CPU for explaining a process in the case of a block write;
FIG. 7 is a sequence diagram of the sequencer 6.

FIG. 4 is a RAM for explaining processing in the case of block write;
FIG. 7 is a sequence diagram of the sequencer 7.

FIG. 5 is a system configuration diagram in the case of a single write.

FIG. 6 is a flowchart illustrating a process in the case of a single write.

FIG. 7 is a sequence diagram illustrating a process for a single write.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 DRAM 3 Address latch 3a, 3b Latch part 4 Data latch 4a-4d Latch part 5 Memory control part 6 CPU sequencer 7 RAM sequencer

Claims (7)

[Claims] A storage unit for storing data of a plurality of continuous words; a data latch unit for latching the data of the plurality of words; an address latch unit for latching an address for writing data in the storage unit; The first from the means to the storage means
A memory for latching continuous data of a second plurality of words in the data latch means while writing the data of the plurality of words, and using the data of the second plurality of words as next write data to the storage means A memory controller, comprising: a control unit; 2. The address latch means according to claim 1, wherein said first data latch unit latches said continuous first plurality of words of data, and a second data latch which latches said continuous second plurality of words of data. 2. The memory controller according to claim 1, comprising a unit. 3. The memory controller according to claim 1, wherein said data latch means includes a plurality of latch units for storing respective word data of said continuous plurality of word data. 4. A first sequencer for performing a data latch control on the data latch means and an address latch control on the address latch means,
2. The memory controller according to claim 1, further comprising a second sequencer for controlling writing of data to said storage means. 5. A storage unit for storing data of a single word, a data latch unit for latching the data of the single word, and an address latch unit for latching an address for writing the data of the single word in the storage unit. While writing the first single-word data from the data latch means to the storage means, latching the second single-word data into the data latch means; A memory control unit for making data the next write data to the storage means. 6. The address latch means comprises: a first data latch unit for latching the first single word data; and a second data latch unit for latching the second single word data. 6. The memory controller according to claim 5, further comprising: 7. A first sequencer for performing a data latch control on the data latch means and an address latch control on the address latch means,
6. The memory controller according to claim 5, further comprising a second sequencer for controlling writing of data to said storage means.