JPH1169263A - Vertical blanking generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent V fluctuation (fluctuation on vertical synchronization signal, when a signal including much noise is received) in an image by avoiding deviation in the timing of a vertical blanking signal with noise superimposed on a horizontal synchronization signal H-sync. SOLUTION: A signal from a leading edge detection section 6 clears counters 7, 8 and a dot clock from a phase-locked loop circuit 1 is counted by the counter 7 and given to an X-count decoder 9, and a pulse is outputted by a set X value. An S-R-FF circuit 11 is set, the H=sync is counted by the counter 8 and given to a Y-count decoder 10, and a pulse is outputted with a set Y-value. The S-R-FF circuit 11 is reset, and a signal from the S-R-FF circuit 11 is outputted as a vertical blanking signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical blanking generation circuit, and relates to a weak electric field TV broadcast signal or VTR.
To reduce backlash (V play) in vertical synchronization at the time of input of a noisy signal in special reproduction or the like.

[0002]

2. Description of the Related Art PDP (Plasma Display Panel)
Alternatively, in a digital display device such as an LCD (liquid crystal panel), a display position of an image is determined by a blanking signal. That is, the first horizontal line starts at the end of vertical blanking, and each horizontal line starts at the end of horizontal blanking. The horizontal blanking signal is generated by counting a dot clock, and the vertical blanking signal is generated by counting a horizontal synchronizing signal. At the time of input, noise may be added to the horizontal synchronizing signal, and the noise may shift the generation timing of the vertical blanking signal. In particular, when the rising timing of the vertical blanking signal fluctuates, V appears on the screen, which is noticeable.

[0003]

SUMMARY OF THE INVENTION In view of the foregoing, the present invention does not shift the rising timing of a vertical blanking signal due to noise or the like superimposed on a horizontal synchronizing signal, and reduces the V play on the screen. Is to prevent it.

[0004]

According to the present invention, there is provided a first counter which counts a dot clock synchronized with a horizontal synchronizing signal and is cleared by a vertical synchronizing signal.
A first decoder that decodes a signal from the first counter with a required count value and outputs a pulse, a second counter that counts a horizontal synchronization signal and is cleared by a vertical synchronization signal, and requires a signal from the second counter A second decoder that decodes with the count value of the above and outputs a pulse, a first S-R-FF (set / reset type flip-flop) circuit that is set by a pulse from the first decoder and reset by a pulse from the second decoder And a vertical blanking generation circuit for outputting a vertical blanking signal from the first SR-FF circuit.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a vertical blanking generation circuit according to the present invention, a first counter is cleared at a rising edge of a vertical synchronization signal, and a dot clock synchronized with a horizontal synchronization signal generated by a PLL circuit or the like is counted. A pulse is output from the first decoder with a required count value by the signal from the first counter, the second counter is cleared at the rising edge of the vertical synchronization signal, the horizontal synchronization signal is counted, and the signal from the second counter is output. A pulse is output from the second decoder with a required count value, the first S-R-FF circuit is set with a pulse from the first decoder, and reset with a pulse from the second decoder;
Generate a vertical blanking signal. The vertical blanking signal from the first S-R-FF circuit is latched by a first D-FF (D-type flip-flop) circuit as a horizontal blanking signal, and the signal from the first D-FF circuit is latched by a second D-FF circuit. The circuit latches with a horizontal blanking signal, the signal from the first D-FF circuit and the signal from the second D-FF circuit are selected by the first selector, and the second S-R-FF circuit is vertically blanked. Set at rising edge of signal, reset at rising edge of horizontal blanking signal, enable by signal from second S-R-FF circuit, count required clock by third counter cleared at rising edge of vertical blanking signal The count data is held in the register at the timing of the rising edge of the horizontal blanking signal, and the data from the register is compared with the first data set in advance. 1 selector to the 1D-FF circuit side, switching to the 2D-FF circuit side when data from the register is less outputs.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a vertical blanking generation circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram of a main part of an embodiment of a vertical blanking generation circuit according to the present invention. In the figure, reference numeral 1 denotes a PLL (phase locked loop) circuit, which includes a phase comparator 2, an LPF (low-pass filter) 3, a VCO (voltage controlled oscillator) 4, and a frequency divider 5.
And generates a dot clock synchronized with the horizontal synchronization signal (H-sync). Reference numeral 6 denotes a first rising edge detection unit which detects a rising edge of the vertical synchronization signal (V-sync). Reference numeral 7 denotes a first counter which counts a dot clock from the PLL circuit 1 and outputs a signal from the first rising edge detector 6, that is,
Cleared at the rise of V-sync. 8 is a second counter,
H-sync is counted, and cleared by a signal from the first rising edge detection unit 6. Reference numeral 9 denotes an X count decoder (first decoder) which outputs a pulse when a signal from the first counter 7 is input from a setting data terminal and reaches an X value set by a clock from a setting clock terminal. Reference numeral 10 denotes a Y count decoder (second decoder) which outputs a pulse when a signal from the second counter 8 is input from a setting data terminal and has a Y value set by a clock from a setting clock terminal. Reference numeral 11 denotes a first S-R-FF circuit, which is set by a pulse from the X count decoder 9 and reset by a pulse from the Y count decoder 10, and rises and resets by the set (X) as shown in the timing chart of FIG. A vertical blanking signal falling at Y) is output.

FIG. 3 is a block diagram showing a main part of another embodiment of the vertical blanking generation circuit according to the present invention. In FIG.
The FF circuit latches the vertical blanking signal from the first S-R-FF circuit 11 in FIG. 1 with a horizontal blanking signal generated by another circuit. A second D-FF circuit 22 latches a signal from the first D-FF circuit 21 with a horizontal blanking signal. Reference numeral 23 denotes a second rising edge detection unit which detects a rising edge of the vertical blanking signal. 24 is a third rising edge detector,
The rising edge of the horizontal blanking signal is detected. Reference numeral 25 denotes a second S-R-FF circuit, which is set by a signal from the second rising edge detection unit 23 and reset by a signal from the third rising edge detection unit 24, that is, the rising edge of the horizontal blanking signal. A third counter 26 enables a signal from the second S-R-FF circuit 25, counts a required clock, and is cleared by a signal from the second rising edge detector 23. Reference numeral 27 denotes a register which holds the output data of the third counter 26 at the timing of the signal from the third rising edge detector 24. Reference numeral 28 denotes first data (fixed data), which is, for example, one half of the count value of one horizontal blanking period N. 29 is a comparator which compares the data from the register 27 with the first data N / 2, and when the data from the register 27 is large, the signal Lo
, And outputs a signal Hi when it is small. Reference numeral 30 denotes a first selector, which receives a signal Lo from the comparator 29 and outputs a (first D-FF circuit).
21), and is switched to b (second D-FF circuit 22) by signal Hi. FIG. 4 is a timing chart of the circuit of FIG.

FIG. 5 is a block diagram of a main part of another embodiment of the vertical blanking generation circuit according to the present invention. In FIG. 5, reference numeral 31 denotes second data, which is smaller than the first data 28 and is N / 2-α. .
32 is the third data, which is larger than the first data 28, N / 2 +
α. A second selector 33 switches to the second data 31 side by the signal Lo from the comparator 29 and switches to the third data 32 side by the signal Hi. Other reference numerals are the same as those in FIG.

Next, the operation of the vertical blanking generation circuit according to the present invention will be described. First, in the case of FIG. 1, the dot clock synchronized with H-sync from the PLL circuit 1 is counted by the first counter 7 which is cleared by the rising edge of V-sync from the first rising edge detection unit 6. The signal is applied to the X count decoder 9, and as shown in FIG. 2, when the count value reaches the set X (the number of dot clocks), a pulse is output from the X count decoder 9 and the first S-R- FF circuit 11
Is set. Then, the second counter 8 (cleared at the rising edge of V-sync from the first rising edge detection unit 6) counts H-sync, and outputs this signal to a Y count decoder.
When the count value reaches the set Y (the number of dot clocks), a pulse is output from the Y count decoder 10 and the first S-R-FF circuit 11 is reset. As a result, the first S-R-FF circuit 11 outputs a vertical blanking signal that rises with the number of dot clocks X and falls with the number of dot clocks Y from the rise of V-sync. Therefore, the vertical blanking signal is not affected even when noise is superimposed on H-sync.

When the rising timing of the vertical blanking signal is in the period of Hi of the horizontal blanking signal, the horizontal position of the top line on the screen is shifted. If the vertical blanking signal is latched by horizontal blanking using a latch circuit, the phases of both blanking signals can be matched. However, when the vertical blanking signal is delayed, the vertical blanking signal is delayed by 1H by the latch.
For example, when the horizontal / vertical blanking phase fluctuates in an unstable manner in the special reproduction of a VTR or the like, the rising timing of the vertical blanking may be shifted by 1H.

FIG. 3 shows a circuit for adjusting the phase so as not to cause this 1H "blur", which is provided at a stage subsequent to the circuit shown in FIG. That is, the vertical blanking signal from the first S-R-FF circuit 11 is input to the first D-FF circuit 21, latched by the horizontal blanking signal, and output to the terminal a of the first selector. The signal is applied to the 2D-FF circuit 22, latched by the horizontal blanking signal (two times in total), and output to the terminal b of the first selector. The rising edge of the vertical blanking signal is detected by the second rising edge detector 23, and the second S-R-
The FF circuit 25 is set, the rising edge of the horizontal blanking signal is detected by the third rising edge detector 24, and the second S-R-FF circuit 25 is reset by this signal. And the second S-R-FF
The third counter 26 is enabled by a signal from the circuit 25, that is, a signal from the rising of the vertical blanking signal to the rising of the first horizontal blanking signal, and the signal from the second rising edge detecting unit 23 is used. Until it is cleared, the required clock is counted and this data is stored in register 27.
, And is held at the timing of the signal from the third rising edge detection unit 24, and is input to the comparator 29 (A). One half of the count value of one horizontal blanking cycle N (N / 2 data, B ). When the data A from the register 27 is large, the signal Lo is output, and when the data A is small, the signal Hi is output.
The signal Lo moves the first selector 30 to the a (first D-FF circuit 21) side,
The signal Hi is switched to the b (second D-FF circuit 22) side. Thereby, as shown in FIG. 4, when the phase difference between the rising edge of the vertical blanking signal and the rising edge of the horizontal blanking signal is N / 2 or less (timing -1), the second D-FF circuit 22 latches twice. If the obtained vertical blanking signal has a phase difference of N / 2 or more (timing-2), the once latched vertical blanking signal from the first D-FF circuit 22 is output, and the next coming horizontal blanking signal Is output at the timing coincident with the rising edge of. Note that this causes the vertical blanking signal to be delayed by 1H, so that the design is made in advance in consideration of this delay.

When the phase of the vertical blanking signal is close to N / 2, there is a possibility that 1H "blur" occurs at the rising timing of the vertical blanking signal. FIG. 5 shows a circuit (reference numeral 21) for preventing this "blur".
30 is the same as FIG. 3), and the first data 28 (N / 2) in FIG.
With hysteresis. That is, N / 2
A second smaller data 31 (N / 2−α) and a third larger data 32 (N / 2 + α) larger than N / 2 are provided.
When the phase difference between the horizontal and vertical blanking signals is large (signal from the comparator 29: Lo), the second selector 33 is set to the A (second data 31) side and the phase difference is small ( The signal from the comparator 29 (Hi) is switched to the B (third data 32) side.
Of the vertical blanking signal and the rising edge of the vertical blanking signal. The first data 28, the second data 31, and the third data 32 may be arbitrarily set from outside.

[0013]

As described above, according to the vertical blanking generation circuit of the present invention, the vertical blanking signal is generated based on the dot clock count.
For example, even when noise is superimposed on H-sync during special reproduction of a VTR or the like, the generation timing of the vertical blanking signal does not change, and no V rattling occurs on the screen.

[Brief description of the drawings]

FIG. 1 is a main part block diagram of an embodiment of a vertical blanking generation circuit according to the present invention.

FIG. 2 is a timing chart of a vertical blanking signal.

FIG. 3 is a main part block diagram of another embodiment of the vertical blanking generation circuit according to the present invention.

FIG. 4 is a timing chart of a vertical blanking signal of the circuit of FIG. 3;

FIG. 5 is a main part block diagram of another embodiment of the vertical blanking generation circuit according to the present invention.

[Explanation of symbols]

 1 PLL circuit 6, 23, 24 Rising edge detector 7, 8, 26 Counter 9, 10 Decoder 11, 25 S-R-FF circuit 21, 22 D-FF circuit 27 Register 29 Comparator 30, 33 Selector

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 3/12 H04N 3/12 B 3/24 3/24 5/06 5/06 A

Claims (8)

[Claims] 1. A first counter which counts a dot clock synchronized with a horizontal synchronization signal and is cleared by a vertical synchronization signal, and a first decoder which decodes a signal from the first counter with a required count value and outputs a pulse. A second counter that counts a horizontal synchronization signal and is cleared by a vertical synchronization signal, a second decoder that decodes a signal from the second counter with a required count value and outputs a pulse, and a pulse from the first decoder And a first S-R-FF circuit which is reset by a pulse from the second decoder.
A vertical blanking generation circuit configured to output a vertical blanking signal from an SR-FF circuit. 2. A system according to claim 1, further comprising a first rising edge detector for detecting a rising edge of said vertical synchronizing signal, wherein said first counter and said second counter are cleared by a signal from said first rising edge detector. 2. The vertical blanking generation circuit according to 1. 3. The vertical blanking generation circuit according to claim 1, wherein the decode values of the first decoder and the second decoder can be arbitrarily set from outside. 4. The vertical blanking generation circuit according to claim 1, wherein said second counter counts said dot clock. 5. A first D-FF circuit for latching a vertical blanking signal from the first SR-FF circuit with a required horizontal blanking signal, and a signal from the first D-FF circuit as a horizontal blanking signal. Second D-FF latched by
And a signal from the first D-FF circuit or a second D-FF circuit.
A first selector for selecting and outputting a signal from the FF circuit, a second rising edge detector for detecting a rising edge of the vertical blanking signal, and the horizontal selector set by a signal from a second rising edge detector. A second SR-FF circuit reset at the rising edge of the blanking signal;
A signal from the R-FF circuit is enabled, a required clock is counted, a third counter cleared by a signal from the second rising edge detector, and output data of the third counter are converted to the third rising edge. The register held at the timing of the signal from the detection unit is compared with the data from the register and the first data set in advance. When the data from the register is large, the signal Lo is obtained, and when the data from the register is small, And a comparator that outputs a signal Hi. The first selector is connected to the first D-FF circuit side by the signal Lo from the comparator, and the signal Hi from the comparator is provided.
5. The vertical blanking generation circuit according to claim 1, wherein the first selector is switched to the second D-FF circuit side. 6. A second data smaller than the first data, a third data larger than the first data, and a signal Lo from the comparator are used to convert the second data into a signal Hi from the comparator. Select the third data in the second
6. The vertical blanking generation circuit according to claim 5, further comprising a selector, wherein the comparator compares data from the register with data from a second selector. 7. A circuit according to claim 1, further comprising a third rising edge detector for detecting a rising edge of said horizontal blanking signal, wherein said second SR-FF circuit is reset by a signal from said third rising edge detector. 7. The vertical blanking generation circuit according to claim 5 or 6. 8. The vertical blanking generation circuit according to claim 5, wherein the first data, the second data, and the third data can be arbitrarily set from outside. .