JPH1169650A - Hysteresis inverter circuit, charge-discharge protective circuit and battery pack - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a chip area, to lower power consumption and to decrease the consumption of a secondary battery, by connecting a step-up hysteresis circuit and a step-down hysteresis circuit between power supply potential and a first (p) channel MOSFET. SOLUTION: In a first-stage inverter circuit, a first (p) channel MOSFET Q42 connected at power supply potential VDD and a first (n) channel MOSFET Q4-connected to ground potential VDD are joined while each gate of both MOSFETs is used as common inputs and each drain as common outputs. Step-up hysteresis circuits Q41, Q45 setting an input voltage threshold level Vth at the time of the increase of the input voltage of the first-stage inverter circuit are connected between power supply potential VDD and the first (p) channel MOSFET Q42. Step-down hysteresis circuits Q44, Q46 setting an input-voltage threshold level VtL at the time of the lowering of input voltage are joined between the ground potential VSS and the first (n) channel MOSFET Q43.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a hysteresis inverter circuit having a hysteresis characteristic at an input voltage threshold level.

The present invention also relates to a secondary battery charge / discharge circuit, and more particularly, to an overcharged state of the secondary battery during charge control, an overdischarged state of the secondary battery during discharge control for supplying load current, or discharge. The present invention relates to a charge / discharge protection circuit that detects an overcurrent state of a secondary battery during control and protects the secondary battery from an overcharged state, an overdischarged state, or an overcurrent state.

[0003] The present invention also relates to a battery device, and more particularly to a battery pack of a secondary battery which can be charged and discharged using a charge and discharge protection circuit.

[0004]

2. Description of the Related Art FIG. 8 is a circuit block diagram for explaining a conventional charge / discharge control circuit.

A conventional charge / discharge protection circuit and a battery pack of this type are disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 6-104015 (Title of Invention: Battery Protection Circuit, Applicant: Sony Corporation and Nihon Motorola Corporation, Filing Date: 19
(September 17, 1992).

That is, the battery protection circuit (charge / discharge protection circuit and battery pack) A1 is composed of a detection unit A2, a control unit A3, a return unit A4, a power down SW unit A5, and a charge / discharge switch unit A6. It had a function of controlling charging and discharging of the batteries Abat and Bbat, which are batteries.

The detecting section A2 has a battery voltage detecting section A7 and an overcurrent detecting section A8. Here, the battery voltage detection unit A7 detects the overcharge (A, B) and overdischarge (A, B) states from the respective voltages of the batteries Abat, Bbat, and the overcurrent detection unit A8 detects the overcurrent state. I was

The control unit A3 includes a discharge control logic unit A9.
And a discharge SW control unit A10 and a GND level shift unit A
11 and a charging system control logic unit A12 and a charging SW control unit A13.

[0009] The discharge system control logic unit A9 and the discharge SW control unit A10 of the control unit A3 control the charge / discharge state of the batteries Abat and Bbat detected by the battery voltage detection unit A7 of the detection unit A2 and the overcurrent detection from the overcurrent detection unit A8. From the current signal state, an overflow current signal was output to the battery voltage detection unit A7, a discharge switch signal was output to the charge / discharge switch unit A6 (usually a MOSFET is used), and a power down signal was output to the return unit A4.

The ground signals from the discharge system control logic unit A9 of the control unit A3 and the discharge SW control unit A10 are supplied to the charge system control logic unit A1 via the GND level shift unit A11.
2 and the charge SW control unit A13.

The GND level shifter A11 has a different ground (GND) between the discharge switches of the discharge control logic A9 and the discharge SW controller A10 and the charge switches of the charge control logic A12 and the charge SW controller A13. , And each ground potential is determined based on a fixed reference.

The control system logic section A12 of the control section A3
The charge SW control unit A13 controls the charge / discharge switch unit A6 based on the battery state, the charge detection (mobile circuit), and the like, and the return unit A
For example, a power-down release signal is output for No. 4.

The return section A4 includes a power down control section A14.
And a start-up circuit charge detection unit A15. The power-down control unit A14 sends a power-down signal from the discharge control logic A9 to the power-down SW A5, and sends a power-down release signal from the charge control logic A12 to the power-down SW A5. Was.
Further, the start-up circuit charge detection unit A15 also has a function of automatically starting.

The power-down SW unit A5 sends a power-down signal from the power-down control unit A14 to the detection unit A2 and the control unit A3, and turns off the power to enter the power-down mode.

The charge / discharge switch unit A6 controls the discharge and charge of the batteries Abat and Bbat based on the control from the discharge SW control unit A10 and the charge SW control unit A13 of the control unit A3.

The battery protection circuit A1 having such a circuit configuration has a power-down prohibition function for preventing the power-down SW section A5 from becoming non-conductive when the batteries Abat and Bbat are overcharged. .

The battery protection circuit A1 is provided with a power supply for preventing the power-down SW unit A5 from becoming non-conductive based on an overcurrent detection signal output from the overcurrent detection means which has detected that a large current has flowed instantaneously. It also had a down prohibition function.

In such a battery protection circuit A1, when an overcurrent signal state is detected by the overcurrent detection unit A8, the charge SW control unit A13 switches the charge / discharge switch unit A6.
Is executed to inactivate.

In this state, when a load is connected between the terminals + EB and -EB, the charge / discharge switch unit A6 is inactivated. A current flows in a forward direction from the charging system GND potential V− to the discharging system GND potential Vss via the parasitic diode. As a result, the charging system GND
The potential V- increases by the forward voltage (about 0.6 V) of the parasitic diode with respect to the discharge system GND potential Vss.

Here, assuming that the overcurrent detection level (potential) in the overcurrent detector A8 is, for example, 0.2 V, the overcurrent detector A8 applies a load to the forward voltage (about 0.6 V) of the parasitic diode. It is necessary to avoid the possibility that the overcurrent state at the time of connection is detected and the charge / discharge switch unit A6 is erroneously inactivated and the current cannot be supplied to the load.

Therefore, in the battery protection circuit A1, the charging / discharging switch section A6 is activated during a predetermined time during which the load is connected between the terminals + EB and -EB, and the charged charging system G is raised.
By lowering the ND potential V- again below the overcurrent detection level, the load current when the load is connected is prevented from being erroneously detected as an overcurrent.

According to this, when an overcharge is detected at the time of connecting a load, there is an effect that the load current can flow when the battery voltage is lower than the overcharge detection voltage.

[0023]

However, in such a conventional battery protection circuit A1, in order for the load current at the time of load connection not to be erroneously detected as overcharge,
When the secondary battery potential VDD is equal to the overcharge detection voltage (for example, 4.25
V) was a prerequisite.

For this reason, when a pulse charger is used as the charger, when the secondary battery potential VDD at the time when the overcurrent with respect to the load current at the time of connection of the load is detected is maintained at the overcharge detection voltage or higher, the overcharge is detected. Since the current detection unit A8 detects an overcharged state, it is difficult to activate the charge / discharge switch unit A6, and as a result, there is a technical problem that it is difficult to supply a load current to the load. Was.

That is, if a load is connected while a pulse charger is used and the battery voltage is maintained at a level equal to or higher than the overcharge detection voltage, the load current at that time is erroneously determined to be an overcurrent. There was a technical problem that it was difficult to pass load current.

An object of the present invention is to solve such a conventional problem. First, a first p-channel MOSFET connected to a power supply potential and a first n-channel MOSFET connected to a ground potential have a gate. And a second p-channel MOSFET connected to the power supply potential and a second n-channel MOSFET connected to the ground potential. A post-stage inverter circuit connected in series as a common output, a rising hysteresis circuit connected between the power supply potential and the first p-channel MOSFET, and setting an input voltage threshold level when the input voltage of the first-stage inverter circuit rises; Connected between the ground potential and the first n-channel MOSFET, A falling hysteresis circuit for setting an input voltage threshold level when the input voltage of the inverter circuit falls, and when the input voltage of the first-stage inverter circuit rises, the first p-channel is connected to the power supply potential via the activated rising hysteresis circuit. A first n-channel MOS is connected to the MOSFET through a deactivated hysteresis circuit and a deactivated hysteresis resistance element.
The FET is connected to the ground potential, and when the input voltage of the first-stage inverter circuit falls, the first p-channel MOSFET is connected to the power supply potential via the deactivated rising hysteresis circuit and the rising hysteresis resistance element, and is activated. The first n-channel MOSFET is connected to the ground potential via the falling hysteresis circuit, so that when the overcharge is detected when the load is connected, the secondary battery potential is higher than the overcharge detection voltage. A function of supplying a load current to the load when the load is low. Even if the secondary battery potential is equal to or higher than the overcharge detection voltage, the load current when the load is connected is erroneously determined as an overcurrent and the discharge transistor is deactivated. A function to supply load current to the load while avoiding noise, and a pulse charger is used as a charger to detect overcurrent with respect to the load current when a load is connected Even if the secondary battery potential at this time is maintained at or above the overcharge detection voltage, it is possible to prevent the load transistor from being inactivated by erroneously determining that the overcurrent state has occurred and to inactivate the discharge transistor. It is an object to realize a hysteresis inverter circuit having a function of supplying.

Second, an overcharged state of the secondary battery at the time of charging control in which a charging transistor provided between the secondary battery and the load is controlled to supply a charging current to the secondary battery, A discharge transistor provided between the power supply and the load is controlled to supply a load current to the load, thereby detecting an overdischarge state of the secondary battery during discharge control or an overcurrent state of the secondary battery during discharge control. In a charge / discharge protection circuit that protects a secondary battery from an overcharged state, an overdischarged state, or an overcurrent state, a delay time required to execute a discharge control according to an overdischarge detection signal, and a delay time according to an overcurrent detection signal The timing capacitor connected to the input of the hysteresis inverter circuit and the delay signal or the overcharge In response to the input of the overcharge detection signal to the gate when the overcharge detection voltage is detected at a secondary battery potential that is higher than the overcharge detection voltage while the overcharge detection signal is received and the gate circuit that generates the delay signal related to the detection signal, A logic signal for blocking the input of the overdischarge detection signal and the overcurrent detection signal to the gate circuit and inhibiting the generation of the delay signal is output to the gate circuit, and the generation of the delay signal for activating the discharge transistor is performed. It has a shut-off MOSFET and a hysteresis inverter circuit for outputting an instruction logic signal to a gate circuit, and detects a discharge time in a secondary battery in response to an over-discharge detection signal and sets a delay time required to execute discharge control. A delay signal for setting is generated through a hysteresis inverter circuit, and is also generated in a secondary battery in response to an overcurrent detection signal. A delay signal for setting a delay time required to execute a discharge control by detecting a current state is generated via a hysteresis inverter circuit. When detecting the potential of the secondary battery, it instructs cancellation of the discharge control according to the overdischarge state and cancellation of the discharge control according to the overcurrent state, and activates the discharge transistor connected to the load to charge the transistor. Generating a delay signal for instructing discharge control for supplying a load current to a load via a parasitic diode and an activated discharging transistor which are present in parallel between the drain and the source through a hysteresis inverter circuit. Connects to the charging potential of the circuit and the charger that charges the secondary battery, and charges the battery ground potential A level shift circuit that generates a charge control signal by shifting to a ground potential of the battery, monitors a discharge state of the secondary battery connected to the secondary battery potential, and generates an overdischarge detection signal when an overdischarge state is detected. And an overcurrent detection circuit connected to the charger ground potential for monitoring the potential of the charger ground potential and generating an overcurrent detection signal when an overcurrent state is detected. A function of supplying a load current to the load when overcharge is detected when a load is connected and the secondary battery potential is lower than the overcharge detection voltage, even if the secondary battery potential is equal to or higher than the overcharge detection voltage A function to supply a load current to a load while avoiding inactivation of a discharge transistor due to erroneous determination of a load current as an overcurrent at the time of load connection, and a load at the time of load connection using a pulse charger as a charger. Electric Even if the secondary battery potential when the overcurrent is detected is held at or higher than the overcharge detection voltage, it is possible to avoid that the overcurrent state is erroneously determined and the discharge transistor is inactivated. It is an object to realize a charge / discharge protection circuit having a function of supplying a load current to a load.

Third, the state of conduction of the discharge current supplied from the battery cell to the load at the time of discharge control is determined by the logic value of the delay signal. A discharge transistor that is controlled in accordance with the charging transistor, and is connected in series between the charger and the battery cell, and controls a conduction state of a charging current supplied from the charger to the battery cell during charging control according to a logical value of a charging control signal. A charge transistor, and a delay capacitor connected to the battery ground potential, for generating a charge / discharge signal for setting a delay time required for detecting an overcharge state in the battery cell, and transmitting the signal to the overcharge detection circuit. The discharge transistor has the logical value of the discharge signal, which is the logical product of the logical value of the delay signal and the logical value of the short-circuit detection signal. The level shift circuit is configured to control a logic value for activating a charging transistor when activated according to a charger ground potential. A function of supplying a load current to the load when overcharge is detected at the time of connection of the load and the secondary battery potential is lower than the overcharge detection voltage. A function of supplying a load current to the load by avoiding that the load current at the time of load connection is erroneously determined as an overcurrent and the discharge transistor is inactivated even when the next battery potential is equal to or higher than the overcharge detection voltage; An overcurrent state even if the secondary battery potential is maintained at or above the overcharge detection voltage when a pulse charger is used as the charger and an overcurrent with respect to the load current when the load is connected is detected. Erroneous determination has been discharging transistor is an object to realize a battery pack having a function of supplying a load current to a load to avoid that would be inactivated.

[0029]

According to the present invention, a first p-channel MOSFET connected to a power supply potential is provided.
Q42 and first n-channel MOSFE connected to ground potential
A first-stage inverter circuit in which TQ43 is connected in series with a gate as a common input and a drain as a common output; a second p-channel MOSFET Q47 connected to the power supply potential; and a second n-channel MOSFET Q48 connected to the ground potential
Are connected in series with a gate as a common input and a drain as a common output, and are connected between a power supply potential and the first p-channel MOSFET Q42, and input when the input voltage of the first-stage inverter circuit rises. A rising hysteresis circuit (Q41, Q45) for setting a voltage threshold level VtH, connected between a ground potential and the first n-channel MOSFET Q43, and setting an input voltage threshold level VtL when the input voltage of the first-stage inverter circuit falls. Falling hysteresis circuit (Q
44, Q46) and the hysteresis inverter circuit 30 (Q26, Q31).

According to the first aspect of the present invention, the circuit has a simpler circuit configuration, a smaller circuit size, a smaller chip area, and lower power consumption than conventional comparators with a latch function. There is an effect that the hysteresis inverter circuit 30 (Q26, Q31) can be realized by using the rising hysteresis circuit (Q41, Q45) and the falling hysteresis circuit (Q44, Q46) which can reduce the consumption of the secondary battery 12.

According to a second aspect of the present invention, in the hysteresis inverter circuit according to the first aspect, when the input voltage of the first-stage inverter circuit rises, the rising hysteresis circuit (Q41, Q45) is activated. The first p-channel MOSFET Q42 is connected to the power supply potential, and the inactive falling hysteresis circuit (Q4
4, Q46) and the falling hysteresis resistance element Q44, so that the first n-channel MOSFET Q43 is connected to the ground potential.
(Q26, Q31).

According to the invention described in claim 2, according to claim 1,
In addition to the effects described in (1), when the input voltage of the first-stage inverter circuit rises, the activated rising hysteresis circuit (Q
41, Q45) and the first p-channel MOSF
By connecting the ETQ42, the threshold level VtH of the first-stage inverter circuit when the input voltage increases can be set based on only the threshold level pVth of the first p-channel MOSFET Q42 without enlarging the circuit scale or power consumption. There is an effect that a circuit suitable for integration can be realized.

[0033] The invention described in claim 3 is the invention according to claim 1 or 2.
In the hysteresis inverter circuit described in (1), when the input voltage of the first-stage inverter circuit falls, the first power supply potential is applied to the power supply potential via the deactivated rising hysteresis circuit (Q41, Q45) and the rising hysteresis resistance element Q41.
A hysteresis inverter circuit 30 (Q26, Q31) configured so that the p-channel MOSFET Q42 is connected and the first n-channel MOSFET Q43 is connected to the ground potential via the activated falling hysteresis circuit (Q44, Q46). It is.

According to the invention described in claim 3, according to claim 1
Or the first n-channel MOSFET through the activated falling hysteresis circuit (Q44, Q46) when the input voltage of the first-stage inverter circuit falls.
Since Q43 is connected to the ground potential, the threshold level nVth
Based on this, it is possible to realize a circuit suitable for integration in which the threshold level VtL of the first-stage inverter circuit when the input voltage falls can be set without increasing the circuit scale or power consumption.

According to a fourth aspect of the present invention, in the hysteresis inverter circuit according to the third aspect, the rising hysteresis circuit (Q41, Q45) is a p-channel MOSFE.
The hysteresis inverter circuit 30 (Q26, Q31) has a configuration in which TQ45 and the rising hysteresis resistance element Q41 are connected in parallel.

According to the invention described in claim 4, according to claim 3,
Of the p-channel MOSFET Q45 which does not involve an increase in circuit scale and power consumption in addition to the effects described in
By setting the resistance value of the rising hysteresis resistance element Q41 sufficiently larger than the N resistance value, when the input voltage of the first-stage inverter circuit rises, the power supply potential is increased via the activated rising hysteresis circuit (Q41, Q45). When the first p-channel MOSFET Q42 is connected,
The threshold level pV of the channel MOSFET Q42
It is possible to realize a circuit suitable for integration in which the threshold level VtH of the first-stage inverter circuit when the input voltage rises based only on th can be set without enlarging the circuit scale or power consumption. .

According to a fifth aspect of the present invention, in the hysteresis inverter circuit according to the third aspect, the falling hysteresis circuit (Q44, Q46) is an n-channel MOSFE.
The hysteresis inverter circuit 30 (Q26, Q31) has a configuration in which TQ46 and the falling hysteresis resistance element Q44 are connected in parallel.

According to the invention described in claim 5, according to claim 3,
Of the n-channel MOSFET Q46, which is not accompanied by an increase in circuit scale and power consumption in addition to the effects described in
By setting the resistance value of the falling hysteresis resistance element Q44 sufficiently large compared to the N resistance value, when the input voltage of the first-stage inverter circuit falls, the ground potential is established via the activated falling hysteresis circuit (Q44, Q46). When the first n-channel MOSFET Q43 is connected,
Threshold level nV of channel MOSFET Q43
It is possible to realize a circuit suitable for integration in which the threshold level VtL of the first-stage inverter circuit when the input voltage falls based only on th can be set without enlarging the circuit scale or increasing power consumption. .

The invention according to claim 6 is the invention according to claims 1 to 3
In the hysteresis inverter circuit according to any one of the above, in the first-stage inverter circuit, the rising hysteresis circuit (Q41, Q45) is connected in parallel between a source of the first p-channel MOSFET Q42 and a power supply potential,
The falling hysteresis circuit (Q4) is connected between the source of the first n-channel MOSFET Q43 and the ground potential and between the source of the first n-channel MOSFET Q43 and the ground potential.
4, Q46) are connected in parallel to form a hysteresis inverter circuit 30 (Q26, Q31).

According to the invention described in claim 6, according to claim 1,
In addition to the effects described in any one of (3) to (3), the circuit size is increased and the power consumption is increased by setting the resistance value of the rising hysteresis resistance element Q41 sufficiently larger than the ON resistance value of the first p-channel MOSFET Q42. The rising hysteresis circuit (Q41, Q45) suitable for integration which can set the threshold level VtH at the time of rising without causing the effect can be realized. For the same purpose, the threshold value VtL at the time of falling without increasing the circuit scale or power consumption is set by setting the resistance value of the falling hysteresis resistance element Q44 sufficiently large as compared with the ON resistance value of the first n-channel MOSFET Q43. Hysteresis circuit suitable for integration (Q44,
Q46) can be realized.

According to a seventh aspect of the present invention, in the hysteresis inverter circuit according to the sixth aspect, a common input of the second-stage inverter circuit is connected to a common output of the first-stage inverter circuit, and a common output of the second-stage inverter circuit is The gate of the p-channel MOSFET Q45 of the rising hysteresis circuit (Q41, Q45) and the n-channel MOSFET Q46 of the falling hysteresis circuit (Q44, Q46)
In a circuit configuration in which a logical value opposite to the logical value output from the first-stage inverter circuit is output from the second-stage inverter circuit, a logic value corresponding to the rise of the voltage of the logical value input to the first-stage inverter circuit is connected. Activated hysteresis circuit (Q41, Q41)
The first p-channel MOSFET Q42 is connected to the power supply potential via the p-channel MOSFET Q45 of (45), and the falling hysteresis circuit (Q44, Q4) responds to the rise of the logic value voltage input to the first-stage inverter circuit.
The hysteresis inverter circuit 30 (Q2) configured so that the first n-channel MOSFET Q43 is connected to the ground potential via the falling hysteresis resistance element Q44 when the n-channel MOSFET Q46 of (6) is inactivated.
6, Q31).

According to the invention of claim 7, according to claim 6,
In addition to the effects described in (1), by providing a post-stage inverter circuit, which is not accompanied by an increase in circuit scale and power consumption, in the output stage of the hysteresis inverter circuit 30 (Q26), the signal input to the first-stage inverter circuit can be reduced. By matching the logical value with the logical value of the output signal of the hysteresis inverter circuit 30 (Q26), the logical value of the signal input to the first-stage inverter circuit can be held and output from the hysteresis inverter circuit 30 (Q26). This has the effect.

According to an eighth aspect of the present invention, in the hysteresis inverter circuit according to the second, third, fourth, sixth, or seventh aspect, the input in the rising hysteresis circuit (Q41, Q45). The threshold level at the time of voltage rise depends on the first p-channel MOSFET Q
This is a hysteresis inverter circuit configured to be set based on the difference between the threshold level pVth of 42 and the power supply potential.

According to the eighth aspect of the invention, in addition to the effects of the second, third, fourth, sixth or seventh aspect, the power supply potential is a constant potential. A hysteresis inverter circuit suitable for integration, in which the threshold level VtH of the first-stage inverter circuit when the input voltage rises can be set based on only the threshold level pVth of the first p-channel MOSFET Q42 without enlarging the circuit scale and power consumption. 30 (Q26) can be realized.

According to a ninth aspect of the present invention, in the hysteresis inverter circuit according to the second, third, fifth, sixth, or seventh aspect, an input to the falling hysteresis circuit (Q44, Q46) is provided. The threshold level at the time of voltage drop is determined by the first n-channel MOSFET Q
43 is a hysteresis inverter circuit configured to be set based on the sum of the threshold level nVth of 43 and the ground potential.

According to the ninth aspect of the present invention, in addition to the effects of the second, third, fifth, sixth or seventh aspects, the ground potential is a constant potential. A hysteresis inverter circuit suitable for integration in which the threshold level VtL of the first-stage inverter circuit when the input voltage falls can be set based on only the threshold level nVth of the first n-channel MOSFET Q43 without enlarging the circuit scale or power consumption. 30 (Q26) can be realized.

The tenth aspect of the present invention provides the secondary battery 12
Charging transistor Q2 provided between the load 14
Is controlled to supply the charging current to the secondary battery 12.
The overcurrent state of the secondary battery 12 during discharge control or the overcurrent state of the secondary battery 12 during discharge control in which the discharge transistor Q1 provided between the secondary battery 4 and the load transistor 4 is controlled to supply a load current to the load 14. In the charge / discharge protection circuit for detecting the overcharge state, the overdischarge state or the overcurrent state by detecting the overcharge state, the overcharge state, and the secondary battery potential is further higher than the overcharge detection voltage And a charge / discharge protection circuit 20 having a delay circuit 26 for executing a discharge control for activating the discharge transistor Q1 connected to the load 14 and supplying a load current to the load 14.

According to the tenth aspect of the present invention, even when the secondary battery potential VDD is equal to or higher than the overcharge detection voltage, the load current when the load 14 is connected is erroneously determined as an overcurrent, and the discharge transistor becomes inactive. It is possible to realize a discharge control function of supplying a load current to the load 14 while avoiding the occurrence of the load current. Similarly, a pulse charger 14 is used as the charger 14, and an overcurrent with respect to the load current when the load 14 is connected. Even when the secondary battery potential VDD is detected to be equal to or higher than the overcharge detection voltage at the time of detection of the load current, it is possible to prevent the discharge transistor from being inactivated due to the erroneous determination of the overcurrent state and the load current. The discharge control function of supplying the load 14 to the load 14 can be realized with a small circuit scale.

The eleventh aspect of the present invention provides the secondary battery 12
Charging transistor Q2 provided between the load 14
Is controlled to supply the charging current to the secondary battery 12.
The overcurrent state of the secondary battery 12 during discharge control or the overcurrent state of the secondary battery 12 during discharge control in which the discharge transistor Q1 provided between the secondary battery 4 and the load transistor 4 is controlled to supply a load current to the load 14. In the charge / discharge protection circuit for detecting the overcharge state, the overdischarge state or the overcurrent state by detecting the overcharge state, the overcharge state, and the secondary battery potential is further higher than the overcharge detection voltage In addition to activating the discharging transistor Q1 connected to the load 14, the load is connected via a parasitic diode existing in parallel between the drain and source of the charging transistor Q2 and the activated discharging transistor Q1. 14 is a charge / discharge protection circuit 20 having a configuration including a delay circuit 26 for executing a discharge control for supplying a load current to the power supply 14.

According to the eleventh aspect, even when the secondary battery potential VDD is equal to or higher than the overcharge detection voltage, the load current when the load 14 is connected is not erroneously determined as an overcurrent and the discharging transistor Q1 And a discharge control function of supplying a load current to the load 14 via the parasitic diode and the discharging transistor Q1 can be realized. Similarly, when the pulse charger 14 is used as the charger 14, Even if the secondary battery potential VDD when the overcurrent with respect to the load current is detected is maintained at the overcharge detection voltage or higher, the overcurrent state is erroneously determined and the discharge transistor is deactivated. Thus, the discharge control function of supplying the load current to the load 14 while avoiding the problem can be realized with a small circuit scale.

According to a twelfth aspect of the present invention, in the charge / discharge protection circuit 20 according to the tenth or eleventh aspect, the delay circuit 26 performs two-level operation in response to the over-discharge detection signal 27a.
A delay signal 26a for setting a delay time required for detecting the overdischarge state and executing the discharge control in the secondary battery 12 is generated, and the overcurrent is detected in the secondary battery 12 according to the overcurrent detection signal 25a. A delay signal 26a for detecting a state and setting a delay time required for performing a discharge control is generated, and furthermore, a secondary battery potential higher than an overcharge detection voltage when the overcharge detection signal 22a is detected. When VDD is detected, an instruction is given to cancel the discharge control according to the overdischarge state and to cancel the discharge control according to the overcurrent state, and the discharging transistor Q1 connected to the load 14
Signal for instructing discharge control to supply a load current to the load 14 via a parasitic diode existing in parallel between the drain and source of the charging transistor Q2 and the activated discharging transistor Q1. 26
The charge / discharge protection circuit 20 according to claim 10 or 11, wherein the charge / discharge protection circuit 20 has a circuit configuration for generating a.

According to the twelfth aspect, in addition to the effects of the tenth or eleventh aspects, the delay circuit 26
Is provided, when the overcharge detection signal 22a is detected and the secondary battery potential VDD equal to or higher than the overcharge detection voltage is further detected, the discharge control according to the overdischarge state is canceled and the overcurrent state is determined. This makes it possible to cancel the discharge control. As a result, in addition to the discharge control function for avoiding the over-discharge state and the over-current control function for avoiding the over-current state, the over-charge state is detected when the load 14 is connected. 2
When the next battery potential VDD is lower than the overcharge detection voltage, a discharge control function of supplying a load current to the load 14 via the discharging transistor Q1 can be realized.

According to a thirteenth aspect of the present invention, in the charge / discharge protection circuit 20 according to any one of the tenth to twelfth aspects, the delay circuit 26 outputs the overcharge detection signal 2
When the secondary battery potential VDD that is equal to or higher than the overcharge detection voltage is further detected in the state where 2a has been detected, the load is connected to the load 14 in preference to the discharge control instruction relating to the overdischarge detection signal 27a and the overcurrent detection signal 25a. A charge / discharge protection circuit 20 having a circuit configuration for executing a discharge control instruction for activating the discharged transistor Q1 to supply a load current to the load 14 by performing the above operation.

According to the thirteenth aspect of the present invention, in addition to the effect of any one of the tenth to twelfth aspects, the overdischarge detection signal 2
7a and the discharge transistor Q1 when detecting the overcharge detection signal 22a more than the discharge control according to the overcurrent detection signal 25a and further detecting the secondary battery potential VDD equal to or higher than the overcharge detection voltage. Priority can be given to the discharge control for activation, and as a result,
Even if the voltage is equal to or higher than the overcharge detection voltage, the load current when the load 14 is connected is not erroneously determined as an overcurrent and the discharging transistor Q
1 to activate the parasitic diode and discharge transistor Q1
And a discharge control function of supplying a load current to the load 14 via the pulse charger 1.
4, even when the secondary battery potential VDD is maintained at or above the overcharge detection voltage when an overcurrent with respect to the load current when the load 14 is connected is determined to be an overcurrent state, the discharge transistor is activated. There is an effect that a discharge control function of supplying a load current to the load 14 while avoiding inactivation can be realized with a small circuit scale.

According to a fourteenth aspect of the present invention, in the charge / discharge protection circuit 20 according to the thirteenth aspect, the delay circuit 26 generates a delay signal 26a related to the overdischarge detection signal 27a or the overcharge detection signal 22a. Gate circuits Q22, Q23, Q2 for generating such a delay signal 26a
5, Q27 and the over-discharge detection signal 27a and the over-charge detection signal 22a in response to the over-charge detection signal 22a when the over-charge detection voltage 22 is detected and the overcharge detection signal 22a is detected. A delay signal 26a related to the overdischarge detection signal 27a or a delay signal 2 related to the overcharge detection signal 22a by interrupting the overcurrent detection signal 25a.
The control for inhibiting the generation of the gate circuit 6a is performed by the gate circuits Q22 and Q2.
3, Q25, and Q27, and controls the generation of the delay signal 26a for activating the discharge transistor Q1 connected to the load 14 by the gate circuits Q22, Q23, Q25, and Q27. Is a charge / discharge protection circuit 20 having a configuration having a circuit configuration to execute the protection.

According to the invention of claim 14, in addition to the effect of claim 13, the gate circuits Q22, Q23, Q
By providing the transistors 25 and Q27, discharge control or a delay signal 26a necessary for discharge control can be generated and supplied to the discharge transistor Q1. Also delay circuit 2
6, the overdischarge detection signal 27a and the overcurrent detection signal 25a are cut off when the secondary battery potential VDD that is equal to or higher than the overcharge detection voltage is detected while the overcharge detection signal 22a is received. Executing a control for inhibiting the generation of the delay signal 26a required for the discharge control related to the overdischarge detection signal 27a and the discharge control related to the overcurrent detection signal 25a;
In addition, when the overcharge detection signal 22a is detected and the secondary battery potential VDD that is higher than the overcharge detection voltage is detected, the generation of the delay signal 26a required for the discharge control for activating the discharge transistor Q1 is permitted. As a result, even if the voltage is equal to or higher than the overcharge detection voltage, the load 1
The discharge control function of activating the discharge transistor Q1 and supplying the load current to the load 14 via the parasitic diode and the discharge transistor Q1 without erroneously determining the load current at the time of connection 4 as an overcurrent can be realized. In addition, even if the secondary battery potential VDD is maintained at the overcharge detection voltage or more when the overcurrent with respect to the load current when the load 14 is connected is detected using the pulse charger 14 as the charger 14, There is an effect that a discharge control function of supplying a load current to the load 14 can be realized with a small circuit scale by avoiding inactivation of the discharge transistor due to erroneous determination as a state.

According to a fifteenth aspect of the present invention, in the charge / discharge protection circuit 20 according to the fourteenth aspect, when the overcharge detection signal 22a is received, the charge / discharge protection circuit 20 further exceeds the overcharge detection voltage.
In response to the input of the overcharge detection signal 22a to the gate when the next battery potential VDD is detected, the gate circuits Q22, Q22 of the overdischarge detection signal 27a and the overcurrent detection signal 25a are input.
23, Q25 and Q27 are shut off and the delay signal 2
6a is output to the gate circuit Q22,
Q23, Q25, and Q27, and a logic signal instructing generation of the delay signal 26a for activating the discharging transistor Q1 is output to the gate circuits Q22, Q23, and Q2.
5, a charge / discharge protection circuit 20 having a shutoff MOSFET Q36 for outputting to Q27.

According to the fifteenth aspect of the present invention, in addition to the effect of the fourteenth aspect, by providing the shutoff MOSFET Q36, the overcharge detection voltage is further increased in a state where the overcharge detection signal 22a is received. In response to the input of the overcharge detection signal 22a to the gate when the above secondary battery potential VDD is detected, the shutoff MOSFET Q36 is activated to activate the overdischarge detection signal 2a.
7a and the overcurrent detection signal 25a are cut off to execute a discharge control according to the overdischarge detection signal 27a and a control to inhibit generation of a delay signal 26a required for the discharge control according to the overcurrent detection signal 25a, and an overcharge detection signal 22a, the secondary battery potential VDD which is higher than the overcharge detection voltage.
Can be executed to generate a delay signal 26a that permits generation of a delay signal 26a required for discharge control for activating the discharge transistor Q1 upon detection of the signal. As a result, even if the load current is equal to or higher than the overcharge detection voltage, the load current when the load 14 is connected is not erroneously determined as an overcurrent, and the discharge transistor Q1 is activated to load the load current via the parasitic diode and the discharge transistor Q1. A discharge control function for supplying to the load 14 can be realized.
Even if the secondary battery potential VDD is maintained at or above the overcharge detection voltage when the overcurrent with respect to the load current when the load 14 is connected is detected using the pulse charger 14, the overcurrent state is erroneously determined. As a result, it is possible to prevent a discharge transistor from being inactivated and to realize a discharge control function of supplying a load current to the load 14 with a small circuit scale.

According to a sixteenth aspect of the present invention, in the charge / discharge protection circuit 20 using the hysteresis inverter circuit Q26 according to any one of the first to ninth aspects, overcharging of the secondary battery 12 during charging control is performed. State, an overdischarge state of the secondary battery 12 at the time of discharge control for supplying a load current, or an overcurrent state of the secondary battery 12 at the time of discharge control to detect an overcharge state, an overdischarge state, or In a charge / discharge protection circuit that protects from an overcurrent state,
An overdischarge detection circuit 27 that monitors a discharge state of the secondary battery 12 and generates an overdischarge detection signal 27a when an overdischarge state is detected, and a charger 14 ground potential V- The overcurrent detection circuit 25 monitors the potential V- and generates an overcurrent detection signal 25a when an overcurrent state is detected. The overcurrent detection circuit 25 is connected to the secondary battery potential, and connects the battery ground potential Vss to the charger 14 ground. The level shift circuit 23 that shifts to the potential V- to generate the charge control signal 23a, and the delay circuit 26 includes the hysteresis inverter circuit Q26, and operates in the secondary battery 12 according to the overdischarge detection signal 27a. A delay signal 26a for setting a delay time required for detecting a discharge state is generated via the hysteresis inverter circuit Q26. 2 in response to the overcurrent detection signal 25a
Delay signal 26 for setting a delay time required for detecting an overcurrent state in next battery 12
a charge / discharge protection circuit 20 having a configuration including a delay circuit 26 for generating a through the hysteresis inverter circuit Q26.

According to the sixteenth aspect of the present invention, in addition to the effect of any one of the first to ninth aspects, by providing the overdischarge detection circuit 27, the discharge state of the secondary battery 12 is provided. Can be generated to generate an overdischarge detection signal 27a when an overdischarge state is detected. Further, by providing the delay circuit 26 having the above-mentioned hysteresis inverter circuit Q26, the overdischarge detection signal 27a can be inputted to the above-mentioned hysteresis inverter circuit Q26,
As a result, the rising input voltage threshold level VtH
And a delay signal 26a having hysteresis characteristics that can be specified by the input voltage threshold level VtL at the time of falling. By providing such a hysteresis characteristic to the delay signal 26a, an oscillation preventing function at the time of overcurrent detection can be realized, and the overcurrent detection of the discharge transistor Q1 for controlling the discharge current using the delay signal 26a can be realized. The oscillation prevention function at the time can be realized. Further, by providing the hysteresis inverter circuit Q26, such a circuit configuration is simpler than that of the comparator with a latch function, and a compact circuit size, a small chip area, and low power consumption with reduced consumption of the secondary battery 12 are provided. The overcurrent detection circuit 25 having the oscillation preventing function can be realized. Since the level shift circuit 23 is connected to the charging potential of the charger 14,
When the battery 4 is connected to the charging potential, the battery 4 is supplied with power from the charger 14 and becomes operable, so that the charging control signal 23a can be generated. In other words, even if the ability to supply enough power to operate the charge / discharge protection circuit 20 to the secondary battery 12 is lost, the level shift circuit 23 can operate if the charger 14 is connected to the charging potential. A state in which the charge control signal 23a can be generated, and even when the battery voltage of the secondary battery 12 falls below the operable voltage, the function of executing reliable charge control by connecting the charger 14 Can be realized. as a result,
By controlling the charging transistor Q2 using the charging control signal 23a, the charging of the secondary battery 12 can be controlled,
This has the effect of enabling the secondary battery 12 to restore the ability to supply power sufficient to operate the charge / discharge protection circuit 20.

According to a seventeenth aspect of the present invention, in the charge / discharge protection circuit 20 according to the sixteenth aspect, the delay circuit 26 generates a delay signal 26a related to the overdischarge detection signal 27a or the overcharge detection signal 22a. In response to the hysteresis inverter circuit Q26 for generating the delay signal 26a and the overcharge detection signal 22a when the secondary battery potential VDD that is higher than the overcharge detection voltage is detected while the overcharge detection signal 22a is received, The over-discharge detection signal 27a and the over-current detection signal 25a are cut off and a delay signal 26a according to the over-discharge detection signal 27a or a delay signal 26a according to the over-charge detection signal 22a
Control for inhibiting the generation of the delay signal 26a for the activation of the discharge transistor Q1 connected to the load 14 and the control for inhibiting the generation of the delay signal 26a for the activation of the discharge transistor Q1 connected to the load 14. This is a charge / discharge protection circuit 20 having a configuration having a circuit configuration executed for the circuit Q26.

According to the seventeenth aspect of the invention, in addition to the effect of the sixteenth aspect, by providing the shutoff MOSFET Q36, the overcharge detection voltage can be further increased while the overcharge detection signal 22a is received. In response to the input of the overcharge detection signal 22a to the gate when the above secondary battery potential VDD is detected, the shutoff MOSFET Q36 is activated to activate the overdischarge detection signal 2a.
By interrupting the input of the overcurrent detection signal 25a and the overcurrent detection signal 25a to the hysteresis inverter circuit Q26, the discharge control of the overdischarge detection signal 27a and the control of prohibiting the generation of the delay signal 26a required for the discharge control of the overcurrent detection signal 25a are controlled. The delay signal 26a required for the discharge control for activating the discharge transistor Q1 when the rechargeable battery potential VDD equal to or higher than the overcharge detection voltage is detected while the overcharge detection signal 22a is being detected. Control for generating a delay signal 26a that is preferentially permitted to the hysteresis inverter circuit Q26 can be executed. As a result, even if the load current is equal to or higher than the overcharge detection voltage, the load current when the load 14 is connected is not erroneously determined as an overcurrent, and the discharge transistor Q1 is activated to load the load current via the parasitic diode and the discharge transistor Q1. A discharge control function for supplying to the load 14 can be realized. Similarly, the pulse battery charger 14 is used as the charger 14, and when the overcurrent with respect to the load current when the load 14 is connected is detected, the secondary battery potential VDD is overcharged. A discharge control function of supplying a load current to the load 14 by avoiding the inactivation of the discharge transistor due to an erroneous determination of an overcurrent state even when the voltage is maintained at a voltage or more is realized with a small circuit scale. It has the effect of being able to do so.

According to an eighteenth aspect of the present invention, in the charge / discharge protection circuit 20 according to the sixteenth aspect, the delay circuit 26 has the hysteresis inverter circuit Q26,
The delay signal 26a for detecting an overdischarge state in the secondary battery 12 and executing discharge control in accordance with the overdischarge detection signal 27a is generated via the hysteresis inverter circuit Q26, and the overcurrent detection signal A state in which the delay signal 26a for detecting an overcurrent state in the secondary battery 12 and executing the discharge control in accordance with the overcharge detection signal 22a is generated through the hysteresis inverter circuit Q26 in response to the overcharge detection signal 22a. When the secondary battery potential VDD that is equal to or higher than the overcharge detection voltage is detected, the load 1
Activate the discharge transistor Q1 connected to the load transistor 4 and load the load 14 via the parasitic diode existing in parallel between the drain and source of the charge transistor Q2 and the activated discharge transistor Q1. The charge / discharge protection circuit 20 has a circuit configuration for executing discharge control for supplying current.

According to the eighteenth aspect, the same effect as that of the sixteenth aspect can be obtained.

The invention according to claim 19 is the charging / discharging protection circuit 20 according to claim 17 or 18, wherein the delay circuit 26 has gate circuits Q22, Q23, Q25, Q27 for generating the delay signal 26a. The gate circuits Q22, Q23, Q25, Q27 are connected to the overcharge detection signal 22a.
When the secondary battery potential VDD that is equal to or higher than the overcharge detection voltage is detected in a state where the overcharge detection voltage is received, the control to cut off the overdischarge detection signal 27a and the overcurrent detection signal 25a is performed on the hysteresis inverter circuit Q26. Charge / discharge protection having a circuit configuration for executing control for generating the delay signal 26a for instructing activation of the discharge transistor Q1 connected to the load 14 to the hysteresis inverter circuit Q26. Circuit 20.

According to the nineteenth aspect of the present invention, in addition to the effects of the seventeenth or eighteenth aspects, the blocking MOSFE
By providing the TQ36, the secondary battery potential V which is higher than the overcharge detection voltage while the overcharge detection signal 22a is received is provided.
The shutoff MOSFET Q36 is activated in response to the input of the overcharge detection signal 22a to the gate when DD is detected, and the overdischarge detection signal 27a and the input of the overcurrent detection signal 25a to the hysteresis inverter circuit Q26 are cut off to overdischarge. The control for prohibiting the generation of the delay signal 26a required for the discharge control related to the detection signal 27a and the discharge control related to the overcurrent detection signal 25a is executed, and further, when the overcharge detection signal 22a is detected, the overcharge detection voltage or more is detected. A control is performed to generate a delay signal 26a that gives priority to the hysteresis inverter circuit Q26 to generate the delay signal 26a required for discharge control for activation of the discharge transistor Q1 when the secondary battery potential VDD is detected. become able to. As a result, even if the voltage exceeds the overcharge detection voltage, the load 14
A discharge control function of activating the discharging transistor Q1 and supplying the load current to the load 14 via the parasitic diode and the discharging transistor Q1 without erroneously determining the load current at the time of connection can be realized. Even when the secondary battery potential VDD when the overcurrent with respect to the load current when the load 14 is connected is detected using the pulse charger 14 as the charger 14 and is maintained at or above the overcharge detection voltage, the overcurrent state occurs. The discharge control function of supplying the load current to the load 14 while avoiding the inactivation of the discharge transistor due to the erroneous determination of the hysteresis inverter circuit Q26 and the shutoff MO
Use of the SFET Q36 has an effect that it can be realized with a small circuit scale.

According to a twentieth aspect of the present invention, in the charge / discharge protection circuit 20 according to the nineteenth aspect, when the overcharge detection signal 22a is received, the charge / discharge protection circuit 20 further exceeds the overcharge detection voltage.
In response to the input of the overcharge detection signal 22a to the gate when the next battery potential VDD is detected, the gate circuits Q22, Q22 of the overdischarge detection signal 27a and the overcurrent detection signal 25a are input.
23, Q25 and Q27 are shut off and the delay signal 2
6a is output to the hysteresis inverter circuit Q26, and a logic signal instructing generation of the delay signal 26a for activating the discharging transistor Q1 is output to the hysteresis inverter circuit Q26.
This is a charge / discharge protection circuit 20 having a shut-off MOSFET Q36 that outputs the signal to an output terminal 26.

According to the twentieth aspect of the present invention, in addition to the effect of the nineteenth aspect, by providing the shutoff MOSFET Q36, the overcharge detection voltage is further increased in a state where the overcharge detection signal 22a is received. In response to the input of the overcharge detection signal 22a to the gate when the above secondary battery potential VDD is detected, the shutoff MOSFET Q36 is activated to activate the overdischarge detection signal 2a.
A logic control for interrupting the input of the overcurrent detection signal 25a and the overcurrent detection signal 25a to the hysteresis inverter circuit Q26 and prohibiting the generation of the delay signal 26a required for the discharge control of the overdischarge detection signal 27a and the discharge control of the overcurrent detection signal 25a. And the generation of the delay signal 26a required for the discharge control for activating the discharge transistor Q1 when the secondary battery potential VDD equal to or higher than the overcharge detection voltage is detected while the overcharge detection signal 22a is detected. Can be executed to generate a delay signal 26a that gives priority to the hysteresis inverter circuit Q26. As a result, even if the voltage exceeds the overcharge detection voltage, the load 14
A discharge control function of activating the discharging transistor Q1 and supplying the load current to the load 14 via the parasitic diode and the discharging transistor Q1 without erroneously determining the load current at the time of connection can be realized. Even when the secondary battery potential VDD when the overcurrent with respect to the load current when the load 14 is connected is detected using the pulse charger 14 as the charger 14 and is maintained at or above the overcharge detection voltage, the overcurrent state occurs. A hysteresis inverter circuit Q capable of logically controlling a discharge control function of supplying a load current to the load 14 while avoiding inactivation of the discharge transistor due to erroneous determination of
By using the MOSFET 26 and the blocking MOSFET Q36, it is possible to realize a small circuit scale and a circuit form suitable for integration.

According to a twenty-first aspect of the present invention, in the charge / discharge protection circuit 20 according to the fifteenth or twentieth aspect, the delay circuit 26 is related to a timing at which discharge control is performed according to the over-discharge detection signal 27a. Delay time,
A timing capacitor C2 connected to an input of the hysteresis inverter circuit Q26 for setting a delay time required to execute a discharge control according to the overcurrent detection signal 25a;
The SFET Q36 is connected to the hysteresis inverter circuit Q26.
The gate of the overcharge detection signal 22a, which is connected in parallel to the timing capacitor C2 with respect to the input of the overcharge detection signal 22a and detects the rechargeable battery potential VDD that is higher than the overcharge detection voltage while receiving the overcharge detection signal 22a. The charge / discharge protection circuit 20 has a circuit configuration that short-circuits the electric charge accumulated in the timing capacitor C2 by the overdischarge detection signal 27a or the overcurrent detection signal 25a in response to the input to the circuit.

According to the twenty-first aspect of the present invention, in addition to the effect of the fifteenth or twentieth aspect, the blocking MOSF
By providing the ETQ36, the shutoff MOSFET Q36 in response to the input of the overcharge detection signal 22a to the gate when the secondary battery potential VDD equal to or higher than the overcharge detection voltage is detected while the overcharge detection signal 22a is received. Is activated to interrupt the charge accumulation of the over-discharge detection signal 27a and the over-current detection signal 25a in the timing capacitor C2, and discharge control for the over-discharge detection signal 27a and delay signal 26a required for discharge control for the over-current detection signal 25a Discharge control for activating the discharge transistor Q1 when the secondary battery potential VDD that is equal to or higher than the overcharge detection voltage is detected while the overcharge detection signal 22a is detected and the overcharge detection signal 22a is detected. Signal 26a that permits the generation of the delay signal 26a required for the hysteresis inverter circuit Q26 preferentially. It becomes possible to perform the logic control of growth. As a result, even if the load current is equal to or higher than the overcharge detection voltage, the load current when the load 14 is connected is not erroneously determined as an overcurrent, and the discharge transistor Q1 is activated to load the load current via the parasitic diode and the discharge transistor Q1. Load 1
4 can be realized. Similarly, the secondary battery potential V when an overcurrent with respect to the load current when the load 14 is connected is detected using the pulse charger 14 as the charger 14
Even when DD is maintained at or above the overcharge detection voltage, load current is prevented by avoiding falsely determining an overcurrent state based on the potential of the timing capacitor C2 and inactivating the discharge transistor. And a hysteresis inverter circuit Q capable of logically controlling the discharge control function supplied to the inverter 14.
By using the MOSFET 26 and the blocking MOSFET Q36, it is possible to realize a small circuit scale and a circuit form suitable for integration.

According to a twenty-second aspect of the present invention, in the charge / discharge protection circuit 20 according to the twenty-first aspect, the hysteresis inverter circuit Q26 adjusts the potential of the timing capacitor C2 to the input voltage in the rising hysteresis circuit (Q41, Q45). The delay signal 26a for inactivating the discharging transistor Q1 when the threshold level is equal to or higher than the rising threshold level is generated, and the timing capacitor C
2 has a circuit configuration for generating the delay signal 26a for activating the discharge transistor Q1 when the potential of the second hysteresis circuit (Q41, Q45) is lower than the threshold level at the time of input voltage rise. It is a discharge protection circuit 20.

According to the twenty-second aspect of the present invention, in addition to the effect of the twenty-first aspect, in addition to the effect of the charge accumulation in the timing capacitor C2 using the overdischarge detection signal 27a and the overcurrent detection signal 25a. A delay for inactivating the discharging transistor Q1 when the capacitor potential is compared with the threshold level of the rising hysteresis circuit (Q41, Q45) when the input voltage rises and the capacitor potential exceeds the threshold level when the input voltage rises. The signal 26a can be generated, and the delay signal 26a for activating the discharging transistor Q1 can be generated when the input hysteresis circuit (Q41, Q45) is lower than the threshold level when the input voltage rises.
As a result, the rising input voltage threshold level VtH
And a delay signal 26a having hysteresis characteristics that can be specified by the input voltage threshold level VtL at the time of falling. By providing such a hysteresis characteristic to the delay signal 26a, an oscillation preventing function at the time of overcurrent detection can be realized, and the overcurrent detection of the discharge transistor Q1 for controlling the discharge current using the delay signal 26a can be realized. The oscillation prevention function at the time can be realized. Further, by providing the hysteresis inverter circuit Q26, such a circuit configuration is simpler than that of the comparator with a latch function, and a compact circuit size, a small chip area, and low power consumption with reduced consumption of the secondary battery 12 are provided. The overcurrent detection circuit 25 having the oscillation preventing function can be realized.

According to a twenty-third aspect of the present invention, in the battery pack 10 using the charge / discharge protection circuit 20 according to any one of the tenth to twenty-second aspects, a secondary battery is provided in addition to the charge / discharge protection circuit 20. The battery 12 as the battery 12 is connected in series between the load 14 and the battery cell 12, and the conduction state of the discharge current supplied from the battery cell 12 to the load 14 during discharge control is determined by the logic of the delay signal 26a. A discharging transistor Q1 controlled according to the value, and a charging transistor connected in series between the charger 14 and the battery cell 12 to supply the charging current supplied from the charger 14 to the battery cell 12 at the time of charging control. A charging transistor Q2 controlled according to a logical value of a control signal 23a, and a battery ground potential Vss, 12 is a battery pack 10 having a delay capacitor C1 for generating a charge / discharge signal 12a for setting a delay time required for detecting an overcharge state and transmitting the signal to the overcharge detection circuit 22.

According to the twenty-third aspect of the present invention, in addition to the effect of any one of the tenth to twenty-second aspects, the provision of the above-described charge / discharge protection circuit 20 enables the Even if the battery voltage falls below the operable voltage, it is possible to realize the function of preventing oscillation when overcurrent is detected, and to realize the function of executing reliable discharge control using the discharging transistor Q1, and ensuring the reliable charging. There is an effect that a function of executing control using the charging transistor Q2 can be realized. Further, by providing such a charge / discharge protection circuit 20, a circuit configuration which is simpler than that of a comparator with a latch function, and has a compact circuit scale,
The battery pack 10 having such a charge / discharge control function and an oscillation prevention function can be realized with a small chip area and low power consumption with reduced consumption of the secondary battery 12.

According to a twenty-fourth aspect of the present invention, in the battery pack 10 according to the twenty-third aspect, the discharging transistor Q1 is a logical product of a logical value of the delay signal 26a and a logical value of the short-circuit detection signal 24a. The battery pack 10 is configured to control the conduction state of the discharge current supplied from the battery cell 12 to the load 14 in accordance with the logical value of the discharge signal 26b.

According to the twenty-fourth aspect of the present invention, in addition to the effect of the twenty-third aspect, the discharge signal 26b, which is the logical product of the logical value of the delay signal 26a and the logical value of the short-circuit detection signal 24a, In accordance with the logical value of the operation result, the current supply state of the discharge current supplied from the battery cell 12 to the load 14 can be controlled using the discharging transistor Q1 while monitoring the overdischarge state and the short circuit state. It has the effect of becoming

According to a twenty-fifth aspect of the present invention, in the battery pack of the twenty-fourth aspect, a logic value for activating the charging transistor Q2 when activated in accordance with the ground potential V- of the charger 14. The battery pack 10 has a configuration including a level shift circuit 23 that generates the charge control signal 23a having the following.

According to the twenty-fifth aspect of the present invention, in addition to the effect of the twenty-fourth aspect, the charge / discharge protection circuit 20
By providing such a level shift circuit 23, even when the battery voltage of the secondary battery 12 falls below the operable voltage, the connection of the charger 14 prevents the oscillation at the time of the above-described overcurrent detection. While realizing the function,
There is an effect that the charge control signal 23a for realizing the function of executing the reliable charge control using the charging transistor Q2 can be generated. Furthermore, such a level shift circuit 23 has a simpler circuit configuration than a comparator with a latch function, and has a compact circuit size, a small chip area, and low power consumption with reduced consumption of the secondary battery 12. This contributes to realizing the battery pack 10 having a charge / discharge control function and an oscillation prevention function.

[0079]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of the present invention will be described below with reference to the drawings.

First, an embodiment of the charge / discharge protection circuit of the present invention will be described with reference to the drawings. FIG. 1 is a functional block diagram for explaining a configuration of a charge / discharge protection circuit 20 for a secondary battery 12 and a battery pack 10 using the same according to the present invention.

The charge / discharge protection circuit 20 shown in FIG. 1 controls a charging transistor Q2 provided between the secondary battery 12 and the load 14 to control the charging current (in FIG. 1, the positive electrode of the battery cell 12). Overcharge state of the secondary battery 12 at the time of charge control to supply the secondary battery 12 with a current flowing in the direction of flowing to the secondary battery 12 by controlling a discharging transistor Q1 provided between the secondary battery 12 and the load 14. An overdischarge state of the secondary battery 12 at the time of discharge control for supplying a current to the load 14 or an overcurrent state of the secondary battery 12 at the time of discharge control is detected to overcharge the secondary battery 12, It has a function of protecting from an overcurrent state, and furthermore, is in an overcharged state, and the secondary battery potential VDD is further overcharged detection potential (for example, 4.25
VDC: DC means direct current) or more, load 1
4 is characterized in that it has a function of activating the discharge transistor Q1 connected to 4 and performing a discharge control for supplying a load current to the load 14.

Such a charge / discharge protection circuit 20 includes a hysteresis inverter circuit 30 which plays a central role for realizing an oscillation prevention function upon detection of an overcurrent, and a charge control function and a discharge control function for realizing the above-described charge control function and discharge control function. The overcharge detection circuit 22, the level shift circuit 23, the short-circuit detection circuit 24, the overcurrent detection circuit 25, which plays a central role, and the secondary battery potential VDD in the overcharged state is further changed to the overcharge detection potential (4.25VD
C) If not less than the above, the delay circuit 26 and the over-discharge detection circuit which play a central role in realizing the discharge control for activating the discharge transistor Q1 connected to the load 14 and supplying the load current to the load 14 27, and it is made into an IC chip and inside the device (specifically,
It is usually incorporated in a battery pack 10 described later). When incorporated in the device in this way, it is normal to receive power supply from a battery in the device. In the following description, the charge / discharge protection circuit 20 will be referred to as a charge / discharge protection IC 20.

Here, as the secondary battery 12, a lithium ion battery 12 is typical, and in the following description, the description will be made using the lithium ion battery 12.

The charge / discharge protection IC 20 is used as an IC chip (integrated) and built in a battery pack 10 described later. In general, the case is used by being attached to various portable devices such as a wireless device. In the following description, the load 14 will be represented by the mobile phone 14.

FIG. 2 shows a hysteresis inverter circuit 30.
It is a circuit diagram for explaining the circuit configuration of (Q26, Q31).

A hysteresis inverter circuit 30 having a hysteresis characteristic at the threshold level of the input voltage
(Specifically, Q26 and Q31 to be described later) include a first-stage inverter circuit, a second-stage inverter circuit, a rising hysteresis circuit (Q41, Q45), and a falling hysteresis circuit (Q44, Q46), as shown in FIG. ing.

Such a hysteresis inverter circuit 3
0 (specifically, Q26 and Q31 described later) is a charge / discharge protection circuit 20 described later or a battery pack 1 incorporating the same.
It is desirable that the overcurrent detection circuit 25 is provided in the overcurrent detection circuit 25 so that the output signal of the detection does not oscillate at 0 when the battery voltage fluctuates when the overcurrent is detected.

The first-stage inverter circuit (Q42, Q43)
As shown in FIG. 2, the secondary battery potential VDD (power supply potential VDD)
Connected to the first p-channel MOSFET Q42 and the first n-channel connected to the battery ground potential Vss (ground potential Vss).
The channel MOSFET Q43 has a circuit configuration in which the gate is commonly connected and the drain is commonly output.

Also, the first-stage inverter circuit (Q42, Q43)
Is, as shown in FIG. 2, a first p-channel MOSFET Q
A rising hysteresis circuit (Q41, Q45) is connected in parallel between the source of the first n-channel MOSFET Q43 and the battery ground potential between the source of the first n-channel MOSFET Q43 and the battery ground potential Vss. The falling hysteresis circuit (Q
44, Q46) are connected in parallel.

According to such a circuit configuration, the resistance value of the rising hysteresis resistance element Q41 is set sufficiently large as compared with the ON resistance value of the first p-channel MOSFET Q42, thereby enlarging the circuit scale and power consumption. Thus, there is an effect that a rising hysteresis circuit (Q41, Q45) suitable for integration that can set the threshold level VtH at the time of rising can be realized. With a similar purport,
By setting the resistance value of the falling hysteresis resistance element Q44 sufficiently larger than the ON resistance value of the first n-channel MOSFET Q43, the threshold level VtL at the time of falling can be set without enlarging the circuit scale and power consumption. Hysteresis circuit (Q44, Q4
6) is achieved.

In such a circuit, as shown in FIG. 2, rising hysteresis circuits (Q41, Q45) activated in response to the rise of the voltage of the logical value input to the first-stage inverter circuits (Q42, Q43). P-channel MOSF
The first p-channel M is connected to the secondary battery potential VDD via the ETQ45.
OSFET Q42 is connected, and the first-stage inverter circuit (Q
42, Q43), the n-channel MOSFET Q46 of the falling hysteresis circuit (Q44, Q46) is inactivated in response to the rise of the voltage of the logical value inputted to the first n-channel MOSFET via the falling hysteresis resistance element Q44.
Q43 has a circuit configuration connected to the battery ground potential Vss.

According to this, the latter-stage inverter circuit (Q42, Q43), which does not involve an increase in circuit scale or power consumption, is provided in the output stage of the hysteresis inverter circuit 30 (Q26, Q31), so that the first-stage inverter circuit (Q42, Q43)
The logical value of the logical signal input to the first-stage inverter circuit (Q42, Q43) is matched by matching the logical value of the logical signal input to the first stage with the logical value of the output logical signal of the hysteresis inverter circuit 30 (Q26, Q31). There is an effect that the data can be held and output from the hysteresis inverter circuit 30 (Q26, Q31).

The subsequent-stage inverter circuit (Q47, Q48)
As shown in FIG. 2, the second battery connected to the secondary battery potential VDD is
p-channel MOSFET Q47 and battery ground potential Vss
And a second n-channel MOSFET Q48 connected in series with the gate as a common input and the drain as a common output.

Also, a rising hysteresis circuit (Q41, Q45)
Is connected between the secondary battery potential VDD and the first p-channel MOSFET Q42 as shown in FIG. 2, and has a circuit configuration for setting an input voltage threshold level VtH when the input voltage of the first-stage inverter circuit rises. .

Here, the rising hysteresis circuit (Q41, Q41)
45) Threshold level V when input voltage rises
Preferably, tH is set based on the difference between the threshold level pVth of the first p-channel MOSFET Q42 and the secondary battery potential VDD.

According to this, since the secondary battery potential VDD is a constant potential, the threshold level VtH of the first-stage inverter circuit when the input voltage rises can be increased based on only the threshold level pVth of the first p-channel MOSFET Q42. There is an effect that the hysteresis inverter circuit 30 (Q26, Q31) suitable for integration that can be set without increasing power consumption can be realized.

The rising hysteresis circuit (Q41, Q45)
The circuit configuration is such that a p-channel MOSFET Q45 and a rising hysteresis resistance element Q41 are connected in parallel. In the present embodiment, in such a circuit configuration, the resistance value of the rising hysteresis resistance element Q41 is set to be sufficiently larger than the ON resistance value of the p-channel MOSFET Q45, which does not involve an increase in circuit scale and power consumption. Is desirable.

According to this, the first-stage inverter circuit (Q4
(2, Q43) when the input voltage rises, the secondary battery potential V rises via the activated rising hysteresis circuit (Q41, Q45).
When the first p-channel MOSFET Q42 is connected to DD, the threshold level VtH of the first-stage inverter circuit when the input voltage rises is based only on the threshold level pVth of the first p-channel MOSFET Q42.
This makes it possible to realize a circuit suitable for integration that can be set without increasing the circuit scale and power consumption.

As shown in FIG. 2, the common input of the second-stage inverter circuit (Q47, Q48) is connected to the common output of the first-stage inverter circuit (Q42, Q43), and the common output of the second-stage inverter circuit (Q47, Q48). Is connected to the gate of the p-channel MOSFET Q45 of the rising hysteresis circuit (Q41, Q45) and the gate of the n-channel MOSFET Q46 of the falling hysteresis circuit (Q44, Q46), and inverts the logical value output from the first-stage inverter circuit (Q42, Q43). The circuit configuration is such that the logical value is output from the subsequent inverter circuit (Q47, Q48).

The falling hysteresis circuit (Q44, Q46)
Battery ground potential Vss and first n-channel MOSFET
Q43, and has a circuit configuration for setting an input voltage threshold level VtL when the input voltage of the first-stage inverter circuit falls.

Here, the falling hysteresis circuit (Q44, Q
Threshold level V when input voltage falls in 46)
It is desirable that tL is set based on the sum of the threshold level nVth of the first n-channel MOSFET Q43 and the battery ground potential Vss.

Accordingly, since the battery ground potential Vss is a constant potential, the threshold level VtL of the first-stage inverter circuit at the time of the fall of the input voltage is increased or consumed based on only the threshold level nVth of the first n-channel MOSFET Q43. There is an effect that the hysteresis inverter circuit 30 (Q26, Q31) suitable for integration which can be set without increasing power can be realized.

A falling hysteresis circuit (Q44, Q46)
Has a circuit configuration in which an n-channel MOSFET Q46 and a falling hysteresis resistance element Q44 are connected in parallel.

In the present embodiment, in such a circuit configuration, the resistance value of the falling hysteresis resistance element Q44 is sufficiently larger than the ON resistance value of the n-channel MOSFET Q46, which is not accompanied by an increase in circuit scale and power consumption. It is desirable to set.

As a result, when the input voltage of the first-stage inverter circuit falls, the first battery ground potential Vss is applied to the battery ground potential Vss via the activated falling hysteresis circuit (Q44, Q46).
When the n-channel MOSFET Q43 is connected, the threshold level VtL of the first-stage inverter circuit at the time of the fall of the input voltage can be adjusted based on only the threshold level nVth of the first n-channel MOSFET Q43 without enlarging the circuit scale or power consumption. There is an effect that a circuit suitable for integration that can be set can be realized.

The operation of the hysteresis inverter circuit 30 (Q26, Q31) will be described in more detail.

When the input In has the logical value L, the output Out also transitions to the logical value L. At this time, the p-channel MOSFET Q45
Are activated, and the n-channel MOSFET Q46 is inactivated.

The activation resistance of p-channel MOSFET Q45 is made sufficiently smaller than rising hysteresis resistance element Q41, and n-channel MOSFE is made smaller than falling hysteresis resistance element Q44.
If the activation resistance of TQ46 is made sufficiently small, the first-stage inverter circuits (Q42, Q43) will have a p-channel MOSFE
It is composed of TQ45, Q42, n-channel MOSFET Q43 and falling hysteresis resistance element Q44, and the threshold level becomes almost equal to Vth of p-channel MOSFET Q42.

Similarly, when In has the logical value H, Out is the logical value H, the p-channel MOSFET Q45 is inactive, and the n-channel MOSFET Q46 is active. , Rising hysteresis resistance element Q41, p-channel MOSFET Q42,
It is composed of n-channel MOSFETs Q43 and Q46, and the threshold level is n-channel MOS
It substantially matches the value of VtH of FET Q43.

Therefore, the thresholds VtH, VIL of the hysteresis inverter circuit 30 (Q26, Q31) shown in FIG.
VtH = secondary battery potential VDD− | threshold level pVth | of p-channel MOSFET, VIL = battery ground potential Vss + n-channel MOSFET
T becomes the threshold level nVth, and a sufficient hysteresis width (difference between VtH and VIL) can be obtained, and a hysteresis inverter circuit 30 (Q26, Q31) effective for preventing oscillation can be formed. Of course, the hysteresis inverter circuit 30 of another circuit configuration
The same applies when (Q26, Q31) is used.

FIG. 3 shows a hysteresis inverter circuit 30.
9 is a graph for explaining an operation of setting the input voltage threshold level VtH when the input voltage of the first-stage inverter circuit rises in (Q26, Q31).

In the overcurrent detection circuit 25, when an overcurrent flows and the charger ground potential V− (the negative terminal of the battery pack 10) becomes higher than Vref, the comparator Q21 is inverted. As a result, the capacitor C2 in the delay circuit 26 is charged with the constant current I from the constant current source Q24, and when the potential of the node a in FIG. 5 gradually rises and reaches the threshold level of the hysteresis inverter Q26, the hysteresis inverter The output of Q26 is inverted,
The discharge signal output terminal Dout has the logical value L.

The hysteresis inverter circuit 30 (Q26,
Q31) is activated (ON) when the input voltage of the first-stage inverter circuit (Q42, Q43) rises as shown in FIG.
Through the rising hysteresis circuit (Q41, Q45)
At the same time when the first p-channel MOSFET Q42 is connected to the next battery potential VDD, the first n-channel MOSFET Q43 is connected to the battery ground potential via the inactivated (OFF) falling hysteresis circuits (Q44, Q46) and the falling hysteresis resistance element Q44. The circuit configuration is such that it is connected to Vss.

More in detail, hysteresis inverter circuit 3
The operation of 0 (Q26, Q31) will be described.

The secondary battery potential VDD is the voltage of the battery cell 12. When an overcurrent flows, the secondary battery potential VDD voltage drops as shown in FIG. 3 due to the internal impedance of the battery cell 12. At this moment, the condenser C described later
The charging current starts to flow in 2 (see FIG. 5), and the node a rises as shown in FIG.

Then, as shown in FIG. 3, the threshold V of the hysteresis inverter circuit 30 (Q26, Q31) is increased.
When tH is reached, the discharge signal output terminal Dout transitions to the logical value L, and in order to inactivate the discharge transistor Q1 in FIG. 1, a discharge current (in FIG. Current) stops flowing and 2
The secondary battery potential VDD voltage rises sharply.

At this time, as shown in FIG. 3, when a one-level threshold inverter is used instead of the hysteresis inverter circuit 30 (Q26, Q31), the secondary battery potential VDD sharply rises as shown in FIG. At this time, the threshold level VtH also rises, so that the voltage at the node a falls again below the threshold VtH, and the discharge signal output terminal Dout again assumes the logical value H, the discharge current flows, and the secondary battery potential VDD drops. Oscillation occurs by repeating this.

The hysteresis inverter circuit 30 (Q26,
Q31), the discharge signal output terminal Dou
When t transitions to the logical value L and the secondary battery potential VDD rises, the threshold level shifts from VtH to VIL, so that the voltage of a is surely higher than the threshold level VIL, and the discharge signal output terminal Dout Stabilizes at the logical value L. The same applies when the short-circuit detection circuit 24 operates.

According to such a circuit configuration, when the input voltage of the first-stage inverter circuits (Q42, Q43) rises, the first battery voltage VDD is applied to the secondary battery potential VDD via the activated rising hysteresis circuits (Q41, Q45). By connecting the channel MOSFET Q42, the first p-channel MOSFET
Based on only the threshold level pVth of TQ42, the first-stage inverter circuit (Q42,
There is an effect that a circuit suitable for integration can be realized in which the threshold level VtH of Q43) can be set without enlarging the circuit scale or power consumption.

FIG. 4 shows a hysteresis inverter circuit 30.
10 is a graph for explaining an operation of setting an input voltage threshold level VtL at the time of detecting a short circuit of the first-stage inverter circuit in (Q26, Q31).

When the short circuit of the first-stage inverter circuit (Q42, Q43) is detected, as shown in FIG. 4, the secondary battery potential is passed through the inactivated rising hysteresis circuit (Q41, Q45) and rising hysteresis resistance element Q41. At the same time that the first p-channel MOSFET Q42 is connected to VDD, the first n-channel MOSFET Q43 is connected to the battery ground potential Vss via the activated falling hysteresis circuit (Q44, Q46).

More in detail, hysteresis inverter circuit 3
The operation of 0 (Q26, Q31) will be described.

When the charger ground potential V-level exceeds the threshold level of the hysteresis inverter Q36 of the short-circuit detection circuit 24 of FIG.
Let t be a logical value L so that no current flows.

FIG. 4 shows the voltage waveform at this time. When the load is short-circuited, the level of the charger ground potential V- rises as shown in FIG.

When the charger ground potential V- reaches the threshold VtH of the hysteresis inverter Q36, the discharge signal output terminal Dout transitions to the logical value L, and the secondary battery potential VDD.
Although the voltage rises, oscillation does not occur similarly because the threshold level of the hysteresis inverter Q36 shifts to VtL.

According to such a circuit configuration, when the short circuit of the first-stage inverter circuit (Q42, Q43) is detected, the first nth inverter circuit (Q44, Q46) is activated via the activated falling hysteresis circuit (Q44, Q46).
When the channel MOSFET Q43 is connected to the battery ground potential Vss, the first n-channel MOSFET
A circuit suitable for integration can be realized in which the threshold level VtL of the first-stage inverter circuit when the input voltage falls can be set based only on the threshold level nVth of the TQ43 without enlarging the circuit scale or power consumption. This has the effect.

As described above, according to the hysteresis inverter circuit 30 (Q26, Q31), the circuit configuration is simpler than that of the comparator with the latch function, the circuit scale is compact, the chip area is small, and the power consumption is small. And the hysteresis inverter circuit 30 (Q26, Q31) can be realized by using the rising hysteresis circuit (Q41, Q45) and the falling hysteresis circuit (Q44, Q46), which can reduce the consumption of the lithium ion battery 12. Play.

Subsequently, based on FIG. 1, the charge / discharge protection IC 2
An embodiment of the configuration circuit of 0 will be described.

The overcharge detection circuit 22 is connected to the charging potential VDD (the positive terminal of the battery pack 10) of the charger 14 for charging the lithium ion battery 12, and monitors the state of charge of the lithium ion battery 12 and When the state of charge is detected, the overcharge detection signal 22a
(The logical value H when charging is possible), and the overcharge detection circuit 22 is activated when the overcharge detection circuit 22 is activated according to the chargeable state of the lithium ion battery 12.
To a battery ground potential Vss logic signal (not shown).

The use of such an overcharge detection circuit 22 makes it possible to detect the chargeable state and the overcharge state of the lithium ion battery 12 separately.

As shown in FIG. 1, the level shift circuit 23 is a charger 1 for charging the lithium ion battery 12.
4 and has a function of shifting the battery ground potential Vss to the charger ground potential V- to generate a charge control signal 23a (logic signal).

As described above, since the level shift circuit 23 is connected to the charging potential of the charger 14, when the charger 14 is connected to the charging potential, the level shift circuit 23 becomes operable by receiving power supply from the charger 14. The charge control signal 23a can be generated. That is, the lithium ion battery 12
Even if the ability to supply enough power to operate the charge / discharge protection IC 20 is lost.
Is connected to the charging potential, the level shift circuit 23 becomes operable and can generate the charge control signal 23a. This is the case where the battery voltage of the lithium ion battery 12 falls below the operable voltage. Also charger 1
The connection of 4 makes it possible to realize a function of executing reliable charge control. As a result, the charge control of the lithium ion battery 12 can be performed by controlling the charge transistor Q2 by using the charge control signal 23a, and the ability to supply enough power to operate the charge / discharge protection IC 20 is increased. This has the effect of being able to be restored. Further, by providing the hysteresis inverter circuit Q26, such a circuit configuration is simpler than that of the comparator with a latch function, and a compact circuit scale, a small chip area, and low power consumption with reduced consumption of the lithium ion battery 12 are provided. The level shift circuit 23 having a charge control function can be realized.

As shown in FIG. 9, the level shift circuit 23 includes a drain of a depletion-type n-channel transistor Q4 whose source and gate are connected in saturation and operates as a constant current source, and an enhancement-type p-channel transistor Q3. Are connected in series, the drain of a depletion-type n-channel transistor Q4 is connected to a charger ground potential V-, and the source of an enhancement-type p-channel transistor Q3 is a secondary battery potential VDD. The circuit configuration is connected to the potential VDD.

According to such a circuit configuration, the source of the enhancement-type p-channel transistor Q 3 suitable for low power consumption by reducing the power consumption of the lithium ion battery 12 by reducing the compact circuit scale, small chip area, Since it is connected to the secondary battery potential VDD which is a charging potential, it can be activated only by inputting a logic signal of a logic value L to the gate. On the other hand, a depletion-type n suitable for a small circuit size, a small chip area, and low power consumption with reduced consumption of the lithium ion battery 12.
Since the channel transistor Q4 is saturated and always in an active state, the level shift circuit 23 can be in an operable state. As a result, even when the charger 14 is connected to the charging potential, the power is not supplied from the charger 14. , And becomes operable, and the charge control signal 23a can be generated. That is, even if the ability to supply enough power to operate the charge / discharge protection IC 20 to the lithium ion battery 12 has been lost, the level shift circuit 23 is in an operable state if the charger 14 is connected to the charging potential. And the charge control signal 23a can be generated,
Even when the battery voltage of the lithium ion battery 12 falls below the operable voltage, the function of executing the reliable charge control can be realized by connecting the charger 14. As a result, the charge transistor Q2 is controlled by using the charge control signal 23a, so that the charge of the lithium ion battery 12 can be controlled.
This has the effect that the ability to supply enough power to operate the battery 20 can be restored in the lithium ion battery 12.

The over-discharge detecting circuit 27 detects the secondary battery potential V which is the potential of the positive terminal of the lithium ion battery 12.
It is connected between DD and the battery ground potential Vss, and has a circuit configuration for monitoring the discharge state of the lithium ion battery 12 and generating an overdischarge detection signal 27a (logical signal) when detecting the overdischarge state.

According to such a circuit configuration, by providing the overdischarge detection circuit 27, the overdischarge detection signal 27a can be generated when the overdischarge state is detected by monitoring the discharge state of the lithium ion battery 12. become.

The over-discharge detection circuit 27 includes a pull-up transistor (not shown) for connecting the charger ground potential V- to the secondary battery potential VDD when activated in accordance with the over-discharge state of the lithium ion battery 12. )have.

According to this, the lithium ion battery 1
2 becomes equal to or lower than the overdischarge detection voltage, the discharging transistor Q1 is inactivated, and when the mobile phone 14 is connected, the mobile phone 14 is connected, and even if the mobile phone 14 is not connected, The pull-up transistor makes it possible to raise the charger ground potential V- to the secondary battery potential VDD. As a result, the hysteresis inverter of the short-circuit detection circuit 24 is inverted to be in a short-circuit detection state, and a short-circuit detection signal 24a (logical signal) is generated. At the same time, the entire circuit of the charge / discharge protection IC 20 is stopped using the short-circuit detection signal 24a. A standby function for reducing current consumption to zero can be added to the overdischarge detection circuit 27. As a result, it is possible to further reduce the circuit size and the chip area, and further reduce the consumption of the lithium ion battery 12.

Further, the overdischarge detection circuit 27 has a function of monitoring the discharge state of the lithium ion battery 12 and generating an overdischarge detection signal 27a (logical value L at the time of overdischarge detection) when the overdischarge state is detected. Have.

By providing such an over-discharge detection circuit 27, the over-discharge detection signal 27 is detected when the over-discharge state is detected by monitoring the discharge state of the lithium ion battery 12.
a can be generated.

FIG. 5 illustrates a first embodiment of the circuit configuration of the short circuit detection circuit 24 having an inverter circuit, the overcurrent detection circuit 25, and the delay circuit 26 having an inverter circuit in the charge / discharge protection circuit 20 of FIG. FIG.

As shown in FIG. 5, the short-circuit detection circuit 24
A hysteresis inverter circuit Q31 connected to the charger ground potential V-, the hysteresis inverter circuit Q31 monitoring the potential of the charger ground potential V- and, at the same time, generating a short-circuit detection signal 24a when detecting a short-circuit state; have. Note that the output value from the hysteresis inverter circuit Q31 is changed to the logic element NOT in order to achieve logic consistency.
The logic element NOTQ33 and the logic element NO
It is desirable to use a circuit configuration for outputting to RQ28.

The inverted signal (logic signal) of the output value from the logic element NOTQ33 is output together with the overdischarge detection signal 27a (logic signal having a logic value L when overdischarge is detected) and the logic element NORQ.
The signal is input to the circuit 34 and is output as a short-circuit detection signal 24a after the NOR operation. When the logical value of the short-circuit detection signal 24a becomes H, all circuits constituting the charge / discharge protection circuit 20 are stopped.

As described above, by providing the short-circuit detecting circuit 24 having the hysteresis inverter circuit Q31, the potential of the charger ground potential V- can be input to the above-described hysteresis inverter circuit Q31. And the short-circuit detection signal 24a having a hysteresis characteristic that can be specified by the input voltage threshold level VtH and the falling input voltage threshold level VtL. Such a hysteresis characteristic is represented by the short-circuit detection signal 2
4a, it is possible to realize an oscillation prevention function at the time of overcurrent detection in the short-circuit detection state, and to control the discharge current using the short-circuit detection signal 24a. The function of preventing oscillation at the time of detection can be realized. Furthermore, by providing the hysteresis inverter circuit Q31, such a circuit configuration is simpler than that of a comparator with a latch function, and a compact circuit scale, a small chip area, and low power consumption with reduced consumption of the lithium ion battery 12 are provided. The short-circuit detection circuit 24 having the oscillation preventing function can be realized.

The short-circuit detecting circuit 24 instructs a standby operation for stopping all circuits in accordance with the charger ground potential V- when the pull-up transistor is activated in accordance with the overdischarge state of the lithium ion battery 12. The circuit configuration is such that the short-circuit detection signal 24a is generated by the hysteresis inverter circuit Q31.

Specifically, when the voltage of the battery cell 12 becomes lower than the overdischarge detection voltage, the discharging transistor Q1 is deactivated, and the charger ground potential V-level is set at the load if the load is connected. , Even if no load is connected, the secondary battery potential VDD
Rise to the level. Thereby, the short-circuit detection circuit 24
The hysteresis inverter Q31 inverts and the short-circuit detection state occurs. At the same time, all the circuits are stopped, and the node g, which is a logic signal for reducing the current consumption to 0, has the logic value H. That is, the short circuit detection circuit 24 also serves as a standby circuit for stopping all circuits.

According to such a circuit configuration, a short circuit instructing a standby operation using hysteresis inverter circuit Q31 having hysteresis characteristics that can be specified by input voltage threshold level VtH at the time of rising and input voltage threshold level VtL at the time of falling. By generating the detection signal 24a, it is possible to realize an oscillation prevention function at the time of detecting an overcurrent in the short-circuit detection state.
Transistor Q1 for controlling the discharge current by using
The function of preventing oscillation when overcurrent is detected in the short-circuit detection state can be realized. Further, by providing the hysteresis inverter circuit Q31, the circuit configuration is simpler than that of the comparator with a latch function, and the circuit scale is compact.
The short-circuit detection circuit 24 having such an oscillation preventing function can be realized with a small chip area and low power consumption in which the consumption of the lithium ion battery 12 is reduced.

In the short-circuit detecting circuit 24, the charger 14 is connected between the charger ground potential V- and the secondary battery potential VDD, and the charger ground potential V- is set to the hysteresis inverter circuit Q.
The circuit configuration is such that the hysteresis inverter circuit Q31 generates a short-circuit detection signal 24a for returning from the standby operation to the start of operation of all circuits when the voltage falls below the threshold level VtL of 31.

According to this, the lithium ion battery 1
After 2 detects overdischarge, stop all circuits,
Even if the current consumption is set to 0, the charging / discharging protection I that makes all circuits operate again by connecting the charger 14
C20 can be realized.

Specifically, when the charger 14 is connected and the ground potential V- of the charger falls below the VtL of the hysteresis inverter Q31 of the short-circuit detection circuit 24, the node g changes to the logical value L, Operates and changes from the standby state to the operating state. The inside of the hysteresis inverter Q31 is
2, there is no path that consumes current. Therefore,
Even when the current consumption is 0 at the time of standby, it is possible to easily configure a circuit that detects that the charger 14 is connected and puts it into the operating state.

That is, the short-circuit detection signal 24a for returning to the start of operation of all circuits using the hysteresis inverter circuit Q31 having hysteresis characteristics that can be specified by the input voltage threshold level VtH when rising and the input voltage threshold level VtL when falling is used. This makes it possible to realize an oscillation prevention function at the time of overcurrent detection in the short-circuit detection state, and to control the discharge current using the short-circuit detection signal 24a. Can be realized. Furthermore, by providing the hysteresis inverter circuit Q31, such a circuit configuration is simpler than that of a comparator with a latch function, and a compact circuit scale, a small chip area, and low power consumption with reduced consumption of the lithium ion battery 12 are provided. The short-circuit detection circuit 24 having the oscillation preventing function can be realized.

As shown in FIG. 5, the overcurrent detection circuit 25 is connected to the charger ground potential V−, monitors the potential of the charger ground potential V− using the reference voltage Vref as the comparator forward potential, It has a function of generating an overcurrent detection signal 25a (logic signal) when detecting a current state.

In the overcurrent detection circuit 25, when an overcurrent flows and the charger ground potential V- becomes higher than the reference voltage Vref, the comparator Q21 is inverted.

As a result, the capacitor C2 in the delay circuit 26 is charged by the constant current I from the constant current source Q24, and when the potential of the node a gradually rises and reaches the threshold level of the inverter circuit Q26A, the inverter circuit The output of Q26A is inverted, and the discharge signal output terminal Dou
t becomes the logical value L.

The delay circuit 26 includes an inverter circuit Q26
A (that is, a logic element NOT), and the over-discharge state in the lithium ion battery 12 is determined according to the over-current detection signal 25a and the over-discharge detection signal 27a (logic signal having a logic value L when over-discharge is detected). Delay signal 26 for setting a delay time related to detection timing
a (logic signal) is generated via the inverter circuit Q26A, and when the overcharge detection signal 22a (logic signal) has been detected, the overcharge detection potential (4.25 VDC) or higher is further detected.
When the next battery potential VDD is detected, an instruction is given to cancel the discharge control according to the overdischarge state and to cancel the discharge control according to the overcurrent state, and at the same time, the discharge transistor Q1 connected to the mobile phone 14 is activated. A delay signal 26a for instructing discharge control for supplying a load current to the mobile phone 14 via a parasitic diode existing in parallel between the drain and source of the charging transistor Q2 and the activated discharging transistor Q1 is converted to an inverter. Circuit Q26
It has a function of generating via A.

That is, the delay circuit 26 detects the overdischarge detection signal 22a and the overdischarge detection signal 27a and the overcurrent when the rechargeable battery potential VDD higher than the overcharge detection potential (4.25 VDC) is detected. A discharge control instruction for supplying a load current to the mobile phone 14 by activating the discharge transistor Q1 connected to the mobile phone 14 prior to the discharge control instruction related to the detection signal 25a is executed.

By providing such a delay circuit 26, the overcharge detection potential (F) is further detected when the overcharge detection signal 22a is detected rather than the discharge control for the overdischarge detection signal 27a and the discharge control for the overcurrent detection signal 25a. 4.
When the secondary battery potential VDD of 25 VDC or higher is detected, priority can be given to the discharge control relating to the activation of the discharging transistor Q1, and as a result, the overcharge detection potential (4.25 VDC) or higher can be obtained. Also, a discharge control function for activating the discharge transistor Q1 and supplying the load current to the mobile phone 14 via the parasitic diode and the discharge transistor Q1 without erroneously determining the load current when the mobile phone 14 is connected as an overcurrent. Similarly, the secondary battery potential VDD when the overcurrent with respect to the load current when the mobile phone 14 is connected is detected by using the pulse charger 14 as the charger 14 is equal to or higher than the overcharge detection potential (4.25 VDC). Even when the load current is held, the load current is supplied to the mobile phone 14 while avoiding the false determination of the overcurrent state and the inactivation of the discharge transistor. There is an effect that the power control function can be realized with a small circuit scale.

Here, the gate circuits Q22, Q23, Q25, and Q27 in the delay circuit 26 further receive the overcharge detection potential (4.25 VDC) while receiving the overcharge detection signal 22a.
When the above-mentioned secondary battery potential VDD is detected, the control to cut off the overdischarge detection signal 27a and the overcurrent detection signal 25a is executed for the inverter circuit Q26A, and at the same time, the discharging transistor connected to the mobile phone 14 is connected. The circuit configuration is such that control for generating a delay signal 26a instructing activation of Q1 is performed on inverter circuit Q26A.

That is, the delay circuit 26 responds to the overcharge detection signal 22a when the overcharge detection signal 22a is received and the secondary battery potential VDD that is higher than the overcharge detection potential (4.25 VDC) is detected. , Overdischarge detection signal 2
The gate circuit Q22, Q23, Q25, Q27 is controlled to cut off the 7a and the overcurrent detection signal 25a and inhibit the generation of the delay signal 26a related to the overdischarge detection signal 27a or the delay signal 26a related to the overcharge detection signal 22a. At the same time, the delay signal 26a for activating the discharging transistor Q1 connected to the mobile phone 14
Control to instruct generation of the gate circuits Q22, Q23, Q25,
This will be executed for Q27.

As an example, the delay circuit 26 has a logic element NANDQ22 to which an overcurrent detection signal 25a and an overdischarge detection signal 27a (a logic signal having a logic value L when overdischarge is detected), and a logic element NANDQ22. A logic element NOTQ23 for inverting the value, a logic element NOTQ25 connected to the constant current source Q24 for inverting the output logic value of the logic element NOTQ23 according to the constant current I, and a delay signal by inverting the logic value of the logic element NOTQ25 A logic element NOTQ27 for outputting as 26a, a timing capacitor C2,
It can be configured with the MOSFET Q36 for interruption at the center.

The gate circuits Q22, Q22 having such a circuit configuration
By providing the transistors 23, Q25, and Q27, the discharge control or the delay signal 26a necessary for the discharge control can be generated and supplied to the discharge transistor Q1. Further, by providing the delay circuit 26, the overcharge detection potential (4.25 VDC) is further increased in a state where the overcharge detection signal 22a is received.
When the above-mentioned secondary battery potential VDD is detected, the overdischarge detection signal 27a and the overcurrent detection signal 25a are cut off and the discharge control and overcurrent detection signal 25
a control for inhibiting the generation of the delay signal 26a required for the discharge control for the discharge control signal a, and further detecting the overcharge detection signal 22a to further increase the overcharge detection potential (4.25 VDC)
The generation of the delay signal 26a required for the discharge control relating to the activation of the discharge transistor Q1 when the above-described secondary battery potential VDD is detected can be permitted. As a result, the overcharge detection potential (4.25VDC) Even if the above is true, the load current when the mobile phone 14 is connected is not erroneously determined as overcharge, and the discharge transistor Q1 is activated to supply the load current to the mobile phone 14 via the parasitic diode and the discharge transistor Q1. Similarly, a pulse charger 14 is used as the charger 14, and the secondary battery potential VDD when the overcurrent with respect to the load current when the mobile phone 14 is connected is detected is changed to the overcharge detection potential (4 .25VD
C) Even if the discharge current is held above, the discharge control function of supplying the load current to the mobile phone 14 by avoiding the inactivation of the discharge transistor due to the erroneous determination of the overcurrent state is reduced in circuit scale. This has the effect of being able to be realized with.

The timing capacitor C2 is provided with an inverter for setting a delay time related to the timing of executing the discharge control according to the overdischarge detection signal 27a and a delay time related to the timing of executing the discharge control according to the overcurrent detection signal 25a. The circuit configuration is connected to the input of the circuit Q26A.

The blocking MOSFET Q36 (specifically, n
The channel MOSFET has a drain connected to the output of the logic element NOTQ25, a source connected to the ground potential, a gate connected to the output stage of the overcharge detection circuit 22, and a parallel connection to the input of the inverter circuit Q26A and the timing capacitor C2. To the overcharge detection potential (4.25) while receiving the overcharge detection signal 22a (logic signal).
VDC) or overcurrent detection signal 27a (logic signal) or overcurrent detection signal 25a according to the input of the overcharge detection signal 22a to the gate when the secondary battery potential VDD equal to or higher than VDC is detected.
The circuit configuration is such that the charge stored in the timing capacitor C2 is short-circuited by (logic signal).

MOSFET for shutting off having such a circuit configuration
Q36 is the secondary battery potential V which is higher than the overcharge detection potential (4.25 VDC) while the overcharge detection signal 22a is received.
In response to the input of the overcharge detection signal 22a to the gate when the DD is detected, the input of the overdischarge detection signal 27a and the overcurrent detection signal 25a to the gate circuits Q22, Q23, Q25, and Q27 is interrupted to delay the signal. A logic signal for inhibiting generation of the discharge transistor Q1 is output to the inverter circuit Q26A at the same time as outputting a logic signal for instructing generation of the delay signal 26a for activating the discharge transistor Q1 to the inverter circuit Q26A. .

By providing such an interrupting MOSFET Q36, overcharge detection is performed when the secondary battery potential VDD that is higher than the overcharge detection potential (4.25 VDC) is detected while the overcharge detection signal 22a is received. The shut-off MOSFET Q36 is activated in response to the input of the signal 22a to the gate, and the input of the overdischarge detection signal 27a and the overcurrent detection signal 25a to the inverter circuit Q26A is cut off to cause the overdischarge detection signal 27.
a logical control for inhibiting the generation of the delay signal 26a required for the discharge control relating to the overcurrent detection signal 25a and the discharge control relating to the overcurrent detection signal 25a, and further detecting the overcharge detection signal 22a, and further detecting the overcharge detection potential (4.25VDC) Discharge transistor Q when detecting the above secondary battery potential VDD
Delay signal 26 required for discharge control for activation of 1
It is possible to execute a logical control for generating a delay signal 26a that preferentially permits the generation of a to the inverter circuit Q26A. As a result, the overcharge detection potential (4.25 V
DC) or more, the load current when the mobile phone 14 is connected is not erroneously determined as an overcurrent, and the discharge transistor Q1 is activated to transfer the load current to the mobile phone 14 via the parasitic diode and the discharge transistor Q1. Similarly, a discharge control function for supplying the battery can be realized. Similarly, the pulse battery charger 14 is used as the charger 14, and when the overcurrent with respect to the load current when the mobile phone 14 is connected is detected, the secondary battery potential VDD becomes the overcharge detection potential ( Even if the voltage is maintained at 4.25 VDC or more, the discharge control function of supplying the load current to the mobile phone 14 while avoiding the erroneous determination of the overcurrent state and the inactivation of the discharge transistor is prevented. Inverter circuit Q that can be controlled
The use of 26A and the blocking MOSFET Q36 has the effect of realizing a small circuit scale and a circuit form suitable for integration.

Further, the inverter circuit Q26A includes a hysteresis circuit (Q4) in which the potential of the timing capacitor C2 rises.
1, Q45), a delay signal 26a for inactivating the discharging transistor Q1 is generated when the threshold voltage VtH is higher than the threshold voltage VtH when the input voltage rises, and the potential of the timing capacitor C2 rises.
Q45) has a circuit configuration for generating a delay signal 26a for activating the discharging transistor Q1 when the input voltage is lower than the threshold level VtH when the input voltage rises.

According to such a circuit configuration, the capacitor potential according to the charge accumulation in the timing capacitor C2 using the overdischarge detection signal 27a and the overcurrent detection signal 25a and the input voltage in the rising hysteresis circuit (Q41, Q45). A delay signal 26a for deactivating the discharge transistor Q1 when the capacitor potential becomes equal to or higher than the threshold level VtH when the input voltage rises can be generated by comparing with the threshold level VtH when the rise occurs, and the rising hysteresis circuit can be generated. A delay signal 2 for activating the discharging transistor Q1 when the input voltage rises below the threshold level VtH at (Q41, Q45).
6a can be generated. As a result, it becomes possible to generate the delay signal 26a having hysteresis characteristics that can be specified by the input voltage threshold level VtH at the time of rising and the input voltage threshold level VtL at the time of falling.
By providing such a hysteresis characteristic to the delay signal 26a, an oscillation preventing function at the time of overcurrent detection can be realized, and the overcurrent detection of the discharge transistor Q1 for controlling the discharge current using the delay signal 26a can be realized. The oscillation prevention function at the time can be realized. Further, by providing the inverter circuit Q26A, the circuit configuration is simpler than that of the comparator with a latch function, the circuit size is small, the chip area is small,
Thus, the overcurrent detection circuit 25 having such an oscillation prevention function can be realized with low power consumption with reduced consumption of the power supply 2.

FIG. 6 shows a second circuit configuration of the charge / discharge protection circuit 20 of FIG. 1 including a short-circuit detection circuit 24 having a hysteresis inverter circuit Q31, an overcurrent detection circuit 25, and a delay circuit 26 having a hysteresis inverter circuit Q26. FIG. 2 is a circuit diagram for explaining the embodiment. FIG.
Battery pack 1 using charge / discharge protection circuit 20 of FIG.
FIG. 7A is a graph for explaining an operation for preventing overcurrent from being detected when the charger 14 is connected to the battery charger 14 and when the mobile phone 14 is connected, and FIG. 7A shows a change in the secondary battery potential VDD. 7 (b) shows a change in the ground potential V- of the charger 14, FIG. 7 (c) shows a change in the potential of the charging signal output terminal Cout, and FIG. 7 (d) shows a node a (hysteresis inverter circuit Q26). FIG. 7 shows the potential change of the input terminal of FIG.
(E) is a graph for explaining a potential change of the discharge signal 26b output terminal Dout. The same parts as those already described in the first embodiment of the delay circuit 26 (specifically, the short-circuit detection circuit 24, the overcurrent detection circuit 2
Regarding 5), the same reference numerals are given, and duplicate description is omitted.

The delay circuit 26 according to the second embodiment includes a first
It is characterized in that a hysteresis inverter circuit Q26 is used instead of the inverter circuit Q26A of the delay circuit 26 of the embodiment.

The delay circuit 26 has an overdischarge detection signal 27
a, a delay signal 26a for detecting an overdischarge state in the lithium ion battery 12 and executing discharge control is generated via a hysteresis inverter circuit Q26, and the lithium ion battery 12 is detected in response to an overcurrent detection signal 25a. Generates a delay signal 26a for detecting the overcurrent state and executing the discharge control via the hysteresis inverter circuit Q26, and further detects the overcharge detection signal 22a and further generates an overcharge detection potential (4.2).
When a secondary battery potential VDD of 5 VDC or higher is detected, the discharging transistor Q1 connected to the mobile phone 14 is activated, and at the same time, a parasitic diode existing in parallel between the drain and source of the charging transistor Q2 is activated. The mobile phone 14 via the activated discharging transistor Q1
Has a circuit configuration for executing discharge control for supplying a load current to the circuit.

The hysteresis inverter circuit Q26 has a circuit configuration for generating a delay signal 26a for the overdischarge detection signal 27a or a delay signal 26a for the overcharge detection signal 22a, as in the case of the inverter circuit Q26A.

In this case, the delay circuit 26 further receives the overcharge detection potential (4.
The overdischarge detection signal 27a and the overcurrent detection signal 25a are cut off according to the overcharge detection signal 22a when the secondary battery potential VDD of 25 VDC or higher is detected.
signal 26a or overcharge detection signal 2
The control for inhibiting the generation of the delay signal 26a relating to 2a is performed on the hysteresis inverter circuit Q26, and the control for instructing the generation of the delay signal 26a for activating the discharge transistor Q1 connected to the mobile phone 14 at the same time. To the hysteresis inverter circuit Q26.

As in the case of the inverter circuit Q26A, the timing capacitor C2 in the delay circuit 26 has a delay time related to the timing at which the discharge control is performed according to the overdischarge detection signal 27a, and a delay time according to the overcurrent detection signal 25a. The circuit configuration is connected to the input of the hysteresis inverter circuit Q26 in order to set a delay time related to the timing of executing the discharge control.

MOSF for cutoff in delay circuit 26
The ETQ 36 is connected in parallel to the input of the hysteresis inverter circuit Q26 to the timing capacitor C2, and outputs an overcharge detection signal 22a that outputs a logical value H when overcharge is detected, as in the case of the inverter circuit Q26A described above.
While receiving the overcharge detection potential (4.25 VD
C) In response to the input of the overcharge detection signal 22a to the gate when the above secondary battery potential VDD is detected, as shown in FIG. 7 (d), the overcharge detection signal 27a or the overcurrent detection signal 25a The circuit configuration is such that the charge stored in the timing capacitor C2 is short-circuited.

That is, in the state where overcharge is detected (the overcharge detection signal 22a of the logical value H), the n-channel M
The OSFET (blocking MOSFET) Q36 is activated, and the node a is always at the logical value L (ground potential).

At this time, if the potential of the node a (see FIG. 7D) does not become equal to or higher than the threshold level VtH of the hysteresis inverter Q26, the potential of the discharge signal output terminal Dout (see FIG. 7E) becomes the logical value L. Therefore, in the overcharge detection state, the potential of the discharge signal output terminal Dout is always at the logical value H (VDD).

According to such a circuit configuration, the blocking MO
By providing the SFET Q36, the overcharge detection signal 22
a while receiving the overcharge detection potential (4.25 VD
C) In response to the input of the overcharge detection signal 22a to the gate when the above secondary battery potential VDD is detected, the MOSFET
TQ36 is activated to stop the overdischarge detection signal 27a and the overcurrent detection signal 25a from accumulating charge in the timing capacitor C2, thereby controlling the discharge control for the overdischarge detection signal 27a and the delay signal 26a required for the discharge control for the overcurrent detection signal 25a. Activation of the discharge transistor Q1 when the logic control for inhibiting generation is executed and the secondary battery potential VDD that is higher than the overcharge detection potential (4.25 VDC) is detected while the overcharge detection signal 22a is detected. Logic control for generating a delay signal 26a that preferentially permits the generation of the delay signal 26a required for the discharge control for the hysteresis inverter circuit Q26. As a result, even when the overcurrent is equal to or higher than the overcharge detection potential (4.25 VDC), the load current when the mobile phone 14 is connected is not erroneously determined as an overcurrent, and the discharge transistor Q1 is activated to activate the parasitic diode and the discharge transistor Q1. , A discharge control function of supplying a load current to the mobile phone 14 via the mobile phone 14 can be realized. Similarly, when a pulse charger 14 is used as the charger 14 and an overcurrent with respect to the load current when the mobile phone 14 is connected is detected. The secondary battery potential VDD is equal to the overcharge detection potential (4.25).
(VDC) or more, the load current is supplied to the mobile phone 14 while avoiding the false inactivation of the discharge transistor based on the potential of the timing capacitor C2 and the inactivation of the discharge transistor based on the potential of the timing capacitor C2. The use of the hysteresis inverter circuit Q26 and the shutoff MOSFET Q36, which can logically control the discharge control function to be performed, has the effect of realizing a small circuit scale and a circuit form suitable for integration.

Further, the hysteresis inverter circuit Q26 includes:
When the potential of the timing capacitor C2 is equal to or higher than the threshold level VtH when the input voltage rises in the rising hysteresis circuit (Q41, Q45), a delay signal 26a for inactivating the discharging transistor Q1 is generated, and the potential of the timing capacitor C2 becomes When the input voltage in the rising hysteresis circuit (Q41, Q45) is lower than the threshold level VtH at the time of rising, the discharging transistor Q1
Circuit circuit for generating a delay signal 26a for activating the signal.

If the potential of the input node a of the hysteresis inverter Q26 does not exceed the threshold level VtH (see FIG. 7D), the potential of the delay signal 26a at the discharge signal output terminal Dout (see FIG. 7E) becomes high. Since the logical value does not become L, the potential of the delay signal 26a at the discharge signal output terminal Dout always becomes the logical value H (VDD) in the overcharge detection state.

That is, when the secondary battery potential VDD (see FIG. 7A) is equal to or higher than the overcharge potential Vdet1 (see FIG. 7A) after the overcharge detection by the overcharge detection circuit 22,
4 is connected to release the hysteresis of the hysteresis inverter Q26, the charge signal output terminal Cout (FIG. 7 (c)).
Even if the charge control signal 23a is in the state of the logical value L, the delay signal 26a at the discharge signal output terminal Dout becomes the logical value H instead of the logical value L. As a result, the load current can continue to flow through the parasitic diode of the charging transistor Q2.

According to such a circuit configuration, the capacitor potential corresponding to the charge accumulation in the timing capacitor C2 using the overdischarge detection signal 27a and the overcurrent detection signal 25a and the input voltage in the rising hysteresis circuit (Q41, Q45). By comparing the rising threshold level VtH with the rising threshold voltage VtH, it becomes possible to generate a delay signal 26a for inactivating the discharging transistor Q1 when the capacitor potential becomes equal to or higher than the threshold voltage VtH when the input voltage rises. A delay signal 2 for activating the discharging transistor Q1 when the input voltage rises below the threshold level VtH at (Q41, Q45).
6a can be generated. As a result, it becomes possible to generate the delay signal 26a having hysteresis characteristics that can be specified by the input voltage threshold level VtH at the time of rising and the input voltage threshold level VtL at the time of falling.
By providing such a hysteresis characteristic to the delay signal 26a, an oscillation preventing function at the time of overcurrent detection can be realized, and the overcurrent detection of the discharge transistor Q1 for controlling the discharge current using the delay signal 26a can be realized. The oscillation prevention function at the time can be realized. Further, by providing the hysteresis inverter circuit Q26, such a circuit configuration is simpler than that of the comparator with a latch function, and a compact circuit scale, a small chip area, and low power consumption with reduced consumption of the lithium ion battery 12 are provided. The overcurrent detection circuit 25 having the oscillation preventing function can be realized.

As described above, the charge / discharge protection circuit 20
, The secondary battery potential VDD is equal to the overcharge detection potential (4.2
Even if the load current is 5 VDC or more, the load current when the mobile phone 14 is connected is prevented from being erroneously determined as an overcurrent and the discharge transistor is inactivated, and the load current is reduced to the mobile phone 1.
4 can be realized. Similarly, the secondary battery potential VDD when an overcurrent with respect to the load current when the mobile phone 14 is connected is detected using the pulse charger 14 as the charger 14 is similarly obtained. Overcharge detection potential (4.25 VD
C) Even if the discharge current is held above, the discharge control function of supplying the load current to the mobile phone 14 by avoiding the inactivation of the discharge transistor due to the erroneous determination of the overcurrent state is reduced in circuit scale. This has the effect of being able to be realized with.

Next, an embodiment of the battery pack of the present invention will be described with reference to the drawings.

The battery pack 10 in which the above-described charge / discharge protection IC 20 is formed into an IC is incorporated.
Using 0, charging and discharging of the lithium ion battery 12 can be executed. Such a battery pack 10 is usually used by being attached to various portable devices such as a portable terminal, a mobile phone, a wireless device, etc., using the lithium ion battery 12.

FIG. 1 is a functional block diagram for explaining the configuration of the battery pack 10 of the present invention.

As shown in FIG. 1, the battery pack 10 includes a charge / discharge protection IC 20, a battery cell 12, which is a lithium ion battery 12, a discharging transistor Q1, a charging transistor Q2, and a delay capacitor C.
It is desirable that it is configured around 1.

The charge / discharge protection circuit 20 has six terminals.
A terminal to which the secondary battery potential VDD is connected, a terminal to which the battery ground potential Vss is connected, a terminal to which the delay capacitor CT is connected, a terminal Dout to which a discharge signal output is connected, a terminal Cout to which a charge signal output is connected, Charger ground potential V
-Is a terminal to be connected.

Here, when the battery cell 12 is, for example, a lithium ion battery, the overcharge detection potential is, for example, 4.
25V or 4.35V.

The delay capacitor C1 is connected to the battery ground potential Vss, generates a charge / discharge signal 12a for setting a delay time relating to the timing of detecting an overcharge state in the battery cell 12, and supplies the charge / discharge signal 12a to the above-described overcharge detection circuit 22. It has a circuit configuration for transmitting via the terminal CT.

The discharge transistor Q 1 can be turned on / off by a logic signal, is connected in series between the mobile phone 14 and the battery cell 12, and is supplied from the battery cell 12 to the mobile phone 14 during discharge control. The circuit configuration is such that the state of current supply is controlled according to the logical value of the delay signal 26a.

The discharge transistor Q1 can be turned on / off by a logic signal, and responds to the logic value of the discharge signal 26b which is the logical product of the logic value of the delay signal 26a and the logic value of the short-circuit detection signal 24a. Thus, a circuit configuration for controlling the state of conduction of a discharge current supplied from the battery cell 12 to the mobile phone 14 is provided.

According to such a circuit configuration, the logical operation of the discharge signal 26b, which is the logical product of the logical value of the delay signal 26a and the logical value of the short-circuit detection signal 24a, is executed, and according to the logical value of the operation result. Mobile phone 1 from battery cell 12
There is an effect that the current supply state of the discharge current supplied to the control unit 4 can be controlled using the discharge transistor Q1 while monitoring the overdischarge state and the short circuit state.

The charging transistor Q2 is connected in series between the charger 14 and the battery cell 12, and determines the conduction state of the charging current supplied from the charger 14 to the battery cell 12 at the time of charging control by the logical value of the charging control signal 23a. In accordance with the circuit configuration.

In this case, level shift circuit 23 provides a charge control signal 2 having a logical value for activating charge transistor Q2 when activated in accordance with charger ground potential V-.
3a is generated.

According to such a circuit configuration, by providing such a level shift circuit 23 in the charge / discharge protection IC 20, the battery voltage of the lithium ion battery 12 falls below the operable voltage. However, the connection of the charger 14 generates the charge control signal 23a for realizing the function of preventing the oscillation at the time of the overcurrent detection described above and realizing the function of executing the reliable charge control using the charging transistor Q2. It has the effect of being able to do so. Further, such a level shift circuit 23
Has a simpler circuit configuration than a comparator with a latch function, and has such a charge / discharge control function and oscillation prevention function with a compact circuit size, a small chip area, and low power consumption by reducing consumption of the lithium ion battery 12. This contributes to the realization of the battery pack 10 having the same.

As described above, the battery pack 1
According to 0, the number of circuit elements can be reduced and the small battery pack 10 can be configured by using the hysteresis inverters Q26 and Q31 to prevent oscillation at the time of overcurrent detection. Further, the above-described charge / discharge protection IC 20
Is provided, even if the battery voltage of the lithium ion battery 12 falls below the operable voltage, an oscillation preventing function at the time of overcurrent detection can be realized, and reliable discharge control can be performed by using the discharging transistor Q1. This makes it possible to realize a function of executing the charging control using the charging transistor Q2 for surely supplying the charging current even when the battery voltage becomes 0 V. Also, the level shift circuit 2 for the overcharge detection signal
By using 3 as well, without adding a circuit,
A small battery pack 10 can be configured.
In addition, when the battery voltage falls below a certain set voltage, a circuit that can not reliably flow the charging current,
By diverting the level shift circuit 23 of the overcharge detection signal, a small battery pack 10 can be configured without adding a circuit. Even if the consumption current is set to 0 after the overdischarge is detected, the circuit that detects the connection of the charger 14 and enters the operating state is obtained by diverting the hysteresis inverter Q31 of the short-circuit detection circuit 24. Thus, the small battery pack 10 can be configured without adding a circuit. Further, by providing such a charge / discharge protection IC 20, a circuit configuration is simpler than that of a comparator with a latch function, and a compact circuit size, a small chip area, and low power consumption with reduced consumption of the lithium ion battery 12 are achieved. The battery pack 10 having such a charge / discharge control function and an oscillation prevention function can be realized.

【The invention's effect】

According to the first aspect of the present invention, a simpler circuit configuration, a smaller circuit size, a smaller chip area, less power consumption, and a smaller power consumption than a comparator with a latch function are provided. A hysteresis inverter circuit can be realized by using a rising hysteresis circuit and a falling hysteresis circuit that can reduce wear.

According to the second aspect of the present invention, the first aspect is provided.
In addition to the effects described in (1), when the input voltage of the first-stage inverter circuit rises, the threshold level of the first p-channel MOSFET is connected to the power supply potential via the activated rising hysteresis circuit. Based on this, a circuit suitable for integration can be realized in which the threshold level of the first-stage inverter circuit when the input voltage rises can be set without enlarging the circuit scale or power consumption.

According to the invention described in claim 3, according to claim 1
In addition to the effect described in 2 above, when the input voltage of the first-stage inverter circuit falls, the first n-channel MOSFET is connected to the ground potential via the activated falling hysteresis circuit.
Thus, it is possible to realize a circuit suitable for integration in which the threshold level of the first-stage inverter circuit when the input voltage falls can be set only based on the threshold level without increasing the circuit scale or power consumption.

According to the invention described in claim 4, according to claim 3,
In addition to the effects described in (1), by setting the resistance value of the rising hysteresis resistance element sufficiently large as compared with the ON resistance value of the p-channel MOSFET, which does not involve an increase in circuit scale and power consumption, the first-stage inverter circuit When the first p-channel MOSFET is connected to the power supply potential via the activated rising hysteresis circuit when the input voltage rises, the first stage when the input voltage rises based only on the threshold level of the first p-channel MOSFET A circuit suitable for integration in which the threshold level of the inverter circuit can be set without enlarging the circuit scale or power consumption can be realized.

According to the invention set forth in claim 5, according to claim 3,
In addition to the effects described in (1), by setting the resistance value of the falling hysteresis resistance element sufficiently larger than the ON resistance value of the n-channel MOSFET that does not involve an increase in circuit scale and power consumption, the first-stage inverter circuit When the first n-channel MOSFET is connected to the ground potential via the activated falling hysteresis circuit when the input voltage falls, the first stage when the input voltage falls based only on the threshold level of the first n-channel MOSFET This makes it possible to realize a circuit suitable for integration in which the threshold level of the inverter circuit can be set without increasing the circuit scale or power consumption.

According to the invention described in claim 6, according to claim 1,
In addition to the effects described in any one of (3) to (3) above, the circuit scale and power consumption can be increased by setting the resistance value of the rising hysteresis resistance element sufficiently larger than the ON resistance value of the first p-channel MOSFET. This makes it possible to realize a rising hysteresis circuit suitable for integration in which a threshold level at the time of rising can be set without accompanying the integration. For the same purpose, by setting the resistance value of the falling hysteresis resistance element sufficiently larger than the ON resistance value of the first n-channel MOSFET, the falling threshold level can be set without enlarging the circuit scale and power consumption. A falling hysteresis circuit suitable for possible integration can be realized.

According to the invention of claim 7, according to claim 6,
In addition to the effects described in (1), by providing a post-stage inverter circuit that does not increase the circuit scale or increase power consumption at the output stage of the hysteresis inverter circuit, the logical value of the signal input to the first-stage inverter circuit and the hysteresis The logical value of the signal input to the first-stage inverter circuit is held by matching the logical value of the output signal of the inverter circuit, and the signal can be output from the hysteresis inverter circuit.

According to the eighth aspect of the invention, in addition to the effects of the second, third, fourth, sixth or seventh aspect, the power supply potential is a constant potential. A hysteresis inverter circuit suitable for integration in which the threshold level of the first-stage inverter circuit when the input voltage rises can be set based on only the threshold level of the first p-channel MOSFET without enlarging the circuit scale or power consumption. become able to.

According to the ninth aspect of the present invention, in addition to the effects of the second, third, fifth, sixth and seventh aspects, the ground potential is constant. A hysteresis inverter circuit suitable for integration, in which the threshold level of the first-stage inverter circuit when the input voltage falls can be set based on only the threshold level of the first n-channel MOSFET without enlarging the circuit scale and power consumption. become able to.

According to the tenth aspect, even when the secondary battery potential is equal to or higher than the overcharge detection voltage, the load current at the time of connecting the load is erroneously determined as an overcurrent, and the discharge transistor is inactivated. This makes it possible to realize a discharge control function of supplying a load current to a load while avoiding the occurrence of an overcurrent. Similarly, when an overcurrent with respect to a load current when a load is connected is detected using a pulse charger as a charger. Discharge control for supplying a load current to a load while avoiding inactivation of a discharge transistor due to erroneous determination of an overcurrent state even when the secondary battery potential is maintained at or above an overcharge detection voltage. The function can be realized with a small circuit scale.

According to the eleventh aspect of the present invention, even when the secondary battery potential is equal to or higher than the overcharge detection voltage, the load current at the time of connecting the load is not erroneously determined as an overcurrent and the discharge transistor is activated. As a result, a discharge control function of supplying a load current to a load via a parasitic diode and a discharging transistor can be realized. Similarly, a pulse charger is used as a charger, and an overcurrent with respect to the load current when a load is connected is detected. Even if the secondary battery potential at this time is maintained at or higher than the overcharge detection voltage, it is possible to prevent the load current from being improperly determined to be an overcurrent state and to inactivate the discharge transistor. The supplied discharge control function can be realized with a small circuit scale.

According to the twelfth aspect of the present invention, in addition to the effect of the tenth or eleventh aspect, by providing a delay circuit, the overcharge detection voltage is further increased in a state where the overcharge detection signal is detected. When the above-described secondary battery potential is detected, the cancellation of the discharge control according to the overdischarge state and the cancellation of the discharge control according to the overcurrent state can be executed.
As a result, in addition to the discharge control function for avoiding the over-discharge state and the over-current control function for avoiding the over-current state, when the over-current is detected when the load is connected, the secondary battery potential is higher than the over-charge detection voltage. This has the effect of realizing a discharge control function of supplying a load current to the load via the discharging transistor when the load current is low.

According to the thirteenth aspect of the present invention, in addition to the effects of any one of the tenth to twelfth aspects, by providing a delay circuit, it is possible to control the discharge control for the overdischarge detection signal and Prioritizing discharge control for activating a discharge transistor when a secondary battery potential equal to or higher than an overcharge detection voltage is detected in a state where an overcharge detection signal is detected, over discharge control for the overcurrent detection signal. As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is not erroneously determined as an overcurrent, and the discharge transistor is activated through the parasitic diode and the discharge transistor. A discharge control function of supplying a load current to the load can be realized. Similarly, a pulse battery charger is used as a charger, and the secondary battery power when an overcurrent with respect to the load current when the load is connected is detected. A small circuit with a discharge control function to supply the load current to the load while avoiding inactivation of the discharge transistor due to erroneous determination as an overcurrent state even when It can be realized on a scale.

According to the fourteenth aspect of the present invention, in addition to the effect of the thirteenth aspect, by providing a gate circuit, a discharge control or a delay signal necessary for the discharge control is generated to generate a discharge signal. It can be supplied to the transistor.
In addition, by providing a delay circuit, when the overcharge detection signal is received and the secondary battery potential that is equal to or higher than the overcharge detection voltage is detected, the overdischarge detection signal and the overcurrent detection signal are cut off and overdischarged. A control for inhibiting generation of a delay signal required for the discharge control related to the detection signal and the discharge control related to the overcurrent detection signal is performed, and furthermore, the secondary battery potential which is equal to or higher than the overcharge detection voltage in a state where the overcharge detection signal is detected. , The generation of the delay signal required for the discharge control related to the activation of the discharge transistor when the discharge is detected can be permitted. As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is reduced. A discharge control function that activates the discharge transistor and supplies the load current to the load via the parasitic diode and the discharge transistor without being erroneously determined as an overcurrent can be realized. Similarly, even if the secondary battery potential is maintained at or above the overcharge detection voltage when a pulse charger is used as the charger and an overcurrent with respect to the load current when the load is connected is detected, it is erroneously regarded as an overcurrent state. It is possible to realize a discharge control function of supplying a load current to the load with a small circuit scale while avoiding the determination that the discharge transistor is inactivated.

According to the fifteenth aspect of the present invention, in addition to the effect of the fourteenth aspect, the provision of the shut-off MOSFET further increases the overcharge detection voltage when the overcharge detection signal is received. MOSFET according to the input of the overcharge detection signal to the gate when the secondary battery potential is detected
Activating the over-discharge detection signal and the over-current detection signal to execute the discharge control over the over-discharge detection signal and the control to inhibit the generation of the delay signal required for the discharge control over the over-current detection signal, and over-charging In the state where the detection signal is detected, a control for generating a delay signal for permitting generation of a delay signal required for a discharge control for activating a discharge transistor when a secondary battery potential equal to or higher than an overcharge detection voltage is detected is executed. become able to. As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is not erroneously determined as an overcurrent, and the discharge transistor is activated to supply the load current to the load via the parasitic diode and the discharge transistor. Similarly, a pulse charger can be used as a charger, and when a secondary battery potential when an overcurrent with respect to a load current at the time of load connection is detected is held at or above an overcharge detection voltage. Even if there is, the discharge control function of supplying the load current to the load can be realized with a small circuit scale while avoiding inactivation of the discharge transistor due to erroneous determination of the overcurrent state.

According to the sixteenth aspect of the present invention, in addition to the effect of any one of the first to ninth aspects, the discharge state of the secondary battery is monitored by providing an overdischarge detection circuit. When an overdischarge state is detected, an overdischarge detection signal can be generated. Further, by providing the delay circuit having the above-mentioned hysteresis inverter circuit, the overdischarge detection signal can be inputted to the above-mentioned hysteresis inverter circuit. As a result, the input voltage threshold level when rising and the input voltage threshold when falling fall. A delay signal having a hysteresis characteristic that can be specified by the level can be generated. By providing such a hysteresis characteristic to the delay signal, it becomes possible to realize an oscillation prevention function at the time of overcurrent detection, and the oscillation of the discharge transistor that controls the discharge current using the delay signal at the time of overcurrent detection. The prevention function can be realized. Furthermore, by providing a hysteresis inverter circuit, such a circuit configuration is simpler than that of a comparator with a latch function, and a compact circuit size, a small chip area, and low power consumption with reduced consumption of secondary batteries prevent such oscillation. An overcurrent detection circuit having a function can be realized. In addition, since the level shift circuit is connected to the charging potential of the charger, when the charger is connected to the charging potential, the level shift circuit is operable by receiving power supply from the charger and can generate a charging control signal. . That is, even if the ability to supply enough power to operate the charge / discharge protection circuit to the secondary battery has been lost, if the charger is connected to the charging potential, the level shift circuit becomes operable. A charge control signal can be generated, and even when the battery voltage of the secondary battery falls below the operable voltage, a function of executing reliable charge control by connecting a charger can be realized. As a result, it becomes possible to control the charge transistor using the charge control signal to control the charge of the secondary battery, and to restore the ability of the secondary battery to supply enough power to operate the charge / discharge protection circuit. Will be able to

According to the seventeenth aspect of the present invention, in addition to the effect of the sixteenth aspect, the provision of the shut-off MOSFET further increases the overcharge detection voltage when the overcharge detection signal is received. MOSFET according to the input of the overcharge detection signal to the gate when the secondary battery potential is detected
Control for activating the overdischarge detection signal and the overcurrent detection signal to the hysteresis inverter circuit, thereby prohibiting the generation of the delay control required for the discharge control for the overdischarge detection signal and the discharge control for the overcurrent detection signal. And a hysteresis inverter circuit for generating a delay signal required for discharge control for activating a discharge transistor when a secondary battery potential equal to or higher than an overcharge detection voltage is detected while an overcharge detection signal is detected. Can be controlled to generate a delay signal that is preferentially permitted for As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is not erroneously determined as an overcurrent, and the discharge transistor is activated to supply the load current to the load via the parasitic diode and the discharge transistor. Similarly, a pulse charger can be used as a charger, and when a secondary battery potential when an overcurrent with respect to a load current at the time of load connection is detected is held at or above an overcharge detection voltage. Even if there is, the discharge control function of supplying the load current to the load can be realized with a small circuit scale while avoiding inactivation of the discharge transistor due to erroneous determination of the overcurrent state.

According to the eighteenth aspect, the same effect as that of the sixteenth aspect can be obtained.

According to the nineteenth aspect of the present invention, in addition to the effects of the seventeenth or eighteenth aspects, the blocking MOSFE
With the provision of T, when the overcharge detection signal is received and the secondary battery potential equal to or higher than the overcharge detection voltage is detected, the shutoff MO is input in response to the input of the overcharge detection signal to the gate.
Activate the SFET and cut off the input of the overdischarge detection signal and the overcurrent detection signal to the hysteresis inverter circuit, thereby inhibiting the discharge control of the overdischarge detection signal and the generation of the delay signal required for the discharge control of the overcurrent detection signal. A hysteresis inverter for generating a delay signal required for discharge control for activating a discharging transistor when a secondary battery potential equal to or higher than an overcharge detection voltage is detected while executing an control and detecting an overcharge detection signal. It is possible to execute control for generating a delay signal that is preferentially permitted to the circuit. As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is not erroneously determined as an overcurrent, and the discharge transistor is activated to supply the load current to the load via the parasitic diode and the discharge transistor. Similarly, a pulse charger is used as a charger, and when a secondary battery potential when an overcurrent with respect to a load current when a load is connected is detected is maintained at or above an overcharge detection voltage. Even if there is, the discharge control function to supply the load current to the load by avoiding the inactivation of the discharge transistor due to erroneous determination of the overcurrent state is achieved by using a hysteresis inverter circuit or a MOSFET for shutting down. It can be realized with.

According to the twentieth aspect of the present invention, in addition to the effect of the nineteenth aspect, by providing the shut-off MOSFET, the overcharge detection voltage can be further increased when the overcharge detection signal is received. MOSFET according to the input of the overcharge detection signal to the gate when the secondary battery potential is detected
Logic for activating the overdischarge detection signal and the overcurrent detection signal to the hysteresis inverter circuit and prohibiting the generation of the delay signal required for the discharge control for the overdischarge detection signal and the discharge control for the overcurrent detection signal. A hysteresis inverter that performs control and generates a delay signal required for discharge control for activation of a discharge transistor when a secondary battery potential equal to or higher than an overcharge detection voltage is detected while an overcharge detection signal is detected. Logic control for generating a delay signal that is preferentially permitted to the circuit can be executed. As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is not erroneously determined as an overcurrent, and the discharge transistor is activated to supply the load current to the load via the parasitic diode and the discharge transistor. Similarly, a pulse charger is used as a charger, and when a secondary battery potential when an overcurrent with respect to a load current when a load is connected is detected is maintained at or above an overcharge detection voltage. By using a hysteresis inverter circuit or a shut-off MOSFET that can logically control the discharge control function that supplies the load current to the load while avoiding the inactivation of the discharge transistor due to erroneous determination of an overcurrent state, It can be realized with a small circuit scale and a circuit form suitable for integration.

According to the twenty-first aspect of the present invention, in addition to the effect of the fifteenth or twentieth aspect, the blocking MOSF
By providing the ET, when the overcharge detection signal is received and the secondary battery potential equal to or higher than the overcharge detection voltage is detected, the shutoff M is input in response to the input of the overcharge detection signal to the gate.
Activate the OSFET to block the charge accumulation in the timing capacitor of the overdischarge detection signal and the overcurrent detection signal and prohibit the discharge control of the overdischarge detection signal and the generation of the delay signal required for the discharge control of the overcurrent detection signal. Hysteresis is applied to the generation of the delay signal required for the discharge control for activating the discharge transistor when the secondary battery potential that is equal to or higher than the overcharge detection voltage is detected while executing the logic control and detecting the overcharge detection signal. Logic control for generating a delay signal that is preferentially permitted to the inverter circuit can be executed. As a result, even when the load current is equal to or higher than the overcharge detection voltage, the load current when the load is connected is not erroneously determined as an overcurrent, and the discharge transistor is activated to supply the load current to the load via the parasitic diode and the discharge transistor. Similarly, a pulse charger can be used as a charger, and when a secondary battery potential when an overcurrent with respect to a load current at the time of load connection is detected is held at or above an overcharge detection voltage. Even if there is a hysteresis inverter circuit that can logically control the discharge control function of supplying the load current to the load by avoiding that the discharge transistor is deactivated due to erroneous determination based on the potential of the timing capacitor due to the overcurrent state, The use of the blocking MOSFET makes it possible to realize a small circuit scale and a circuit form suitable for integration.

According to the twenty-second aspect of the present invention, in addition to the effect of the twenty-first aspect, a capacitor potential according to charge accumulation in a timing capacitor using an overdischarge detection signal and an overcurrent detection signal is provided. Compared with the threshold level when the input voltage rises in the rising hysteresis circuit, a delay signal that deactivates the discharge transistor when the capacitor potential exceeds the threshold level when the input voltage rises can be generated. A delay signal that activates the discharge transistor can be generated when the input voltage in the hysteresis circuit is lower than the threshold level when the input voltage rises. As a result, it is possible to generate a delay signal having hysteresis characteristics that can be specified by the input voltage threshold level at the time of rising and the input voltage threshold level at the time of falling. By providing such a hysteresis characteristic to the delay signal, it becomes possible to realize an oscillation prevention function at the time of overcurrent detection, and the oscillation of the discharge transistor that controls the discharge current using the delay signal at the time of overcurrent detection. The prevention function can be realized. Furthermore, by providing a hysteresis inverter circuit, such a circuit configuration is simpler than that of a comparator with a latch function, and a compact circuit size, a small chip area, and low power consumption with reduced consumption of secondary batteries prevent such oscillation. An overcurrent detection circuit having a function can be realized.

According to the twenty-third aspect of the present invention, in addition to the effect of any one of the tenth to twenty-second aspects, the battery voltage of the secondary battery is provided by providing the above-described charge / discharge protection circuit. Even if the voltage falls below the operable voltage, the function to prevent oscillation when overcurrent is detected can be realized, the function to execute reliable discharge control using the discharge transistor can be realized, and the reliable charge control can be charged. Function to be performed using the transistor for use. Further, by providing such a charge / discharge protection circuit, the circuit configuration is simpler than that of the comparator with a latch function, and the power consumption is reduced with a compact circuit size, a small chip area, and reduced consumption of the secondary battery. A battery pack having such a charge / discharge control function and an oscillation prevention function can be realized.

According to the twenty-fourth aspect of the present invention, in addition to the effect of the twenty-third aspect, a logical operation of a discharge signal which is a logical product of a logical value of a delay signal and a logical value of a short-circuit detection signal. Is executed, and the conduction state of the discharge current supplied from the battery cell to the load can be controlled using the discharge transistor while monitoring the overdischarge state and the short circuit state according to the logical value of the operation result.

According to the twenty-fifth aspect of the present invention, in addition to the effect of the twenty-fourth aspect, by providing such a level shift circuit in the charge / discharge protection circuit, the battery voltage of the secondary battery can be improved. Even if the voltage falls below the operable voltage, the connection of the charger realizes the above-mentioned oscillation prevention function at the time of overcurrent detection, and at the same time, executes the function of executing reliable charging control using the charging transistor. This makes it possible to generate a charge control signal for realizing this. Furthermore, such a level shift circuit has a simpler circuit configuration than a comparator with a latch function and a compact circuit scale.
This contributes to realizing a battery pack having such a charge / discharge control function and an oscillation prevention function with a small chip area and low power consumption with reduced consumption of a secondary battery.

[Brief description of the drawings]

FIG. 1 is a functional block diagram illustrating a configuration of a charge / discharge protection circuit for a secondary battery and a battery pack using the same according to the present invention.

FIG. 2 is a circuit diagram for explaining a circuit configuration of a hysteresis inverter circuit.

FIG. 3 is a graph for explaining an operation of setting an input voltage threshold level when an input voltage of a first-stage inverter circuit in a hysteresis inverter circuit rises.

FIG. 4 is a graph for explaining an operation of setting an input voltage threshold level when detecting a short circuit of a first-stage inverter circuit in a hysteresis inverter circuit.

FIG. 5 is a circuit diagram for explaining a first embodiment of a circuit configuration of a short circuit detection circuit having an inverter circuit, an overcurrent detection circuit, and a delay circuit having an inverter circuit in the charge / discharge protection circuit of FIG. 1; .

FIG. 6 is a circuit diagram for explaining a second embodiment of a circuit configuration of a short-circuit detection circuit having a hysteresis inverter circuit, an overcurrent detection circuit, and a delay circuit having a hysteresis inverter circuit in the charge / discharge protection circuit of FIG. It is.

FIG. 7 is a graph for explaining an operation of preventing overcurrent from being detected when a battery pack is connected to a charger and when a load is connected, using the charge / discharge protection circuit of FIG. 6; 7) shows a change in the potential of the secondary battery, and FIG.
FIG. 7B shows a change in the ground potential of the charger, and FIG.
7D shows a change in the potential of the charge signal output terminal, FIG. 7D shows a change in the potential of the node a (input terminal of the hysteresis inverter circuit), and FIG. 7E shows a change in the potential of the discharge signal output terminal. It is a graph of.

FIG. 8 is a circuit block diagram for explaining a conventional charge / discharge control circuit.

FIG. 9 is a circuit diagram illustrating a charger connection detection circuit that can reliably output a logical value H to a charging signal output terminal by connecting a charger even when the battery voltage becomes 0V.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Battery pack 12 ... Secondary battery (battery cell, lithium ion battery) 12a ... Charge / discharge signal 14 ... Charger (load) 20 ... Charge / discharge protection circuit 22 ... Overcharge detection circuit 22a ... Overcharge detection signal 23 ... Level Shift circuit 23a ... Charge control signal 24 ... Short circuit detection circuit 24a ... Short circuit detection signal 25 ... Overcurrent detection circuit 25a ... Overcurrent detection signal 26 ... Delay circuit 26a ... Delay signal 26b ... Discharge signal 27 ... Overdischarge detection circuit 27a ... Over Discharge detection signal 30 ... Hysteresis inverter circuit C1 ... Delay capacitor C2 ... Timing capacitor Cout ... Charge signal output terminal Dout ... Discharge signal output terminal nVth ... N-channel MOSFE of falling hysteresis circuit
T threshold level pVth ... p-channel MOSFE of rising hysteresis circuit
Threshold level of T Q1 ... Discharge transistor Q2 ... Charge transistor Q3 ... Enhancement type p-channel transistor Q4 ... Depletion type n-channel transistor Q26 ... Hysteresis inverter circuit Q26A ... Inverter circuit Q31 ... Hysteresis inverter circuit Q36 ... Cutting MOSFET Q41: rising hysteresis resistance element Q42: first p-channel MOSFET Q43: first n-channel MOSFET Q44: falling hysteresis resistance element Q45: p-channel MOSFET of rising hysteresis circuit Q46: n-channel MOSFET of falling hysteresis circuit Q47: second p-channel MOSFET Q48 ... Second n-channel MOSFET V-: Charger ground potential VDD: Secondary battery potential Vss: Battery ground potential Vth: Threshold level VtH: Input when rising Pressure threshold level VtL ... input voltage threshold level at the time of descent

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI // H01M 10/44 H01M 10/44 P

Claims (25)

[Claims] 1. A first p-channel M connected to a power supply potential
OSFET and first n-channel MO connected to ground potential
A first-stage inverter circuit in which an SFET is connected in series with a gate as a common input and a drain as a common output,
A second-stage inverter circuit in which a second p-channel MOSFET connected to the power supply potential and a second n-channel MOSFET connected to the ground potential are connected in series with a gate as a common input and a drain as a common output; A rising-hysteresis circuit connected between the first-stage inverter circuit and a channel MOSFET, the rising-hysteresis circuit for setting an input voltage threshold level when the input voltage of the first-stage inverter circuit rises; A falling hysteresis circuit for setting an input voltage threshold level when the input voltage of the circuit falls. 2. When the input voltage of the first-stage inverter circuit rises, the first p-channel MOSFET is connected to a power supply potential via the activated rising hysteresis circuit, and the deactivated falling hysteresis circuit is activated. 2. The hysteresis inverter circuit according to claim 1, wherein the first n-channel MOSFET is connected to a ground potential via the first hysteresis resistor and a falling hysteresis resistor. 3. When the input voltage of the first-stage inverter circuit falls, the first p-channel MOSFET is connected to a power supply potential via the deactivated rising hysteresis circuit and the rising hysteresis resistance element, and is activated. 3. The hysteresis inverter circuit according to claim 1, wherein said first n-channel MOSFET is connected to a ground potential via said falling hysteresis circuit. 4. The hysteresis inverter circuit according to claim 3, wherein said rising hysteresis circuit comprises a p-channel MOSFET and said rising hysteresis resistance element connected in parallel. 5. The hysteresis inverter circuit according to claim 3, wherein said falling hysteresis circuit comprises an n-channel MOSFET and said falling hysteresis resistance element connected in parallel. 6. The first-stage inverter circuit according to claim 1, wherein:
The rising hysteresis circuit is connected in parallel between the source of the p-channel MOSFET and the power supply potential, and between the source of the first n-channel MOSFET and the ground potential between the source of the first n-channel MOSFET and the ground potential. 4. The hysteresis inverter circuit according to claim 1, wherein a falling hysteresis circuit is connected in parallel. 7. A common input of the second-stage inverter circuit is connected to a common output of the first-stage inverter circuit, and a common output of the second-stage inverter circuit is a gate of a p-channel MOSFET of the rising hysteresis circuit and an n-channel of the falling hysteresis circuit. In a circuit configuration in which a logic value opposite to the logic value output from the first-stage inverter circuit is connected to the gate of the MOSFET and output from the second-stage inverter circuit, the rising edge of the logic value voltage input to the first-stage inverter circuit The first p-channel MOSFET is connected to the power supply potential via the p-channel MOSFET of the rising hysteresis circuit activated in response to the rising hysteresis circuit, and the falling hysteresis circuit is connected to the rising edge of the logical value input to the first-stage inverter circuit. N channel MOSF
7. The hysteresis inverter circuit according to claim 6, wherein the first n-channel MOSFET is connected to a ground potential via the falling hysteresis resistance element when ET is inactivated. 8. The threshold value of the rising hysteresis circuit when an input voltage rises is set based on a difference between a threshold level of the first p-channel MOSFET and a power supply potential.
The hysteresis inverter circuit according to claim 3, 4, 6, or 7. 9. The system according to claim 2, wherein a threshold level of the falling hysteresis circuit when the input voltage falls is set based on a sum of a threshold level of the first n-channel MOSFET and a ground potential.
The hysteresis inverter circuit according to claim 3, claim 5, claim 6, or claim 7. 10. An overcharge state of a secondary battery during charging control for controlling a charging transistor provided between the secondary battery and a load to supply a charging current to the secondary battery, and the secondary battery and the load. To detect the over-discharge state of the secondary battery at the time of discharge control or the over-current state of the secondary battery at the time of discharge control by controlling the discharging transistor provided between In a charge / discharge protection circuit that protects a secondary battery from an overcharged state, an overdischarged state, or an overcurrent state, when the overcharged state is reached and the secondary battery potential is higher than the overcharge detection voltage, the battery is connected to the load. A charge / discharge protection circuit comprising a delay circuit for executing discharge control for activating a discharging transistor and supplying a load current to a load. 11. An overcharged state of the secondary battery during charge control for controlling a charging transistor provided between the secondary battery and the load to supply a charging current to the secondary battery, and the secondary battery and the load. To detect the over-discharge state of the secondary battery at the time of discharge control or the over-current state of the secondary battery at the time of discharge control by controlling the discharging transistor provided between In a charge / discharge protection circuit that protects a secondary battery from an overcharged state, an overdischarged state, or an overcurrent state, when the overcharged state is reached and the secondary battery potential is further higher than the overcharge detection voltage, the battery is connected to the load. In addition to activating the discharging transistor, the discharging control for supplying the load current to the load through the parasitic diode existing in parallel between the drain and the source of the charging transistor and the discharging transistor in the activated state is performed. Discharge protection circuit and having a delay circuit for. 12. The delay circuit generates a delay signal for detecting an overdischarge state in a secondary battery in accordance with the overdischarge detection signal and setting a delay time required to execute discharge control. In addition, a delay signal for setting a delay time required to execute a discharge control by detecting an overcurrent state in the secondary battery in accordance with the overcurrent detection signal is generated, and the overcharge detection signal is detected. In the state, it is more than the overcharge detection voltage.
When detecting the potential of the next battery, it instructs cancellation of the discharge control according to the overdischarge state and cancellation of the discharge control according to the overcurrent state, and activates the discharge transistor connected to the load to charge the battery. A circuit configuration for generating a delay signal for instructing discharge control for supplying a load current to a load via a parasitic diode existing in parallel between the drain and source of the transistor and the activated discharging transistor. The charge / discharge protection circuit according to claim 10 or 11, wherein: 13. The discharge circuit according to claim 1, wherein the delay circuit detects the overcharge detection signal and discharges the overdischarge detection signal and the overcurrent detection signal when further detecting a secondary battery potential equal to or higher than the overcharge detection voltage. 13. The circuit according to claim 10, further comprising a circuit configured to activate a discharge transistor connected to the load prior to the control instruction and execute a discharge control instruction to supply a load current to the load. A charge / discharge protection circuit according to claim 1. 14. The delay circuit, comprising: a gate circuit for generating a delay signal according to the overdischarge detection signal or a delay signal according to the overcharge detection signal; and further detecting overcharge in a state where the overcharge detection signal is received. In response to an overcharge detection signal when a secondary battery potential equal to or higher than a voltage is detected, the overdischarge detection signal and the overcurrent detection signal are interrupted to delay the overdischarge detection signal or the overcharge detection signal Control for inhibiting the generation of the delay signal according to
14. The charge / discharge according to claim 13, having a circuit configuration for executing control for instructing generation of the delay signal for activating a discharge transistor connected to a load to the gate circuit. Protection circuit. 15. An over-discharge detection signal and an over-charge detection signal according to an input to a gate of the over-charge detection signal when a rechargeable battery potential equal to or higher than an over-charge detection voltage is detected while receiving the over-charge detection signal. A logic signal for blocking the input of the overcurrent detection signal to the gate circuit and prohibiting the generation of the delay signal is output to the gate circuit, and the generation of the delay signal for activating the discharge transistor is performed. Interruption MOS that outputs a designated logic signal to the gate circuit
The charge / discharge protection circuit according to claim 14, further comprising an FET. 16. An overcharged state of the secondary battery during charge control,
Detects the over-discharge state of the secondary battery during discharge control that supplies load current or the over-current state of the secondary battery during discharge control to protect the secondary battery from over-charge, over-discharge, or over-current. A charge / discharge protection circuit that is connected to the secondary battery potential, monitors the discharge state of the secondary battery, and generates an overdischarge detection signal when the overdischarge state is detected; An overcurrent detection circuit that is connected to the potential, monitors the potential of the charger ground potential, and generates an overcurrent detection signal when an overcurrent state is detected, and is connected to the secondary battery potential to reduce the battery ground potential. A level shift circuit that shifts to a charger ground potential to generate a charge control signal; and the delay circuit includes the hysteresis inverter circuit, and generates an overdischarge state in the secondary battery in response to the overdischarge detection signal. A delay signal for setting a delay time required for detecting the state of the battery through the hysteresis inverter circuit, and a delay required for detecting an overcurrent state in the secondary battery in response to the overcurrent detection signal. 10. A delay circuit for generating a delay signal for setting a time via said hysteresis inverter circuit.
A charge / discharge protection circuit using the hysteresis inverter circuit according to any one of the above. 17. A delay circuit that generates a delay signal according to the overdischarge detection signal or a delay signal according to the overcharge detection signal; and a further overcharge when the overcharge detection signal is received. The overdischarge detection signal and the overcurrent detection signal are cut off in response to an overcharge detection signal when a secondary battery potential equal to or higher than the detection voltage is detected, and a delay signal related to the overdischarge detection signal or the overcharge detection is performed. A control for inhibiting generation of a delay signal according to the signal is performed on the hysteresis inverter circuit, and a control for instructing generation of the delay signal for activating a discharge transistor connected to a load is performed on the hysteresis inverter circuit. 17. The charging / discharging device according to claim 16, wherein the charging / discharging device has a circuit configuration to be executed for an inverter circuit. Protection circuit. 18. The delay circuit includes the hysteresis inverter circuit, and detects the overdischarge state in the secondary battery in response to the overdischarge detection signal and converts the delay signal for executing the discharge control to the hysteresis inverter circuit. The delay signal is generated through an inverter circuit, and the delay signal for executing the discharge control by detecting an overcurrent state in the secondary battery according to the overcurrent detection signal is generated through the hysteresis inverter circuit. When the overcharge detection signal is detected and the secondary battery potential that is equal to or higher than the overcharge detection voltage is detected, the discharge transistor connected to the load is activated and the drain-source of the charge transistor is activated. To supply a load current to a load via a parasitic diode existing in parallel with the Discharge protection circuit according to claim 16, characterized in that it comprises a circuit arrangement for executing control. 19. The delay circuit has a gate circuit for generating the delay signal, and the gate circuit further detects a secondary battery potential equal to or higher than an overcharge detection voltage while receiving the overcharge detection signal. At this time, the control to cut off the overdischarge detection signal and the overcurrent detection signal is executed for the hysteresis inverter circuit, and the delay signal for instructing activation of the discharge transistor connected to the load is generated. 18. A circuit configuration for performing the control to be performed on the hysteresis inverter circuit.
9. The charge / discharge protection circuit according to 8. 20. In response to the input of an overcharge detection signal to a gate when a secondary battery potential equal to or higher than an overcharge detection voltage is detected while receiving the overcharge detection signal, the overdischarge detection signal and A logic signal for interrupting the input of the overcurrent detection signal to the gate circuit and inhibiting the generation of the delay signal is output to the hysteresis inverter circuit, and the generation of the delay signal for activating the discharge transistor is performed. 20. The charge / discharge protection circuit according to claim 19, further comprising: a shut-off MOSFET that outputs a logic signal designating to the hysteresis inverter circuit. 21. The delay circuit sets a delay time required to execute a discharge control according to the overdischarge detection signal and a delay time required to execute a discharge control according to the overcurrent detection signal. A timing capacitor connected to the input of the hysteresis inverter circuit, and the shut-off MOSFET is connected in parallel to the timing capacitor with respect to the input of the hysteresis inverter circuit to receive the overcharge detection signal. In response to the input of the overcharge detection signal to the gate when the secondary battery potential that is equal to or higher than the overcharge detection voltage is further detected in the state, the signal is accumulated in the timing capacitor by the overdischarge detection signal or the overcurrent detection signal. 16. A circuit for short-circuiting a charge. Discharge protection circuitry includes other described 20. 22. The hysteresis inverter circuit,
When the potential of the timing capacitor is equal to or higher than a threshold level at the time of rising of the input voltage in the rising hysteresis circuit, the delay signal for inactivating the discharging transistor is generated, and the potential of the timing capacitor is changed to the input voltage in the rising hysteresis circuit. 22. The charge / discharge protection circuit according to claim 21, further comprising a circuit configuration for generating the delay signal that activates the discharge transistor when the threshold level is lower than a rising threshold level. 23. In addition to the charge / discharge protection circuit, a battery cell as a secondary battery, and a discharge current that is connected in series between a load and the battery cell and is supplied from the battery cell to the load during discharge control A discharge transistor for controlling the conduction state of the battery according to the logic value of the delay signal; a discharge transistor connected in series between a charger and the battery cell, for supplying a charging current supplied from the charger to the battery cell during charge control. A charging transistor for controlling a state according to a logical value of the charge control signal; and a charge / discharge signal connected to a battery ground potential for setting a delay time required for detecting an overcharge state in the battery cell. 3. A delay capacitor for generating and transmitting the signal to the overcharge detection circuit. Battery pack with the charge and discharge protection circuit according to any one of. 24. A discharge current supplied from the battery cell to a load according to a logical value of a discharge signal, which is a logical product of a logical value of the delay signal and a logical value of the short-circuit detection signal. 24. The battery pack according to claim 23, wherein the battery pack is configured to control an energized state of the battery pack. 25. A level shift circuit for generating the charge control signal having a logic value for activating the charging transistor when activated in accordance with a charger ground potential. The battery pack described in.