JPH1167892A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the deterioration of an element characteristic, by forming an element separation insulating film which covers the side wall of an element separation groove and protrudes from the surface of an element forming area on the element separation insulating film which is buried to the middle of the element separation groove. SOLUTION: A buried oxidized film 5 is formed on the whole face and it is etched until the upper side wall of a trench groove is exposed. The upper corner of the element forming area is exposed. A polycrystalline silicon film 6 is formed on the whole face. Then, a silicon nitride film 3 and the unnecessary polycrystalline silicon film 6 on the buried oxide film 5 are removed, so that the polycrystalline silicon film 6 on the boundary of the element forming area and the trench groove does not come under the element forming area. The polycrystalline silicon film 6 is oxidized by a thermal oxidizing method and it is changed to the silicon oxide film 6a. Thus, the upper corner part of the element forming area is covered by the silicon oxide film 6a, and it can prevent the upper side wall of the trench groove from being exposed when removing the buffer oxide film 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device using trench type element isolation and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, large-scale integrated circuits (ICs) formed by integrating a large number of transistors, resistors, and the like into an important part of a computer or a communication device so as to achieve an electric circuit are integrated on one chip. LSI) is frequently used. For this reason, the performance of the entire device is greatly related to the performance of the LSI alone. The performance of the LSI alone can be improved by miniaturizing the element and increasing the degree of integration.

On the other hand, conventionally, element isolation has been performed by LOCOS element isolation, which is one of local oxidation methods.
In this element isolation, an oxide film called bird's beak is formed in the element formation region, and the effective area of the element formation region is reduced. Therefore, LOCOS element isolation is not effective for high integration.

Therefore, recently, a shallow trench groove (element isolation groove) is formed on the substrate surface, and the shallow trench groove is filled with an insulating film.
lation) is increasingly used. Unlike the LOCOS element isolation, this element isolation does not cause bird's beaks, so that a reduction in the element formation region can be prevented, which is effective for high integration.

However, STI has the following problems. This problem will be specifically described with an example in which a MOS transistor is formed in an element formation region. FIG.
FIG. 1 shows a process sectional view of a method for forming a MOS transistor in an element formation region by performing element isolation by STI.

First, as shown in FIG. 11A, a surface of a silicon substrate 91 is thermally oxidized to form a buffer oxide film 92. Next, as shown in FIG. 3A, after a silicon nitride film 93 is formed on the buffer oxide film 92, a resist turn 94 is formed on the silicon nitride film 93.

Next, as shown in FIG. 11B, the silicon nitride film 93 is etched using the resist pattern 94 as a mask, and the pattern of the resist pattern 94 is transferred to the silicon nitride film 93. This silicon nitride film 93 is also used as a mask pattern similarly to the resist pattern 94. Thus, even if the resist pattern 94 disappears during the etching, the pattern is transferred to the base as long as the silicon nitride film 93 exists.

Next, as shown in FIG. 1B, using the silicon nitride film 93 and the resist pattern 94 as a mask, the buffer oxide film 92 and the silicon substrate 91 are sequentially etched to form a shallow trench groove in the surface of the silicon substrate 91. To form a plurality of island-shaped element formation regions. After that, the resist pattern 94 is peeled off.

The etching in the step of FIG. 11B includes, for example, reactive ion etching (Reactive).
e Ion Etching (RIE) is used. Next, as shown in FIG. 11C, a buried oxide film 94 is formed on the entire surface.
After an oxide film is deposited and the trench is filled, the oxide film is subjected to chemical mechanical polishing (Chemical Me).
After planarization is performed using a mechanical polishing (CMP) method, the buffer oxide film 92 and the silicon nitride film 93 are removed.

Next, as shown in FIG. 11D, after a gate oxide film 95 is formed on the substrate surface in the element region, a gate electrode 96 is formed. Thereafter, the well-known MOS transistor manufacturing method is followed.

In this conventional manufacturing method, when the buffer oxide film 92 is removed in the step of FIG. 11C, the buried oxide film 95 in the upper corner portion of the trench is also removed, and the upper sidewall of the trench is exposed. Resulting in. In other words, the upper corner portion of the element formation region is exposed. Therefore, FIG.
In the step 1 (d), the gate electrode 96 is provided on the exposed portion via the gate oxide film 95.

As a result, an electric field formed by applying a gate voltage to the gate electrode 96 is concentrated on the upper corner portion of the element-shaped region, whereby the gate withstand voltage is reduced and the sub-threshold characteristics are kinked. There is a problem that the electrical characteristics of the MOS transistor are significantly deteriorated, for example, the occurrence of a hump or the like.

[0013]

As described above, after forming the STI structure by providing the buffer oxide film on the substrate surface and then forming the MOS transistor after removing the buffer oxide film, the upper part of the element type region is formed. Since the corner portion is exposed and the gate electrode is disposed on the exposed portion via the gate oxide film, when a voltage is applied to the gate electrode, an electric field is concentrated on the exposed portion, and the electrical characteristics of the MOS transistor are reduced. There has been a problem of significant deterioration.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a groove-type element isolation structure capable of preventing deterioration of element characteristics.

Further, according to the present invention, after an insulating film is provided on a substrate surface to form a groove-type element isolation structure, the above-mentioned insulating film is removed, and then the boundary between the element formation region and the element isolation region is straddled. It is an object of the present invention to provide a method for manufacturing a semiconductor device having a groove-type element isolation structure capable of preventing deterioration of element characteristics even when a conductive film is formed on an element formation region.

[0016]

[Means for Solving the Problems]

[Structure] To achieve the above object, a semiconductor device according to the present invention (claim 1) has an element isolation region in which an element isolation insulating film is embedded in an element isolation groove formed on a surface of a semiconductor substrate. And a first element isolation insulating film in which the element isolation insulating film is buried to a depth halfway in the element isolation groove. Formed on the first element isolation insulating film so as to cover a side wall of the element isolation groove,
And a second element isolation insulating film protruding from a surface of the element formation region on a boundary between the element formation region and the element isolation groove.

Further, another semiconductor device according to the present invention (claim 2) is the semiconductor device (claim 1) in which the element formation region extends over a boundary between the element formation region and the element isolation region. A conductive film is formed over the region.

Further, another semiconductor device according to the present invention (Claim 3) is characterized in that, in the semiconductor device (Claim 2), the conductive film is a gate electrode. Another semiconductor device according to the present invention (claim 4) is characterized in that, in the semiconductor device (claim 1), the first element isolation insulating film is an insulating film containing impurities.

Further, in another semiconductor device according to the present invention (claim 5), in the semiconductor device (claim 1), the second element isolation insulating film is a silicon oxide film or a silicon nitride film. It is characterized by.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on a semiconductor substrate; and forming an element isolation groove on the first insulating film. Forming a mask pattern, etching the first insulating film and the semiconductor substrate using the mask pattern as a mask, forming an element isolation groove on a surface of the semiconductor substrate, and forming a plurality of island-shaped element formation regions. Forming a first and a first
Embedding a second insulating film as an element isolation insulating film to a depth in the middle of the element isolation groove, and forming an insulating film to be a second element isolation insulating film on the entire surface so that the element isolation groove is embedded. Forming a non-insulating film that can be converted, and the non-insulating film on the boundary between the element forming region and the element isolation groove is not below the surface of the element forming region, Removing the non-insulating film, forming the second element isolation insulating film by insulating the non-insulating film, and removing the first insulating film and the mask pattern. And

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein the mask pattern on a corner portion of the element formation region is removed. After that, the non-insulating film is formed.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein the mask pattern is formed from a silicon nitride film, and the non-insulating film is formed. Is a polycrystalline silicon film.

Here, an amorphous silicon film may be used as the non-insulating film. The non-insulating film on the mask pattern is removed by, for example, a reactive ion etching method or a chemical mechanical polishing method.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention, wherein the non-insulating film is insulated from the second semiconductor device.
Removing the mask pattern after forming the insulating film, and forming a gate insulating film on the device forming region, and then crossing a boundary between the second device isolation insulating film and the device forming region. Forming a gate electrode on the gate insulating film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on a semiconductor substrate; and forming an element isolation groove on the first insulating film. Forming a mask pattern for use as a mask, etching the first insulating film and the semiconductor substrate using the mask pattern as a mask, forming element isolation grooves on the surface of the semiconductor substrate, and forming a plurality of island-shaped elements. Forming a formation region;
A step of burying a second insulating film as a first element isolation insulating film to a depth in the middle of the element isolation groove; and forming a second element isolation insulating film on the entire surface so that the element isolation groove is embedded. Forming a third insulating film on the mask pattern so that the third insulating film on the boundary between the element forming region and the element isolation groove does not fall below the surface of the element forming region. Removing the third insulating film, and removing the first insulating film and the mask pattern.

Here, the removal of the third insulating film on the mask pattern is performed by, for example, a reactive ion etching method or a chemical mechanical polishing method. According to another aspect of the present invention, there is provided a method of manufacturing another semiconductor device.
3) In the method of manufacturing a semiconductor device (claim 11), the third insulating film on the mask pattern is removed by using a reactive ion etching method or a chemical mechanical polishing method. .

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the present invention.
Removing the mask pattern after removing the insulating film, and forming a gate insulating film on the element formation region, and then crossing a boundary between the second element isolation insulating film and the element formation region. Forming a gate electrode on the gate insulating film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on a semiconductor substrate; and forming an element isolation groove on the first insulating film. Forming a mask pattern for use as a mask, etching the first insulating film and the semiconductor substrate using the mask pattern as a mask, forming element isolation grooves on the surface of the semiconductor substrate, and forming a plurality of island-shaped elements. Forming a formation region;
A step of burying a second insulating film as a first element isolation insulating film to a depth in the middle of the element isolation groove, a step of removing the mask pattern on an upper corner portion of the element region, and a step of removing the mask Selectively forming an insulative non-insulating film serving as a second element isolation insulating film on the upper corner portion of the element region from which the pattern has been removed; A step of forming an element isolation insulating film; and a step of removing the first insulating film and the mask pattern.

Such a non-insulating film can be formed by using, for example, an epitaxial growth method.
6). The mask pattern may be, for example, a silicon nitride film, and the non-insulating film may be, for example, a single crystal silicon film formed by an epitaxial growth method.

According to the present invention (claim 1), the element isolation insulating film has a first element isolation insulating film buried to a depth in the middle of the element isolation groove, and the first element isolation insulating film is formed on the first element isolation insulating film. Is formed by the second element isolation insulating film formed on the substrate.

Here, the second element isolation insulating film is formed so as to cover the side wall of the element isolation groove, and protrudes from the surface of the element formation area on the boundary between the element formation area and the element isolation groove. The upper side wall of the isolation trench is
Is surely covered with the element isolation insulating film.

For this reason, a conductive film is formed on the element formation region so as to cross the boundary between the element formation region and the element isolation region (Claim 2), and a voltage is applied to the conductive film. The electric field does not concentrate on the upper corner portion of the element formation region.

Therefore, according to the present invention, it is possible to prevent the deterioration of the device characteristics due to the electric field concentration in the corner portion of the device forming region when the trench type device isolation is used. Even when such an element isolation groove needs to be formed with an insulating film to be removed in a later step like the first insulating film, the manufacturing method of the present invention (claims 6, 11 and 15) can be used. It can be formed without exposing the upper corner portion of the element formation region.

Further, according to the present invention (claim 3), since the electric field concentration at the upper corner portion of the element formation region can be prevented, the gate withstand voltage is reduced, the kink is generated in the sub-threshold characteristic, the hump is suppressed. MO such as occurs
Deterioration of the electrical characteristics of the S transistor can be prevented.

Further, by dividing the element isolation insulating film into a first element isolation insulating film and a second element isolation insulating film (claims 4, 5, 8, and 12), the present invention (claim 1) The groove-type element isolation structure can be easily manufactured. The first element isolation insulating film is an insulating film similar to the conventional element isolation insulating film, and thus, the buried isolation can be performed as in the related art. The second element isolation insulating film is selected to be suitable for manufacturing the groove-type element isolation structure of the present invention (claim 1).

Further, according to the present invention (claims 6, 11 and 15), the upper side wall of the trench is covered with the second element isolation insulating film which is higher than the surface of the element formation region. Even if the first insulating film is removed after the formation of the second element isolation insulating film, the upper side wall of the trench (the upper corner portion of the element formation region) is hardly exposed. Therefore, it is possible to prevent the upper side wall of the trench from being exposed when the previously formed second insulating film is removed.

Further, after removing the mask pattern on the corner portion of the element type region, the non-insulating film is formed (claim 7), whereby the non-insulating film is insulated to form the second element isolation insulating film. When forming, a bird's beak in the upper corner portion of the element formation region can be suppressed, and the stress applied to the semiconductor substrate can be reduced.

[0038]

Embodiments of the present invention (hereinafter, referred to as embodiments) will be described below with reference to the drawings. (First Embodiment) FIGS. 1 and 2 are process sectional views showing a method for forming an STI and a MOS transistor according to a first embodiment of the present invention.

First, as shown in FIG. 1A, a buffer oxide film 2 having a thickness of about 10 nm is formed on the surface of a single-crystal silicon substrate 1 by thermal oxidation. A silicon nitride film 3 having a thickness of about 1000 nm is formed using, for example, the LP-CVD method.

Next, as shown in FIG. 1B, after forming a resist pattern 4 on the silicon nitride film 3, the silicon nitride film 3 is etched using the resist pattern 4 as a mask to form a pattern of the resist pattern 4. Is transferred to the silicon nitride film 3. For this etching, for example, RIE is used.

This silicon nitride film 3 is also used as a mask pattern like the resist pattern 4. Thereby, even if the resist pattern 4 disappears during the etching, the pattern remains as long as the silicon nitride film 3 exists.
It will be transferred to the base.

Next, as shown in FIG. 2B, the buffer oxide film 2 and the silicon substrate 1 are etched using the resist pattern 4 and the silicon nitride film 3 as a mask to form shallow trenches, and a plurality of island-shaped trenches are formed. Is formed. For this etching, for example, RIE is used.

Next, as shown in FIG. 1C, after the resist pattern 4 is removed, a buried oxide film 5 is formed on the entire surface, and after the trench is buried, the surface of the buried oxide film 5 is subjected to CMP. Substantially flatten.

Next, as shown in FIG. 1D, the entire surface of the buried oxide film 5 is etched until the upper side wall of the trench is exposed. At this time, the buffer oxide film 2 near the upper corner of the trench is also etched, exposing the upper corner of the element-shaped region.

Next, as shown in FIG. 2E, a polycrystalline silicon film 6 having a thickness of about 1000 nm is formed on the entire surface by a CVD method. Next, as shown in FIG. 2 (f), the entire surface of the polycrystalline silicon film 6 is subjected to RIE (so-called side wall remains), so that only the buffer oxide film 2, the silicon nitride film 3 and the polycrystalline silicon The film 6 is left selectively.

That is, unnecessary polycrystalline silicon on silicon nitride film 3 and buried oxide film 5 is maintained so that polycrystalline silicon film 6 on the boundary between the element forming region and the trench groove does not become lower than the surface of the element forming region. The film 6 is removed.

Next, as shown in FIG. 2 (g), the polycrystalline silicon film 6 is oxidized by a thermal oxidation method.
Is changed to a silicon oxide film 6a. As a result, the upper corner portion of the element formation region is covered with the silicon oxide film 6a. Also, the buried oxide film 5 can be densified by the thermal acid step at this time, and the subsequent densifying step can be omitted.

Next, as shown in FIG. 2H, after removing the silicon nitride film 3 and the buffer oxide film 2, a gate oxide film 7 and a gate electrode 8 are formed on the element formation region. Here, since the upper side wall of the trench is covered with the silicon oxide film 6a higher than the surface of the element formation region, the upper side wall of the trench is prevented from being exposed when the buffer oxide film 2 is removed. it can.

Thereafter, the well-known MOS transistor manufacturing method is followed. That is, n-type impurity ions such as As ions are implanted into the element region using the gate electrode 8 as a mask to form n-type source / drain regions in a self-aligned manner, and then an interlayer insulating film is deposited. Then, a contact hole is opened to form a source / drain electrode (wiring) and a gate wiring.

In the present embodiment, the side wall of the trench, which is the boundary with the element formation region, is covered with the buried oxide film 5 and the silicon oxide film 6a and is not exposed. That is, the upper side wall of the trench is covered with the silicon oxide film 6a, and the other side wall is covered with the buried oxide film 5.

For this reason, the gate electrode 8 is formed on the element formation region so as to cross the boundary between the element formation region and the trench (element isolation region). The electric field does not concentrate on the upper corner portion of the formation region.

Therefore, according to the present embodiment, the STI
In the case where is used, it is possible to prevent the deterioration of the electrical characteristics due to the electric field concentration in the upper corner portion of the element formation region. Specifically, for example, it is possible to prevent a reduction in gate breakdown voltage, the occurrence of kink in the sub-threshold characteristics, the occurrence of hump, and the like. (Second Embodiment) FIG. 3 is a process sectional view showing a method for forming an STI and a MOS transistor according to a second embodiment of the present invention. 1 and 2 are denoted by the same reference numerals as in FIGS. 1 and 2, and the detailed description is omitted.

The main difference between this embodiment and the first embodiment is that unnecessary polycrystalline silicon film 6 is removed not by RIE but by CMP. First, following the step of forming the polycrystalline silicon film 6 shown in FIG. 2E of the first embodiment, as shown in FIG. 3A, the silicon nitride film 3 is used as a stopper, The polycrystalline silicon film 6 is planarized by CMP until the upper polycrystalline silicon film 6 disappears. At this time, the polycrystalline silicon film 6
May be slightly lower than the upper surface of the silicon nitride film 3.

Next, as shown in FIG. 3B, the remaining polycrystalline silicon film 6 is oxidized by a thermal oxidation method, and the polycrystalline silicon film 6 is changed to a silicon oxide film 6a. As a result, the upper corner portion of the element formation region is covered with the silicon oxide film 6a. Also, the buried oxide film 5 can be densified by the thermal acid step at this time, and the subsequent densifying step can be omitted.

Next, as shown in FIG. 3C, after removing the silicon nitride film 3 and the buffer oxide film 2, a gate oxide film 7 and a gate electrode 8 are formed on the element formation region. Thereafter, the well-known MOS transistor manufacturing method is followed. That is, n-type impurity ions such as As ions are implanted into the element region using the gate electrode 8 as a mask to form n-type source / drain regions in a self-aligned manner, and then an interlayer insulating film is deposited. Then, a contact hole is opened to form a source / drain electrode (wiring) and a gate wiring.

In this embodiment, the same effects as in the first embodiment can be obtained. (Third Embodiment) FIG. 4 is a process sectional view showing a method for forming an STI and a MOS transistor according to a third embodiment of the present invention. 1 and 2 are denoted by the same reference numerals as in FIGS. 1 and 2, and the detailed description is omitted.

The main difference between the present embodiment and the first embodiment is that the silicon nitride film 3 on the upper corner portion of the element formation region is removed before the polycrystalline silicon film 6 is formed.

First, following the RIE process of the buried oxide film 5 shown in FIG. 1E of the first embodiment, FIG.
As shown in (a), the silicon nitride film 3 is retracted by about 20 nm using hot phosphoric acid. As a result, the silicon nitride film 3 on the upper corner portion of the element formation region is removed, and the buffer oxide film 2 on the upper corner portion is exposed.

Next, as shown in FIG. 4A, after a polycrystalline silicon film 6 having a thickness of about 1000 nm is formed on the entire surface, the entire surface of the polycrystalline silicon film 6 is subjected to RIE, and the The polycrystalline silicon film 6 is selectively left on the upper corner portion of the element formation region.

Next, as shown in FIG. 4B, the polycrystalline silicon film 6 is oxidized by a thermal oxidation method.
Is changed to a silicon oxide film 6a. As a result, the upper corner portion of the element formation region is covered with the silicon oxide film 6a. Also, the buried oxide film 5 can be densified by the thermal acid step at this time, and the subsequent densifying step can be omitted.

Further, since the silicon nitride film 3 at the upper corner portion of the element formation region is removed, bird's beak of the silicon oxide film 6a is suppressed, and the stress applied to the silicon substrate 1 is reduced.

Next, as shown in FIG. 4C, after removing the silicon nitride film 3 and the buffer oxide film 2, a gate oxide film 7 and a gate electrode 8 are formed on the element formation region. Thereafter, the well-known MOS transistor manufacturing method is followed. That is, n-type impurity ions such as As ions are implanted into the element region using the gate electrode 8 as a mask to form n-type source / drain regions in a self-aligned manner, and then an interlayer insulating film is deposited. Then, a contact hole is opened to form a source / drain electrode (wiring) and a gate wiring.

In this embodiment, effects similar to those of the first embodiment can be obtained. Further, according to the present embodiment, bird's beak of the silicon oxide film 6a can be suppressed, and the stress applied to the silicon substrate 1 can be reduced. (Fourth Embodiment) FIG. 5 is a process sectional view showing a method for forming an STI and a MOS transistor according to a fourth embodiment of the present invention. 1 and 2 are denoted by the same reference numerals as in FIGS. 1 and 2, and the detailed description is omitted.

The second embodiment differs from the first embodiment mainly in that the silicon nitride film 3 is removed before the polycrystalline silicon film 6 is oxidized. First, following the RIE step of the polycrystalline silicon film 6 shown in FIG. 2F of the first embodiment, as shown in FIG. 5A, the silicon nitride film 3 is removed using hot phosphoric acid. I do.

Next, as shown in FIG. 5 (b), the polycrystalline silicon film 6 is oxidized by a thermal oxidation method.
Is changed to a silicon oxide film 6a. At this time, since the silicon nitride film 3 does not exist, bird's beak does not occur in the silicon oxide film 6a, and the stress applied to the silicon substrate 1 can be sufficiently reduced. Also, the buried oxide film 5 can be densified by the thermal acid process at this time,
The subsequent densify step can be omitted.

Next, as shown in FIG. 5C, after removing the buffer oxide film 2 and the silicon nitride film 3, a gate oxide film 7 and a gate electrode 8 are formed on the element formation region. Thereafter, the well-known MOS transistor manufacturing method is followed. That is, n-type impurity ions such as As ions are implanted into the element region using the gate electrode 8 as a mask to form n-type source / drain regions in a self-aligned manner, and then an interlayer insulating film is deposited. Then, a contact hole is opened to form a source / drain electrode (wiring) and a gate wiring.

In this embodiment, effects similar to those of the first embodiment can be obtained. Further, according to the present embodiment, since bird's beak does not occur in the silicon oxide film 6a, the stress applied to the silicon substrate 1 can be sufficiently reduced. (Fifth Embodiment) FIGS. 6 and 7 are process sectional views showing a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.

First, as shown in FIG. 6A, a buffer oxide film 12 having a thickness of about 10 nm is formed on the surface of a single-crystal silicon substrate 11 by thermal oxidation. A polycrystalline silicon film 13 having a thickness of about 1000 nm is formed using, for example, a CVD method.

Next, as shown in FIG. 6B, after forming a resist pattern 14 on the polycrystalline silicon film 13, the polycrystalline silicon film 13 is etched using the resist pattern 14 as a mask to form a resist pattern 14. Is transferred to the polycrystalline silicon film 13. For this etching, for example, RIE is used.

This polycrystalline silicon film 13 is also used as a mask pattern similarly to the resist pattern 14. Thus, even if the resist pattern 14 disappears during the etching, the pattern is transferred to the base as long as the polycrystalline silicon film 13 exists.

Next, as shown in FIG. 3B, the buffer oxide film 12 and the silicon substrate 11 are etched using the resist pattern 14 and the polycrystalline silicon film 13 as a mask to form trenches, thereby forming a plurality of islands. Is formed. For this etching, for example, RIE is used.

Next, as shown in FIG. 6C, after the resist pattern 14 is removed, a buried oxide film 15 is formed on the entire surface, and after the trench is filled, the buried oxide film 1 is formed.
The surface of No. 5 is substantially flattened by CMP.

Next, as shown in FIG. 6D, the entire surface of the buried oxide film 15 is etched until the upper side wall of the trench is exposed. At this time, the buffer oxide film 12 near the upper corner portion of the trench is also etched, exposing the upper corner portion of the element region.

Next, as shown in FIG. 7E, a silicon nitride film 16 having a thickness of about 1000 nm is formed on the entire surface by LP-CVD.
It is formed using a method. Next, as shown in FIG. 7F, the silicon nitride film 16 is used as a stopper, and the silicon nitride film 16 is planarized by CMP until the silicon nitride film 16 on the polycrystalline silicon film 13 disappears. At this time, the upper surface of silicon nitride film 16 may be slightly lower than the upper surface of polycrystalline silicon film 13.

Next, as shown in FIG. 7G, the polycrystalline silicon film 13 is selectively removed. Next, as shown in FIG. 7H, after removing the buffer oxide film 12, a gate oxide film 17 and a gate electrode 18 are formed on the element formation region.

Thereafter, the well-known MOS transistor manufacturing method is followed. That is, n-type impurity ions such as As ions are implanted into the element region using the gate electrode 8 as a mask to form n-type source / drain regions in a self-aligned manner, and then an interlayer insulating film is deposited. Then, a contact hole is opened to form a source / drain electrode (wiring) and a gate wiring.

In the present embodiment, the side wall of the trench, which is the boundary with the element formation region, is covered with the buried oxide film 15 and the silicon nitride film 16 and is not exposed. That is, the upper corner portion of the element formation region is covered with the silicon oxide film 16, and the other portions are covered with the buried oxide film 15.

For this reason, the gate electrode 18 is formed on the element formation region so as to cross the boundary between the element formation region and the trench (element isolation region). The electric field does not concentrate on the upper corner portion of the formation region.

Therefore, according to the present embodiment, the STI
In the case where is used, it is possible to prevent the deterioration of the electrical characteristics due to the electric field concentration in the upper corner portion of the element formation region. Specifically, for example, it is possible to prevent a reduction in gate breakdown voltage, the occurrence of kink in the sub-threshold characteristics, the occurrence of hump, and the like.

As a modification of this embodiment, FIG.
Instead of CMP of the silicon nitride film 16 in the step (f), as shown in FIG.
IE may be used. Subsequent steps are the same as those in FIG. FIG. 8B shows a sectional view corresponding to FIG. 7H. (Sixth Embodiment) FIG. 9 is a process sectional view showing a method for forming an STI and a MOS transistor according to a sixth embodiment of the present invention. Parts corresponding to FIGS. 6 and 7 are denoted by the same reference numerals as in FIGS. 7 and 8, and detailed description is omitted.

The present embodiment is different from the fifth embodiment mainly in that the polycrystalline silicon film 13 is removed after being oxidized. First, following the RIE step of the polycrystalline silicon film 6 shown in FIG. 7F of the seventh embodiment, as shown in FIG. 9A, the polycrystalline silicon film 13 is thermally oxidized to silicon oxide. Change to film 13a.

Next, as shown in FIG. 9B, the buffer oxide film 12 and the silicon oxide film 13a are removed by wet etching. Next, as shown in FIG. 9C, a gate oxide film 17 and a gate electrode 18 are formed on the element formation region.

Thereafter, the well-known MOS transistor manufacturing method is followed. That is, n-type impurity ions such as As ions are implanted into the element region using the gate electrode 8 as a mask to form n-type source / drain regions in a self-aligned manner, and then an interlayer insulating film is deposited. Then, a contact hole is opened to form a source / drain electrode (wiring) and a gate wiring.

In the present embodiment, the same effects as in the fifth embodiment can be obtained. Also, since the buried oxide film 15 can be densified in the oxidation step of changing the polycrystalline silicon film 13 into the silicon oxide film 13a by thermal oxidation, the subsequent densification step can be omitted. (Seventh Embodiment) Next, a method of forming a MOS transistor according to a seventh embodiment of the present invention will be described.

This embodiment is mainly different from the fourth embodiment in that an upper corner portion (exposed ST) of an element formation region is formed.
(I corner portion) is to selectively form a single crystal silicon film 6 'to be a silicon oxide film 6a.

First, as in the step of FIG. 4A of the third embodiment, the silicon nitride film 3 is retreated using hot phosphoric acid, and as shown in FIG. The buffer oxide film 2 in the upper corner is exposed.

Next, as shown in FIG. 10B, a single-crystal silicon oxide film 6 ′ is selected by an epitaxial growth method on the upper corner portion of the element formation region which is not covered with the silicon nitride film 3. It is formed.

Next, as shown in FIG. 10B, the silicon film 6 'is oxidized by a thermal oxidation method to change the silicon film 6' into a silicon oxide film 6a. As a result, the upper corner portion of the element formation region is covered with the silicon oxide film 6a. Subsequent steps are the same as the steps after FIG. 4C of the third embodiment.

In the present embodiment, the same effects as in the third embodiment can be obtained. Further, according to the present embodiment, since the silicon oxide film 6 ′ is formed only by the film forming process, the process can be shortened as compared with the third embodiment that requires the film forming process and the etching process. can get.

The present invention is not limited to the above embodiment, but can be variously modified as follows. For example,
In the above embodiment, the case where an n-channel MOS transistor is formed has been described.
This is also effective when forming an OS transistor. Further, the present invention relates to, for example, MOS diodes and other MI diodes.
It is also effective for an element having an S structure.

Further, in the above embodiment, RIE which is dry etching is used in the step of retracting the buried oxide film, but wet etching may be used. In the above embodiment, a polycrystalline silicon film is used, but an amorphous silicon film may be used.

In the above embodiment, CMP is used in the step of flattening the polycrystalline silicon film. However, etchback by CDE may be used. Further, in the above embodiment, the sidewall is left by RIE, but may be left by CDE. In addition, various modifications can be made without departing from the scope of the present invention.

[0093]

As described in detail above, in the present invention, the side walls of the element isolation trench, which is the boundary with the element formation region, are covered with the first and second element isolation insulating films. Here, the second isolation insulating film is formed so as to cover the sidewall of the isolation trench,
In addition, it protrudes from the surface of the element formation region on the boundary between the element formation region and the element isolation groove.

Therefore, even if a conductive film is formed on the element formation region so as to cross the boundary between the element formation region and the element isolation region, the electric field does not concentrate on the upper corner portion of the element formation region. Therefore, according to the present invention, it is possible to prevent the deterioration of the device characteristics due to the electric field concentration in the upper corner portion of the device forming region when the trench type device isolation is used.

[Brief description of the drawings]

FIG. 1 shows STI and M according to a first embodiment of the present invention.
Sectional drawing showing the method for forming the first half of the OS transistor

FIG. 2 shows STI and M according to the first embodiment of the present invention.
Sectional drawing showing the method of forming the latter half of the OS transistor

FIG. 3 shows STI and M according to a second embodiment of the present invention.
Process cross-sectional view illustrating a method for forming an OS transistor

FIG. 4 shows STI and M according to a third embodiment of the present invention.
Process cross-sectional view illustrating a method for forming an OS transistor

FIG. 5 shows STI and M according to a fourth embodiment of the present invention.
Process cross-sectional view illustrating a method for forming an OS transistor

FIG. 6 shows STI and M according to a fifth embodiment of the present invention.
Sectional drawing showing the method for forming the first half of the OS transistor

FIG. 7 shows STI and M according to a fifth embodiment of the present invention.
Sectional drawing showing the method of forming the latter half of the OS transistor

FIG. 8 is a process sectional view showing a modification of the fifth embodiment;

FIG. 9 shows STI and M according to a sixth embodiment of the present invention.
Process cross-sectional view illustrating a method for forming an OS transistor

FIG. 10 is a process cross-sectional view illustrating a method of forming an STI according to a seventh embodiment of the present invention.

FIG. 11 is a process sectional view showing a conventional method for forming an STI and a MOS transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 silicon substrate 2 buffer oxide film (first insulating film) 3 silicon nitride film (mask pattern) 4 resist pattern 5 buried oxide film (second insulating film, first element isolation insulating film) 6 ... polycrystalline silicon film (non-insulating film) 6 '... single-crystal silicon film (second element isolating insulating film) 6a ... silicon oxide film (second element isolating insulating film) 7 ... gate oxide film 8 ... gate electrode 11 ... Silicon substrate 12 ... Buffer oxide film (first insulating film) 13 ... Polycrystalline silicon film (mask pattern) 14 ... Resist pattern 15 ... Buried oxide film (second insulating film, first element isolation insulating film) 16 ... Silicon nitride film (third insulating film, second element isolation insulating film) 17 ... Gate oxide film 18 ... Gate electrode

Claims (17)

[Claims] An element isolation region in which an element isolation insulating film is embedded in an element isolation groove formed on a surface of a semiconductor substrate; an island-shaped element formation region separated from the element isolation region by the element isolation region; The device isolation insulating film comprises: a first device isolation insulating film buried to a depth in the middle of the device isolation trench; and a sidewall of the device isolation trench on the first device isolation insulating film. And a second element isolation insulating film protruding from the surface of the element formation region on a boundary between the element formation region and the element isolation groove. Semiconductor device. 2. The semiconductor device according to claim 1, wherein a conductive film is formed on the element formation region so as to extend over a boundary between the element formation region and the element isolation region. 3. The semiconductor device according to claim 1, wherein said conductive film is a gate electrode. 4. The semiconductor device according to claim 1, wherein said first element isolation insulating film is an insulating film containing impurities. 5. The semiconductor device according to claim 1, wherein said second element isolation insulating film is a silicon oxide film or a silicon nitride film. 6. A step of forming a first insulating film on a semiconductor substrate, a step of forming a mask pattern for forming an element isolation groove on the first insulating film, and using the mask pattern as a mask. A first insulating film,
Etching the semiconductor substrate, forming element isolation grooves on the surface of the semiconductor substrate, and forming a plurality of island-shaped element formation regions; and forming a second insulating film as a first element isolation insulating film. Forming a buried non-insulating film to be a second device isolation insulating film over the entire surface so that the device isolation groove is buried; Removing the non-insulating film on the mask pattern so that the non-insulating film on the boundary between the formation region and the element isolation trench does not fall below the surface of the element formation region; A method of manufacturing a semiconductor device, comprising: a step of forming a second element isolation insulating film by insulating; and a step of removing the first insulating film and the mask pattern. 7. The method according to claim 6, wherein the non-insulating film is formed after removing the mask pattern on an upper corner portion of the element formation region. 8. The method according to claim 6, wherein said mask pattern is formed of a silicon nitride film, and said non-insulating film is a polycrystalline silicon film. 9. The method according to claim 6, wherein the non-insulating film on the mask pattern is removed by a reactive ion etching method or a chemical mechanical polishing method. 10. A step of removing the mask pattern after forming the second insulating film by insulating the non-insulating film; and forming the second insulating film on the element forming region. 7. The method of manufacturing a semiconductor device according to claim 6, further comprising: forming a gate electrode on said gate insulating film so as to cross a boundary between said element isolation insulating film and said element formation region. 11. A step of forming a first insulating film on a semiconductor substrate, a step of forming a mask pattern for forming an element isolation groove on the first insulating film, and using the mask pattern as a mask. A first insulating film,
Etching the semiconductor substrate, forming element isolation grooves on the surface of the semiconductor substrate, and forming a plurality of island-shaped element formation regions; and forming a second insulating film as a first element isolation insulating film. Forming a third insulating film as a second device isolation insulating film on the entire surface so as to fill the device isolation groove; and forming the device formation region. Removing the third insulating film on the mask pattern so that the third insulating film on the boundary between the first insulating film and the element isolation groove does not become lower than the surface of the element forming region; Removing the insulating film and the mask pattern. 12. The method according to claim 11, wherein said mask pattern is formed of a polycrystalline silicon film, and said third insulating film is a silicon nitride film. 13. The method according to claim 11, wherein the third insulating film on the mask pattern is removed by a reactive ion etching method or a chemical mechanical polishing method. 14. A step of removing the mask pattern after removing the third insulating film on the mask pattern; and forming a gate insulating film on the element forming region, and then removing the second element isolation. 12. The method according to claim 11, further comprising: forming a gate electrode on the gate insulating film so as to extend over a boundary between the insulating film and the element formation region. 15. A step of forming a first insulating film on a semiconductor substrate, a step of forming a mask pattern for forming an element isolation groove on the first insulating film, and using the mask pattern as a mask. A first insulating film,
Etching the semiconductor substrate, forming element isolation grooves on the surface of the semiconductor substrate, and forming a plurality of island-shaped element formation regions; and forming a second insulating film as a first element isolation insulating film. A step of burying and forming a part of the element isolation groove to a depth, a step of removing the mask pattern on the upper corner part of the element region, Selectively forming an insulative non-insulating film to be an element isolating insulating film, forming an insulative non-insulating film to form a second element isolating insulating film, and forming the first insulating film. And a step of removing the mask pattern. 16. The method according to claim 15, wherein said non-insulating film is formed by an epitaxial growth method. 17. The method according to claim 15, wherein said mask pattern is formed of a silicon nitride film, and said non-insulating film is a single crystal silicon film.