JPH1154705A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics as a coil and realize high scale integration and miniaturization, by alternately laminating a plurality of insulating films and a plurality of coils on a substrate and electrically connecting the coils through slit-like vias. SOLUTION: A second wiring 106, a third wiring 109 and a fourth wiring 112 which constitute parts of coils of spiral inductors are mutually connected through slit-like vias, and only a first wiring 103 forming a lower extraction electrode and the second wiring 106 forming the coil part of the spiral inductor are connected with a dot-like first via. Since a plurality of inductors formed by laminating wirings are mutually connected through the slit-like vias 116, the slit parts can be also used as wirings, wiring resistance can be reduced as compared with the case that upper and lower wirings are connected through the dot-like via, so that the Q value of an inductor can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device for a microwave integrated circuit and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the spread of portable telephones such as PHS, demands for downsizing of high-frequency circuits for portable telephones have been increasing. In order to realize this with a semiconductor integrated circuit device,
It is necessary to mount on a single chip from active elements to passive elements such as resistors, capacitors, coils (hereinafter also referred to as inductors).

[0003] Since the resistance and the capacitance can be easily formed on a semiconductor substrate, the key point in realizing them is to form an inductor on the semiconductor substrate. At this time, it is necessary to secure an inductance required from the circuit, and to form an inductor having a small loss and a high resonance frequency. It is generally known that in order to obtain a high inductance, it is effective to use a spiral inductor (spiral inductor).

Here, as an example of a conventional spiral inductor, Joachim N.S. The structure proposed by Burghartz will be described (for details,
Joachim N. Burghartz: TECHNICAL DIGEST of internati
onal ELECTRON DEVICES meeting. 1015 (1995)). FIG. 15 is a plan view showing a conventional spiral inductor, and FIGS. 16 and 17 are enlarged plan views showing one layer portion of a layered portion in a region A of FIG. In the figure, 3
13 is a lower lead electrode made of a first wiring, 314 is an upper lead electrode made of a fourth wiring, 303 is a first wiring, 306 is a second wiring, 309 is a third wiring, 31
5 is a first via, and 316 is a second via.

Here, an example of a method for manufacturing the spiral inductor will be described with reference to FIG. This figure 1
8 is a sectional view taken along line AA of FIG. 16 and BB of FIG.
It shows a portion corresponding to a cross section along a line. First, as shown in FIG. 1A, a first interlayer insulating film 302 having a thickness of 1000 to 1600 nm is formed on a P-type semiconductor substrate 301, and aluminum is formed on the first interlayer insulating film 302.
500-1000 nm first conductive material such as copper
Is formed.

Next, as shown in FIG. 1B, a second interlayer insulating film 3 having a thickness of 500 to 800 nm is formed on the first wiring 303.
04, a first via 315 in the form of a dot is opened in the second interlayer insulating film 304, and if aluminum is used for the wiring in the first via 315, for example, 10 to 300
5 nm barrier metal made of titanium, titanium nitride, etc.
A first plug 337 is formed by embedding tungsten of 1000 to 1000 nm, and a second wiring 306 of 500 to 1000 nm made of a conductive material such as aluminum or copper is formed.

Next, as shown in FIG. 1C, the above-described steps are repeated to form a third interlayer insulating film 307, a second plug 338, a third wiring 309, and a fourth interlayer insulating film. 3
10, a third plug 339 and a fourth wiring 312 are formed. As described above, in the conventional spiral inductor, the first wiring 303, the second wiring 306, the third wiring 309, and the fourth wiring 312, which are upper and lower wirings, are formed by the dot-shaped first wiring.
Are connected to each other via a via 315 to a third via 317.

[0008] In this spiral inductor,
A total of five wiring layers are used. The first-layer wiring (not shown) is used in a portion other than the spiral inductor, and the lowermost first wiring 303 is formed by the second wiring layer. Then, the second wiring 306, the third wiring 309, and the fourth wiring 312 are formed in a third wiring layer, a fourth wiring layer, and a fifth wiring layer, respectively.

[0009]

Generally, as an index indicating the performance of an inductor, Q value <quality factor)
It is known that this Q value is expressed by the equation of Q = ωL / R. Here, R is wiring resistance, and L is inductance. By the way, in a conventional spiral inductor, when trying to obtain a large inductance, for example, in a spiral inductor designed with a wiring width of 12 μm and a wiring interval of 4 μm, the area of the spiral inductor is 226 μm in order to obtain a value of 5.1 nH. There was a problem that it occupied a large area called a corner.

Therefore, when the wiring width of the spiral inductor is reduced, there is a problem that the Q value is reduced because the wiring resistance R increases. Further, as shown in FIG. 19A, when the distance between the wirings 540 and 540 of the inductor is reduced, the aspect ratio between the wiring 540 and the wiring 540 increases, and the second interlayer insulating film 504 and the third interlayer insulating 540 are formed. Membrane 5
07 cannot be completely buried between the wirings 540 and 540.

As shown in FIG. 19B, for example, when the interlayer insulating film is planarized by using CMP (Chemical-Mechanical Polishing), the second interlayer insulating film 50 is formed.
There is a problem that a gap 541 is generated in the fourth and third interlayer insulating films 507, and the wirings 540 and 540 are damaged by the CMP etchant. Further, as shown in FIG. 19C, when the interlayer insulating film is planarized by dry etching, the planarization cannot be completed completely, a gap 541 is generated between the wirings 540 and 540, and an upper wiring is formed. In this case, there is a problem that the wiring material enters the gap 541 and causes a short circuit.

If the wiring resistance is reduced by increasing the film thickness of the wiring, the wiring 540 -the wiring 54
There is a problem that the aspect ratio between 0 becomes large and the interlayer insulating film cannot be buried in the same manner as described above.

The present invention has been made in view of the above circumstances, and by reducing a wiring bitch, ie, a wiring width and a wiring interval, the entire area of a coil formed on a substrate can be reduced. Another object of the present invention is to provide a semiconductor integrated circuit device capable of improving the characteristics as a coil and adapting to high integration and miniaturization, and a method of manufacturing the same.

[0014]

In order to solve the above-mentioned problems, the present invention employs the following semiconductor integrated circuit device and its manufacturing method. That is, the semiconductor integrated circuit device according to claim 1 is a device in which a plurality of insulating films and a plurality of coils are alternately stacked on a substrate, and the coils are electrically connected to each other via a slit-shaped via. is there.

According to a second aspect of the present invention, in the semiconductor integrated circuit device, a transistor is provided on the substrate, and a first ferromagnetic film is formed on at least one of a source / drain region and a gate electrode of the transistor. In addition, a second ferromagnetic film is formed below the plurality of coils.

According to a third aspect of the present invention, in the semiconductor integrated circuit device, the first ferromagnetic film and the second ferromagnetic film are formed of silicide.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit device, the coil has a spiral shape.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device, a ferromagnetic film is provided at a spiral center of the coil.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming an insulating film and a first coil on a substrate;
Forming an insulating film on the first coil, forming a slit-shaped via and a groove for forming a second wiring forming the second coil in the insulating film. And embedding a conductor in the slit-shaped via and the groove, and removing the conductor from a portion other than the via and the groove.

A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein a gate electrode and a source / drain region of a transistor are sequentially formed on the substrate, and a surface of the gate electrode and the source / drain region are formed on the substrate. The method includes a step of forming a ferromagnetic film and a step of removing an excess portion of the ferromagnetic film.

The method of manufacturing a semiconductor integrated circuit device according to claim 8, wherein the ferromagnetic film formed on the surface of the gate electrode and / or the source / drain region is silicided, and the gate electrode and the source / drain are formed. This is a method including a step of forming a silicide layer on at least one surface of the region.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a via at the center of the first and second coils; and forming a ferromagnetic film in the via. It is a method to have.

In the semiconductor integrated circuit device according to the present invention, a plurality of insulating films and a plurality of coils are alternately stacked on a substrate, and the coils are electrically connected to each other through slit-shaped vias. Wiring can be formed at narrow wiring intervals, and by connecting a plurality of wirings constituting a coil to each other via slit-shaped vias, the vias can also be used as coil wiring. Become.
Thus, even if the planar layout is the same, the cross-sectional area of the wiring is larger than in the case where the upper and lower wirings are connected by the conventional dot-shaped via, and the wiring resistance of the coil can be reduced. .

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a step of sequentially forming an insulating film on a substrate and a first wiring constituting a first coil; and forming an insulating film on the first coil. Forming a groove for forming a slit-shaped via and a second wiring forming a second coil in the insulating film; and embedding a conductor in the slit-shaped via and the groove. The step of removing the conductor from portions other than the vias and the trenches. This makes it possible to reduce the area of the entire coil formed on the substrate by reducing the wiring bitch, that is, the wiring width and the wiring interval.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a plan view showing a spiral inductor of a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIGS. 2 and 3 show a laminated portion of a region B in FIG. FIG. 4 is an enlarged plan view showing one layer portion of FIG.
It is sectional drawing which follows a line. In the drawing, reference numeral 113 denotes a lower extraction electrode formed of the first wiring 103, and 114 denotes an upper extraction electrode formed of the fourth wiring 112. here,
The spiral inductor 122 is connected to the lower extraction electrode 113.
And the upper lead electrode 114.

Reference numeral 106 denotes a second wiring, and 109 denotes a third wiring.
, 115 is a dot-shaped first via, and 116 is a slit-shaped second via. The second wiring 106, the third wiring 109, and the fourth wiring 112 forming the coil part of the spiral inductor are formed by slit-shaped vias 11.
6, only the first wiring 103 forming the lower extraction electrode 113 and the second wiring 106 forming the coil portion of the spiral inductor are connected by the dot-shaped first via 115. ing.

Next, a method of manufacturing the spiral inductor will be described with reference to FIGS. First, FIG.
As shown in FIG.
A first interlayer insulating film 102 of O00 to 16 OO nm is formed, and a first wiring 103 made of a conductive material such as aluminum or copper and having a thickness of 500 to 1000 nm is formed on the first interlayer insulating film 102. Interlayer insulating film 102 and first
A second interlayer insulating film 104 is grown on the wiring 103 of FIG.

Next, the surface of the second interlayer insulating film 104 is flattened by CMP, etch back, or the like so that the first wiring 103 has a thickness of 100 to 2000 nm. Next, as shown in FIG. 5B, a first mask 11 for forming a via on the second interlayer insulating film 104 is formed.
7 are formed, and a second mask 118 for forming wiring is formed on the first mask.

Next, as shown in FIG. 5C, openings are formed in the first mask 117 and the second mask 118 to expose the second interlayer insulating film 104, and anisotropic etching is performed. The exposed portion of the lever is etched to form a dot-shaped first via 115. In this case, the etching conditions are set so that the second interlayer insulating film 104 remains on the first wiring 103 by about 200 to 700 nm.

Next, as shown in FIG. 6D, the first mask 117 exposed at the opening of the second mask 118 is selectively etched with respect to the second interlayer insulating film 104, and In one mask 117, an opening 117a for forming a wiring is formed so that the second interlayer insulating film 104 is exposed.

Next, as shown in FIG. 6E, the exposed surface of the second interlayer insulating film 104 is removed by anisotropic etching.
Etching is performed to a thickness of 100 to 1000 nm to form a groove 119 for forming a wiring. After that, the first mask 117 and the second mask 118 are removed. At this time, the first via 11
5 is also etched at the same time, and its bottom is completely disappeared, so that the surface of the first wiring 103 is exposed.

Next, as shown in FIG. 6F, a first barrier metal 105 having a thickness of 10 to 300 nm is formed on the entire surface of the etched second interlayer insulating film 104, and the first barrier metal 105 is formed. A thickness of 800 to 20 made of a conductive material such as aluminum or copper on the metal 105 by CVD.
A second wiring 106 of 00 nm is formed, and the first via 11
5 and the groove 119 are completely buried.

Next, as shown in FIG.
An extra portion of the second wiring 106 is removed by using P, etchback, or the like, and the surface of the second interlayer insulating film 104 is flattened to form the second wiring 106. Then, FIG.
As shown in (h), the second interlayer insulating film 104 and the second
A third interlayer insulating film 107 is formed on the wiring 106, and the slit-shaped second via 11 is formed in the third interlayer insulating film 107.
6 and a groove for wiring formation.

Thereafter, a second barrier metal 10 having a thickness of 10 to 300 nm is formed on the entire surface of the third interlayer insulating film 107.
After forming the third wiring 109 made of a conductive material such as aluminum or copper and having a thickness of 800 to 2000 nm by CVD, and completely filling the second via 116 and the groove for forming the wiring, An extra portion of the third wiring 109 is removed by etching, CMP, etching, or the like, and the surface of the third interlayer insulating film 107 is further planarized.
09 is formed.

Further, the steps shown in FIGS. 5A to 7G are repeated to form a fourth interlayer insulating film 110 having a thickness of 10 to 10.
Forming a third barrier metal 111 of 300 nm in order,
Thereafter, a fourth wiring 112 made of a conductive material such as aluminum or copper and having a thickness of 800 to 2000 nm is formed by CVD, and a slit-like via and a groove for forming the wiring are completely buried. The surface of the fourth interlayer insulating film 110 is planarized and the fourth wiring 112
To form Thus, the spiral inductor of the present embodiment as shown in FIG. 4 can be manufactured.

FIGS. 8 to 10 show the results of experiments conducted to confirm the effect of the spiral inductor.
It will be described based on. FIG. 8 is an equivalent circuit of an inductor formed on a semiconductor substrate doped with a low resistance, for example, a P-type doped semiconductor substrate via an insulating film.
1 is the wiring resistance of the inductor, R2 and R3 are the resistances of the semiconductor substrate, C1 and C2 are the parasitic capacitance between the wiring and the semiconductor substrate, C3 is the parasitic capacitance between the wiring and the wiring, and C4 and C5 are both ends of the resistance of the semiconductor substrate. This is the parasitic capacitance attached.

FIG. 9 is a circuit diagram showing an outline of an experimental example (hereinafter, referred to as a conventional experiment) by a conventional branch operation, and FIG. 10 is a schematic diagram showing an experimental example (hereinafter, referred to as a main experiment) according to the present embodiment. It is a circuit diagram. Note that, in these figures, the wiring of the inductor has an aspect ratio of 1: 1, for easy understanding.
2 and 2: 1 have the same cross-sectional area, and the wiring interval and the wiring-substrate interval are also the same. In these figures, R1
Are not considered below for the above reasons, and R2, R3, C
Since the same semiconductor substrate is used for C4 and C5, they are not considered below.

In this experiment, C1 and C
It is clear that the value of 2 is halved and the value of C3 is doubled. However, when the values of C1, C2, and C3 were determined by experiments, C1 and C2 were about 1p in the conventional experiment.
F and C3 were about 20 fF, and it became clear that C3 was negligibly small compared to C1 and C2. Since it is known from experiments that C4 and C5 are 30 to 60 fF, C1 and C5 are the total parasitic capacitances C1 to C5 parasitic on the spiral inductor.
The value of 2 was found to be dominant by two orders of magnitude. From the above, in this experiment, it was found that the total parasitic capacitance parasitic to the spiral inductor can be reduced as compared with the conventional experiment.

According to the spiral inductor of the semiconductor integrated circuit device of the present embodiment, a plurality of inductors formed by laminating wirings are connected to each other through slit-shaped vias, so that the slits can be used as wirings. The wiring resistance can be reduced as compared with the case where the upper and lower wirings are connected by dot-shaped vias, and the Q value of the inductor can be improved.

Further, since the wirings stacked in the vertical direction to the substrate are connected to each other by slit-shaped vias, when obtaining the same wiring cross-sectional area, the wiring thickness is larger than that of the conventional spiral inductor, and The wiring width can be reduced, the capacitance between the wiring and the substrate can be reduced, and the capacitance between the wiring and the wiring increases by a small amount, but the total parasitic capacitance parasitic to the viral inductor can be reduced. it can.

According to the method of manufacturing a spiral inductor of a semiconductor integrated circuit device of the present embodiment, an interlayer insulating film for insulating and separating upper and lower wirings is formed first, and a slit-like film for connecting upper and lower wirings is formed. Forming grooves for forming vias and wiring, burying conductive material in slit-shaped vias and grooves, removing conductive material in portions other than grooves, and forming wiring. Therefore, the wiring bitch can be narrowed, and the area of the spiral inductor can be reduced.

(Second Embodiment) FIG. 11 shows a second embodiment of the present invention.
FIG. 12 is a plan view showing a spiral inductor of the semiconductor integrated circuit device according to the embodiment, and FIG. 12 is a sectional view taken along the line DD in FIG.

The difference between the spiral inductor of the present embodiment and the spiral inductor of the first embodiment is that a via 318 having an aspect ratio of about 3 to 5 is formed at the center of the spiral inductor. A first ferromagnetic film 120 of cobalt, nickel, or the like having a thickness of 10 to 1000 nm is formed on the inner surface, and a fifth interlayer insulating film 121 is embedded in a region surrounded by the first ferromagnetic film 120. Is a point. In the spiral inductor, the inductance of the spiral inductor is improved by using the first ferromagnetic film 120 as the magnetic core of the spiral inductor.

Next, a method of manufacturing the spiral inductor will be briefly described with reference to FIGS. First, similarly to the manufacturing method of the first embodiment, FIG.
7 to form a spiral inductor composed of four wiring layers. Next, as shown in FIG.
An interlayer insulating film (not shown) having a thickness of 10 to 100 nm is formed, and the aspect ratio is about 3 at the center of the spiral inductor.
5 through 318 are formed until they reach the fourth interlayer insulating film 110.

Next, the inner surface of the via 318 has a thickness of 10 to
A first ferromagnetic film 120 of 1000 nm, such as cobalt or nickel, is formed, and a fifth interlayer insulating film 121 is buried in a region surrounded by the first ferromagnetic film 120. afterwards,
After the fifth interlayer insulating film 121 completely fills the via 318, the fourth wiring 112 is formed by CMP, etching, or the like.
Expose the surface.

According to the spiral inductor of the semiconductor integrated circuit device of the present embodiment, since the first ferromagnetic film 120 is formed at the center of the spiral inductor, the inductance L of the inductor can be increased.

(Third Embodiment) FIGS. 13 and 14 are process diagrams showing a method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention. First, the structure of the semiconductor integrated circuit device according to the present embodiment will be described with reference to FIG.

This structure is composed of a spiral inductor and a CM.
An OS is simultaneously formed on the same wafer (substrate), and a silicide layer 231 as a first ferromagnetic film is formed on the surface of each of the source / drain region 228 and the gate electrode 225 of the CMOS. In which a second ferromagnetic film 229 made of silicide is formed.

The structure of the wiring layer of this spiral inductor is the same as that of the conventional spiral inductor, the first and second spiral inductors.
The same as each of the spiral inductors of the first embodiment,
The second wiring forms the lower lead electrode, the second and third wirings form the coil part of the spiral inductor, and the fourth wiring forms the coil part of the spiral inductor and the upper lead electrode.

Next, a method for manufacturing a semiconductor integrated circuit device will be described.
This will be described with reference to FIGS. First, FIG.
As shown in FIG.
An element isolation insulating film 222 of about 1000 nm is formed, then a P-type well region (N-type well region for PMOS) 223 for NMOS is formed by ion implantation or the like, and then a gate oxide film 224 and multiple 100-400 made of crystalline silicon or amorphous silicon
A gate electrode 225 of nm is formed, and an LDD region 226 is formed in the self-alignment of the gate electrode 225 by ion implantation.

Next, as shown in FIG.
A side wall 227 made of a silicon oxide film or a silicon nitride film having a thickness of about 200 nm is formed, and a P ⁺ -type source / drain region 228 (N-type ⁺ source / drain region for a PMOS) is formed by ion Then, a second ferromagnetic film 229 of 5 to 100 nm made of cobalt, nickel or the like is formed.

Next, as shown in FIG.
A fifth interlayer insulating film 230 having a thickness of about 200 nm is formed, and the fifth interlayer insulating film 230 is formed only in a portion below the spiral inductor by using a mask.
The surface of the gate electrode 225 and the surface of the source / drain region 228 are silicided by annealing in, for example, a nitrogen atmosphere or an argon atmosphere while leaving the interlayer insulating film 230 of After that, the second ferromagnetic film 229 is selectively removed from portions other than the portion under the fifth interlayer insulating film 230.

Next, as shown in FIG.
A sixth interlayer insulating film 232 having a thickness of 00 to 2000 nm is formed, and the sixth interlayer insulating film 2 is formed by using CMP, etching, or the like.
32, the contact 320 is formed on the gate electrode 225 and the source / drain region 228 of the CMOS.
320 is opened and a fourth
The barrier metal 233 and the fifth wiring 234 are formed.

Next, as shown in FIG.
A seventh interlayer insulating film 235 having a thickness of 00 to 2000 nm is formed, and a fifth barrier metal 236, 5 having a thickness of 10 to 300 nm is formed.
First wirings 203 each having a thickness of 00 to 1000 nm are formed. The first wiring 203 of the spiral inductor
Form the lower extraction electrode of the spiral inductor.

Next, as shown in FIG.
The second interlayer insulating films 204, 10 to
300 nm first barrier metal 205, 500-10
00 nm second wiring 206, 1000 to 2000 nm
Third interlayer insulating film 207, 10 to 300 nm second barrier metal 208, 500 to 1000 nm third wiring 209, 1000 to 2000 nm fourth interlayer insulating film 210, 10 to 300 nm third barrier Metal 21
A fourth wiring 212 having a thickness of 1,500 to 1,000 nm is formed.

In general, it is known that a magnetic field leakage can be reduced by disposing a ferromagnetic film under a spiral inductor.
The silicide layer used on the surface of the source / drain region 228 and the gate electrode 225 is formed of C such as cobalt or nickel.
A silicide of a ferromagnetic film generally used in MOS,
This was achieved by masking the ferromagnetic film after silicidation and leaving it selectively under the spiral inductor.

Further, by further applying this embodiment, it is possible to leave ferromagnetic films above and below the inductor. Further, by combining the above-described second embodiment with an application example of this embodiment, It is also possible to leave a ferromagnetic film on the top and bottom of the inductor and on the core of the inductor,
By digging a slit-shaped groove so as to surround the periphery of the spiral inductor and leaving the ferromagnetic film in the groove, it is possible to cover the top and bottom and the periphery with the ferromagnetic film, thereby preventing leakage of the magnetic field. In the present embodiment, a spiral inductor is used, but it is needless to say that it can be realized with a normal inductor.

According to the semiconductor integrated circuit device of the present embodiment, the magnetic field leakage can be reduced by leaving the ferromagnetic film generally used in the CMOS manufacturing process below the inductor, and the CMOS manufacturing process can be reduced. Can be improved.

[0060]

As described above, according to the semiconductor integrated circuit device of the present invention, a plurality of insulating films and a plurality of coils are alternately stacked on a substrate, and the coils are formed with slit-shaped vias. Since the wires are electrically connected to each other, the wires can be formed at a narrow wiring interval. Also, since a plurality of wires constituting the coil are connected to each other via the slit-shaped via, the via portion is also connected to the wire of the coil. Even if the planar layout is the same, the cross-sectional area of the wiring can be increased compared to the case where the upper and lower wirings are connected with the conventional dot-shaped vias, and the wiring resistance of the coil can be reduced. Can be planned. Therefore, the area of the entire coil as an element can be reduced, the characteristics of the coil can be improved, and high integration and miniaturization of a semiconductor integrated circuit device can be achieved.

According to the method for manufacturing a semiconductor integrated circuit device of the present invention, an insulating film and a first coil constituting a first coil are formed on a substrate.
Forming an insulating film on the first coil, forming a slit-shaped via and a groove for forming a second wiring forming the second coil in the insulating film. Forming the conductors in the slit-shaped vias and the grooves, and removing the conductors from portions other than the vias and the grooves. Can be. Therefore, the area of the entire coil as an element can be reduced, and high integration and
A semiconductor integrated circuit device that can cope with miniaturization can be manufactured.

[Brief description of the drawings]

FIG. 1 is a plan view showing a spiral inductor of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is an enlarged plan view showing one layer of a layered portion of a region B in FIG. 1;

FIG. 3 is an enlarged plan view showing one layer of a layered portion of a region B in FIG. 1;

FIG. 4 is a sectional view taken along the line CC of FIG. 1;

FIG. 5 is a process chart showing a method of manufacturing the spiral inductor of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 6 is a process chart showing a method of manufacturing the spiral inductor of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 7 is a process chart showing a method for manufacturing a spiral inductor of the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 8 is an equivalent circuit of an inductor formed on a substrate having a low layer resistance via an insulating film.

FIG. 9 is a circuit diagram schematically illustrating an experimental example using a conventional branch technique.

FIG. 10 is a circuit diagram schematically illustrating an experimental example according to the first embodiment of the present invention.

FIG. 11 is a plan view showing a spiral inductor of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 12 is a sectional view taken along line DD in FIG. 11;

FIG. 13 is a process chart illustrating a method for manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 14 is a process chart illustrating a method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 15 is a plan view showing a conventional spiral inductor.

FIG. 16 is an enlarged plan view showing a layer portion of a layered portion in a region A of FIG.

FIG. 17 is an enlarged plan view showing a layer portion of a layered portion in a region A of FIG.

FIG. 18 is a process diagram showing an example of a conventional method for manufacturing a spiral inductor.

FIG. 19 is a cross-sectional view for describing a problem in a conventional method for manufacturing a spiral inductor.

[Explanation of symbols]

101, 201, 301, 401, 501 P-type semiconductor substrate 102, 302, 502 First interlayer insulating film 103, 203, 303 First wiring 104, 204, 304, 504 Second interlayer insulating film 105, 205 1st barrier metal 106, 206, 306 2nd wiring 107, 207, 307, 507 3rd interlayer insulating film 108, 208 2nd barrier metal 109, 209, 309 3rd wiring 110, 210, 310 4th Interlayer insulating film 111, 211 Third barrier metal 112, 212, 312 Fourth wiring 113 Lower extraction electrode 114 Upper extraction electrode 115 First via 116 Second via 117 First mask 117a Opening 118 Second Mask 119 Groove for forming wiring 120 First ferromagnetic film 121 Fifth interlayer insulating film 122 Spiral inductor 222 Element isolation insulating film 223 Well region 224 Gate oxide film 225 Gate electrode 226 LDD region 227 Side wall 228 Source / drain region 229 Second ferromagnetic film 230 Fifth interlayer insulating film 231 Silicide layer 232 First Sixth interlayer insulating film 233 Fourth barrier metal 234 Fifth wiring 235 Seventh interlayer insulating film 236 Fifth barrier metal 313 Lower extraction electrode 314 Upper extraction electrode 315 First via 316 Second via 317 Third Via 318 via 320 contact 337 first plug 338 second plug 339 third plug 440, 540 wiring 541 gap

Claims (9)

[Claims] 1. A semiconductor integrated circuit, wherein a plurality of insulating films and a plurality of coils are alternately stacked on a substrate, and the coils are electrically connected to each other through slit-shaped vias. apparatus. 2. A transistor is provided on the substrate, a first ferromagnetic film is formed on at least one surface of a source / drain region or a gate electrode of the transistor, and the plurality of coils are provided. Second under
2. The semiconductor integrated circuit device according to claim 1, wherein said ferromagnetic film is formed. 3. The semiconductor integrated circuit device according to claim 2, wherein said first ferromagnetic film and said second ferromagnetic film are made of silicide. 4. The semiconductor integrated circuit device according to claim 1, wherein the coil has a spiral shape. 5. The semiconductor integrated circuit device according to claim 4, wherein a ferromagnetic film is provided at a spiral center of said coil. 6. A step of sequentially forming an insulating film and a first wiring constituting a first coil on a substrate, forming an insulating film on the first coil, and forming a slit-shaped via in the insulating film. Forming a groove for forming a second wiring constituting the second coil, embedding a conductor in the slit-shaped via and the groove, and forming the conductor other than the via and the groove. Removing the portion from the portion. 7. A step of sequentially forming a gate electrode and a source / drain region of a transistor on the substrate; a step of forming a ferromagnetic film on surfaces of the gate electrode and the source / drain region; 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, further comprising the step of removing an excess portion of the magnetic film. 8. A ferromagnetic film formed on the surface of the gate electrode and / or the source / drain region is silicided, and a silicide layer is formed on at least one surface of the gate electrode and the source / drain region. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7, further comprising the step of: 9. The semiconductor according to claim 6, further comprising a step of forming a via at the center of the first and second coils, and a step of forming a ferromagnetic film in the via. A method for manufacturing an integrated circuit device.