JPH1154584A - Semiconductor device and evaluation method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cancel the entire existing leakage current or unnecessary component by reverse leakage current derived from a second PN junction, by adding the second PN junction for compensation of leakage current from a first PN junction. SOLUTION: An existing PN junction 3 is formed within a semiconductor device 4. The semiconductor device 4 is electrically connected via a connection line 5 to a semiconductor device 2 having a PN junction 1a to compensate a leakage current from the PN junction 3. Thus, by additionally providing the other PN junction 1a, the leakage current derived from the PN junction 3 upon operation of the semiconductor device 4 can be compensated by utilizing cancellation of the leakage current from the PN junction 1a. The PN junction 1a may be provided on the same substrate where the PN junction 3 is provided, or may be provided on a different substrate. Further, in a semiconductor device, a leakage current which occurs in the central portion of PN junction and a leakage current which occurs in the peripheral portion of the PN junction, are generated by different mechanisms.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device capable of compensating for a leakage current caused by a PN junction and a method of evaluating the same.

[0002]

2. Description of the Related Art A PN junction is indispensable as a component of a semiconductor device such as a diode and a transistor because of its excellent rectifying characteristics. However, when a reverse bias voltage is applied to the PN junction, a leak current flows.
This causes deterioration of device characteristics such as an increase in power consumption and a decrease in output of the inverter.

[0003]

The cause of the increase in the leak current is a crystal defect in a semiconductor material forming a PN junction,
Or heavy metal contamination in the PN junction formation process. For crystal defects in the semiconductor material, the quality of the semiconductor material has been improved, and for heavy metal contamination, the process has been cleaned up. In order to reduce the leakage current, measures such as reducing the junction area of the PN junction are actually taken. However, as the miniaturization of semiconductor devices and the reduction in power consumption have progressed, there has been an increasing demand for a reduction in leakage current for the purpose of improving device characteristics, and this is still an important issue.

[0004]

According to a first aspect of the present invention, there is provided a semiconductor device having a first PN junction.
A second PN junction for compensating a leakage current of the PN junction is added. This makes it possible to obtain a semiconductor device having good device characteristics without being affected by defects in a semiconductor material and a semiconductor manufacturing process.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first PN junction and the second PN junction are connected so that voltages having opposite polarities are applied to each other. .

When a voltage is applied, the second PN having the opposite direction
The leak current at the junction can cancel out and compensate for all or a predetermined component of the leak current at the first PN junction.

According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the second PN junction is a first PN junction.
It is characterized by being formed by a process under substantially the same conditions as the PN junction.

As a result, when the same reverse bias voltage is applied, the same leakage current occurs at the first and second PN junctions.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the third aspect, further comprising a transistor of one conductivity type and a transistor of another conductivity type, wherein the first PN junction is formed in a drain region of the one conductivity type transistor. A voltage whose absolute value is a predetermined multiple of a voltage applied to a series connection of the one conductivity type transistor and the other conductivity type transistor is connected to the one conductivity type transistor and the second PN transistor.
It is characterized in that it is applied to a series connection with a junction.

For example, when a voltage twice as high as a voltage to be applied during operation of a circuit element (inverter) including a first PN junction is applied to a series connection of a one conductivity type transistor and a second PN junction, the first and second PN junctions are applied. Since the voltages applied to the junctions are both reverse biased and opposite in direction, a current from which the leakage current has been removed can be obtained by summing the currents. Therefore, there is apparently no leakage current, so that the characteristics of the device can be improved.

A semiconductor device according to a fifth aspect of the present invention is characterized in that:
4. The semiconductor device according to any one of 4,
The N-junction is characterized in that the peripheral length is substantially the same as that of the first PN junction and the area is different. In the present invention, “substantially the same” includes an error that occurs within the processing accuracy range of the manufacturing apparatus, and does not necessarily mean that they are physically completely the same. Absent.

By canceling the same component (peripheral component) of the existing leak current of the first PN junction with the leak current originating from the second PN junction, the area component of the leak current originating from the existing first PN junction can be obtained. Suitable for evaluation semiconductor devices.

According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the second PN junction has substantially the same area as the first PN junction and has a different peripheral length. It is characterized by the following.

By canceling the same component (area component) of the leak current of the existing first PN junction with the leak current derived from the second PN junction, it is possible to obtain a peripheral component in the leak current derived from the existing first PN junction. Suitable for evaluation semiconductor devices.

According to a seventh aspect of the present invention, there is provided a semiconductor device evaluation method,
The first and second Ps in the semiconductor device according to claim 5.
A voltage of the opposite polarity having substantially the same absolute value is applied to the N-junction at least once each, a leak current in each case is measured, and a difference between leak currents when the absolute value is the same is obtained. A predetermined component of the leakage current is obtained from a plurality of differences obtained for the absolute value of

By utilizing the above-described operation, it is possible to obtain a predetermined component, that is, an area component or a peripheral length component, of the leak current derived from the existing first PN junction.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings showing the embodiments. Embodiment 1 FIG. FIG. 1 is a conceptual diagram showing a configuration of the semiconductor device according to the first embodiment. In the figure, reference numeral 3 denotes an existing PN junction, which is formed in the semiconductor device 4. A semiconductor device 2 having a PN junction 1 a for compensating for a leakage current of the PN junction 3 is electrically connected to the semiconductor device 4 via a connection line 5.

By adding another PN junction 1a in this manner, the leakage current originating from the PN junction 3 during the operation of the semiconductor device 4 can be canceled out and compensated by utilizing the leakage current of the PN junction 1a. PN junction 1a is PN junction 3
May be provided on the same substrate as the above, or may be provided on a different substrate.

Embodiment 2 FIG. 2 is a diagram showing a circuit including the semiconductor device according to the second embodiment. In this embodiment, the concept of the first embodiment is applied to an evaluation device, and a PN junction 1b is reversely connected to a PN junction 3 to be evaluated. The voltage sources 6 are connected in series to form a series circuit. The PN junction 3 and the PN junction 1b have the same peripheral length and different areas.

In the semiconductor device thus configured, P
When a forward bias voltage is applied to the N junction 3, the PN junction
A reverse bias voltage is applied to 1b. When the current at this time is measured by an ammeter 7 connected in series with the circuit, the ammeter 7 shows a value equal to the leak current of the PN junction 1b because the forward bias resistance is much smaller than the reverse bias resistance. Conversely, applying a reverse bias voltage to the PN junction 3
When a forward bias voltage is applied to the junction 1b, the ammeter 7 indicates a value equal to the leakage current of the PN junction 3.

The mechanism by which the leakage current of the semiconductor device occurs at the center of the PN junction and that at the periphery of the PN junction are different. The leak current generated in the central portion is derived from a defect existing in a substrate (for example, a silicon substrate), and is hereinafter referred to as an area component. The leak current generated in the peripheral portion includes a current component derived from a defect on the semiconductor surface, and is hereinafter referred to as a peripheral component. The leak current of the PN junction mainly includes these area components and peripheral components. Further, the corner of the PN junction is a singular point in structure, and the leakage current generated here includes, for example, a current component derived from electric field concentration. This current component is hereinafter referred to as a corner component.

In the present embodiment, since the two PN junctions have the same peripheral length and different areas, when the applied voltages have the same absolute value, the area difference of the PN junction leak current is obtained from the difference between the obtained current values. Can be obtained. The leakage current measurements PN junction 1b and I _1, the area of the PN junction 1b and S _1, the leakage current measured value of the PN junction 3 and I _3, the area of the PN junction 3 When S _3, the unit surface shape The leak current I _unit per area is obtained by the following equation. I _unit = | I ₁ -I ₃ | / | S ₃ -S ₁ | (1)

Since this value relates only to the area component, it is suitable as an index for substrate evaluation. In order to obtain this value by the conventional method, it is necessary to change the probing location because two samples are separately measured, which takes time, and a lot of measurement errors are included depending on the contact state of the stylus. was there. However, according to the method of the present invention, since the probing state is the same, it is determined in principle only by the accuracy of the ammeter and the accuracy of the prober, so that it contains almost no error. Here, the number of corners needs to be the same in order to eliminate the influence of the corner component.

Embodiment 3 FIG. FIG. 3 is a diagram showing a circuit including the semiconductor device according to the third embodiment. In this embodiment, the concept of the first embodiment is applied to an evaluation device, and a PN junction 1c is reversely connected to a PN junction 3 to be evaluated. The voltage sources 6 are connected in series to form a series circuit. The PN junction 3 and the PN junction 1c have the same area and different peripheral lengths.

In the semiconductor device thus configured, as in the second embodiment, when a forward bias voltage is applied to the PN junction 3, a reverse bias voltage is applied to the PN junction 1c. The current at this time is measured by an ammeter 7 connected in series to the circuit.
Since the forward bias resistance is much smaller than the reverse bias resistance, the ammeter 7 shows a value equal to the leak current of the PN junction 1c. Conversely, when a reverse bias voltage is applied to the PN junction 3 and a forward bias voltage is applied to the PN junction 1c, the ammeter 7 indicates a value equal to the leakage current of the PN junction 3. Therefore, when the absolute values of the applied voltages are equal in these cases, the peripheral component of the PN junction leak current can be obtained from the difference between the obtained current values. The calculation formula is the same as the formula (1). Here, the number of corners needs to be the same in order to eliminate the influence of the corner component.

Embodiment 4 FIG. 4 relates to the fourth embodiment.
FIG. 3 is a circuit diagram illustrating a configuration of a semiconductor device. This embodiment
Describes the concept of the first embodiment in a half
This is applied to an inverter that is a conductor device. Power supply
V_DDP-channel MOSFET 8 and N-channel MO between ground and ground
An SFET 9 is connected in series, and a P-channel MOSFET 8
Power supply V _DDN-channel type MOSF
The substrate of ET9 is grounded. P-channel type MOSFET8 and
The connection point of the N-channel MOSFET 9 and the N-channel MOSFET
PN junction of the same structure as the PN junction at the drain of SFET 9
The P side of 1d is connected and its N side is 2 × V_DDNo electricity
Connected to the second place. And a P-channel MOSFET 8 and
Enter the connection point connecting both gates of N-channel MOSFET 9
Force terminal V_inAnd a P-channel MOSFET 8 and an N-channel MOSFET
The connection point between the MOSFET 9 and the PN junction 1d is connected to the output terminal V_outToss
You.

[0027] When the PN junction 1d is not connected, V _in
= 0 (V), V _out <V _DD (V) and the voltage V _L due to the leakage current are reduced, but as shown in FIG.
If 1d is added, because it is fixed to the potential of the N side is 2 × V _DD of the PN junction 1d, potential V _out at the output terminal V _{out is, V out = 2 × V DD} -V L - ( (V _DD -V _L ), the leakage current is compensated, and it is possible to maintain V _out = V _DD (V).

[0028]

【Example】

Embodiment 1 FIG. FIG. 5 is a diagram illustrating a measurement circuit of the semiconductor device according to the second embodiment. A rectangular N-type diffusion layer 13 having an area of 0.5 mm ² and a peripheral length of 4 mm and a square N-type diffusion layer 14 having an area of 1 mm ² and a peripheral length of 4 mm are formed at appropriate positions on the surface of the P-type silicon wafer 15. Have been. The N-type diffusion layers 13 and 14 include a voltage source 6 (included in HP4140B) and a capacitance meter (HP428
4A) A channel matrix 12 for switching between 10 and an ammeter (included in HP4140B) 7 is connected. Voltage source 6, ammeter 7, capacity meter 10, and channel matrix 12
Is connected to the computer 11 via a GP-IB cable 16.

The voltage from the voltage source 6 is changed to 0.2, 0.4,
FIG. 6 shows the measurement results of the leak current value when the depletion layer width W was changed to 6, 0.8, and 1.0 V. The depletion layer width W on the horizontal axis in FIG. 6 is calculated from the capacitance value. When the output voltage is positive (x in FIG. 6) or negative (o in FIG. 6), the leakage current value includes an area component and a peripheral component, so that the leakage current increases as the depletion layer width W increases. Increase in a curve. Therefore, the dependence of the leak current on the depletion layer width is approximated by a straight line, and a diffusion current component (a current component diffused from the outside of the depletion layer, that is, from the inside of the bulk) is obtained from the intercept of the vertical axis (leak current) of the straight line. It can be seen that it is impossible to apply a method for determining the lifetime of carriers generated in the depletion layer from the slope of the straight line.

However, the difference between the current values when positive and negative voltages having the same absolute value are applied changes linearly (● in FIG. 6). This is because this value includes only the area component. Therefore, the area component of the leakage current approximates the depletion layer width dependence with a straight line, and the diffusion current component and the lifetime of carriers generated in the depletion layer can be obtained.

Embodiment 2 FIG. FIG. 7 is a schematic sectional view showing the semiconductor device according to the fourth embodiment. In this semiconductor device, a CMOS inverter 30 is formed on an SOI wafer, and a PN junction 1d is further added. Silicon substrate
A buried oxide film 18 having a thickness of 1.0 μm is formed on the substrate 17, and a P-type layer 22 a, an N-type layer 23, and a P-type layer 22 b are formed thereon by element isolation by an element isolation oxide film 19. ing. On the surface of the P-type layer 22a, a P-type diffusion layer 24a, an N-type diffusion layer 25a,
N-type diffusion layers 25b are formed at appropriate intervals. N
On the surface of the mold layer 23, a P-type diffusion layer 24b, a P-type diffusion layer 24c,
N-type diffusion layers 25c are formed at appropriate intervals. N
The surface of the mold layer 22b has a P-type diffusion layer 24d and an N-type diffusion layer 25d.
Are formed at appropriate intervals.

On the P-type layer 22a, a gate oxide film 20a is formed over the N-type diffusion layer 25a and the N-type diffusion layer 25b, and a gate polysilicon electrode 21a is further laminated thereon. . On the N-type layer 23, a gate oxide film 20b is formed over the P-type diffusion layer 24b and the P-type diffusion layer 24c, and a gate polysilicon electrode 21b is further laminated thereon.

The P-type diffusion layer 24a and the N-type diffusion layer 25a are grounded, and the P-type diffusion layer 24c and the N-type diffusion layer 25c are connected to the power supply _VDD . 2 × V is applied to the N-type diffusion layer 25d.
_DD potential is applied. Gate polysilicon electrode 21
a and 21b are connected and the input terminal V of the CMOS inverter 30 is
_The N-type diffusion layer 25b, the P-type diffusion layer 24b, and the P-type diffusion layer 24d are connected to form an output terminal _Vout of the CMOS inverter 30.

FIG. 8 shows an input terminal V_inWith a period of 10 nsec.
Input potential V when applying a shape wave _inAnd output potential V
_outFIG. Solid line indicates input potential V_inIndicates that
The broken line indicates the output potential V in the semiconductor device shown in FIG._outTo
Show. The dashed line indicates a conventional semiconductor without a PN junction 1d.
Output potential V in the device (inverter only)_outShows
You.

In the conventional device, the N-type layer formed on the P-type layer 22a is
Output terminal V of channel type MOSFET 9 _outN connected to
PN junction composed of the P-type diffusion layer 25b and the P-type layer 22a
If there is a leakage current, a voltage drop occurs here,
The output potential V_{ou t}Decrease. For PN junction
Leakage current due to wafer-derived defects and device operation
Defects from the synthesis process are the cause. But
The same structure created by the same process on the same wafer
PN junction of N-channel MOSFET 9 and PN junction 1d
Has the same value of leakage current as
Has the effect as described in the description of FIG. That is, V
_in= 0 (V), the PN junction of the N-channel MOSFET 9
2 × V for series connection with PN junction 1d_DDVoltage is applied
Therefore, the output potential V of the inverter 30_outIs V_DDMaintained in
You. Thus, the inverter having the configuration of the present invention is ideal.
It can be said that it has a characteristic.

[0036]

As described above, in the semiconductor device according to the present invention, the addition of the second PN junction for compensating for the leak current originating from the existing first PN junction makes it possible to achieve the opposite effect derived from the second PN junction. All or unnecessary components of the existing leak current can be canceled by the leak current. When a predetermined reverse bias voltage is applied to the second PN junction formed under the same conditions, the second PN junction can be applied to a semiconductor device actually used in a circuit, and the device characteristics are significantly improved. can do. Further, when a reverse bias voltage having the same absolute value is applied to the second PN junctions formed with different areas or perimeters, the present invention is excellent in that a predetermined component of the leak current can be accurately measured. It works.

[Brief description of the drawings]

FIG. 1 is a conceptual diagram showing a semiconductor device according to a first embodiment.

FIG. 2 is a diagram illustrating a circuit including a semiconductor device according to a second embodiment;

FIG. 3 is a diagram illustrating a circuit including a semiconductor device according to a third embodiment;

FIG. 4 is a circuit diagram showing a semiconductor device according to a fourth embodiment.

FIG. 5 is a diagram illustrating a measurement circuit of the semiconductor device according to the first embodiment.

FIG. 6 is a graph showing a measurement result of a leak current in Example 1.

FIG. 7 is a schematic sectional view showing a semiconductor device used in Example 2.

8 is a waveform diagram showing input waveforms and output waveforms in the semiconductor device shown in FIG. 7 and a conventional semiconductor device.

[Explanation of symbols]

 1a, 1b, 1c, 1d, 3 PN junction 2, 4 Semiconductor device 16 GP-IB cable

Claims (7)

[Claims] In a semiconductor device including a first PN junction, a second P-type semiconductor device for compensating for a leakage current of the first PN junction.
A semiconductor device to which an N junction is added. 2. The semiconductor device according to claim 1, wherein the first PN junction and the second PN junction are connected such that voltages of opposite polarities are applied to each other. 3. The semiconductor device according to claim 1, wherein the second PN junction is formed by a process under substantially the same conditions as the first PN junction. 4. A transistor comprising a transistor of one conductivity type and a transistor of another conductivity type, a first PN junction is formed in a drain region of the transistor of one conductivity type, and a first PN junction is formed between the transistor of one conductivity type and the transistor of another conductivity type. 4. A voltage whose absolute value is a predetermined multiple of a voltage applied to the series connection is applied to the series connection of the one conductivity type transistor and the second PN junction. 13. The semiconductor device according to claim 1. 5. The semiconductor device according to claim 1, wherein the second PN junction has substantially the same peripheral length and a different area as the first PN junction. 6. The semiconductor device according to claim 1, wherein the second PN junction has substantially the same area as the first PN junction and has a different peripheral length. 7. The semiconductor device according to claim 5, wherein voltages of opposite polarities having substantially the same absolute value are respectively applied to the first and second PN junctions at least once each, and leakage in each case is performed. A method for evaluating a semiconductor device, comprising: measuring a current; obtaining a difference between leak currents when the absolute values are the same; and obtaining a predetermined component of the leak current from a plurality of differences obtained for a plurality of absolute values.