JPH1152420A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress longitudinal smear, to improve the productivity, and to reduce power consumption by providing conductive light shield films on the opposite surfaces of video signal lines and mutually inverting the polarities of video signal voltages applied to adjacent video signal lines in the same period. SOLUTION: The conductive light shield films are formed on the opposite surfaces of video signal lines and the polarities of the video signal voltages applied to adjacent video signal lines are mutually inverted in the same period. Namely, a scanning signal VG has ON level in every 1 scanning period and others have OFF level. The video signal voltage is applied to one pixel while inverted in polarity in alternate frames with an amplitude twice as large as that of a voltage applied to a liquid crystal layer. Here, the video signal voltage Vd is inverted in polarity for column and also inverted in polarity for each row. Consequently, pixels which are inverted in polarity adjoin to one another in the vertical and horizontal directions to reduce a flicker and crosstalk (horizontal smear).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a high picture quality and having a thin film transistor element.

[0002]

2. Description of the Related Art In a so-called horizontal electric field type color liquid crystal display device, a region corresponding to one or both liquid crystal unit pixels of a transparent substrate disposed opposite to each other with a liquid crystal layer interposed therebetween. A surface is provided with a display electrode and a reference electrode, and light transmitted through the liquid crystal layer is modulated by an electric field generated between the display electrode and the reference electrode in parallel with the transparent substrate surface. is there. Such a color liquid crystal display device can recognize a clear image even when viewed from a large angle field of view with respect to its display surface, and has come to be known as having a so-called wide angle field of view.

A liquid crystal display device having such a configuration is disclosed in, for example, Japanese Patent Application Laid-Open Nos. Hei 5-505247, Japanese Patent Publication No. 63-21907, and Japanese Unexamined Patent Publication No. Hei.
This is described in detail in JP-A-160878.

[0004]

However, in the liquid crystal display device configured as described above, an unnecessary electric field generated from the video signal line causes the electric field between the display electrode and the reference electrode to fluctuate, so that the display surface is not changed. However, there still remains a problem that a so-called vertical smear (crosstalk) occurs, which is a poor image quality in which stripes are formed in a band along the video signal line. Means for solving this problem is described in detail in JP-A-6-202127. However, in the liquid crystal display element configured as described above, since the shield electrode is provided and an electric potential is supplied to the shield electrode from the outside, a large amount of current is charged and discharged to and from the capacitor between the shield electrode and the signal electrode. The load becomes too large, the power consumption becomes too large, or the drive circuit becomes too large, and furthermore, a connection means for applying a potential to the shield electrode is required, which leads to an increase in the number of steps and poor connection. Had remained.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a liquid crystal display element which can suppress so-called vertical smear, has good productivity, and has low power consumption. Is to do.

[0006]

In order to achieve the above object, according to the present invention, as a first configuration, a plurality of pixels each including a plurality of video signal lines and a plurality of scanning electrodes are provided. An active matrix type liquid crystal display device having a pixel electrode and a counter electrode capable of applying an electric field parallel to the substrate surface and capable of supplying a video signal from a thin film transistor connected to a video signal line and a scanning signal line to the pixel electrode. Has a conductive light-shielding film on the opposite surface of the video signal line, and the polarity of the video signal voltage applied to the adjacent video signal line is the same,
An active matrix type liquid crystal display device characterized by being inverted is constituted.

As a second structure including the first structure, the conductive light-shielding film forms an active matrix type liquid crystal display device having a laminated structure of chromium, chromium nitride, and chromium oxide.

As a third configuration including the first configuration, an active matrix type liquid crystal display device in which the polarity inversion cycle of the video signal voltage of the video signal line is equal to or longer than every two scanning periods is provided.

As a fourth configuration including the first configuration, an active matrix type liquid crystal display device in which alternating-current rectangular waves whose polarities are inverted to each other are applied to opposing electrodes of pixels adjacent to each other in the longitudinal direction of the scanning electrode.

As a fifth configuration including the fourth configuration, an active matrix type liquid crystal display device in which the polarity inversion cycle of the AC rectangular wave is equal to or longer than every two scanning periods is provided.

In the liquid crystal display device thus constructed, first, a conductive light-shielding film (in a state of being completely superimposed on a video signal line formed on one transparent substrate side in a plan view) is used. Since the (black matrix) is formed on the other transparent substrate side, unnecessary lines of electric force generated from the video signal lines terminate in the black matrix. FIG. 1 is a schematic diagram showing the principle.

Further, by using a driving method in which a signal whose polarity is inverted for each column is applied to a video signal line, a voltage generated by capacitive coupling between the video signal line and the light-shielding film is applied to a video signal line of an adjacent column. Since the polarity and the voltage generated by the capacitive coupling between the light-shielding films are inverted, a cancel current flows between the light-shielding films, so that the potential of the light-shielding film does not change. As a result, unnecessary electric field lines can be shielded without applying an external voltage to the light-shielding film, so that the electric field between the display electrode and the reference electrode does not fluctuate depending on the video signal, So-called vertical smear can be suppressed. FIG. 2 is a schematic diagram of the principle.

An advantage of the present invention is that it is not necessary to apply a voltage to the light-shielding film from the outside, so that means for applying a voltage to the light-shielding film from the outside becomes unnecessary, and the occurrence of a defect such as a connection failure associated therewith is also eliminated. Disappears.

Also, since only a cancel current is generated in the light-shielding film, no current flows into and out of the light-shielding film, so that power consumption is suppressed and the load as viewed from the video signal line is reduced. The drive circuit can be reduced in size.

FIG. 3A shows the distribution of the transmittance in the left and right direction due to the electric field of the video signal line when an insulating light-shielding film is used. As shown in the figure, generation of transmitted light due to the electric field of the video signal line extends to 26 μm from the center of the video signal line. On the other hand, FIG. 3B shows the distribution of the transmittance in the left-right direction due to the electric field of the video signal line when a conductive light-shielding film is used. When the conductive BM is used, the area affecting transmission light of the display unit is reduced to 14 μm and 12 μm. Therefore, since the width of the light-shielding film can be reduced from 52 μm to 28 μm, the aperture ratio can be greatly increased, and both high aperture ratio and low smear can be achieved.

[0016]

BRIEF DESCRIPTION OF THE DRAWINGS The invention, further objects of the invention and further features of the invention will become apparent from the following description with reference to the drawings, in which: FIG.

(Embodiment 1) << Active matrix liquid crystal display device >> An embodiment in which the present invention is applied to an active matrix type color liquid crystal display device will be described below. In the drawings described below, components having the same function are denoted by the same reference numerals, and repeated description thereof will be omitted.

<< Planar Configuration of Matrix Part (Pixel Part) >> FIG. 4 is a plan view showing one pixel of the active matrix type color liquid crystal display device of the present invention and its periphery.

As shown in FIG. 4, each pixel has a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode line) CL, and two adjacent video signal lines (drain). The signal line or the vertical signal line) is arranged in an intersecting region with the DL (in a region surrounded by four signal lines). Each pixel is a thin film transistor TFT, a storage capacitor Cst
g, pixel electrode PX (referred to as a pixel electrode in this embodiment,
That is, the display electrode) and the counter electrode CT
(In this embodiment, it is called a counter electrode, that is, a reference electrode). The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in FIG. The video signal lines DL extend in the up-down direction, and a plurality of video signal lines DL are arranged in the left-right direction. The pixel electrode PX is electrically connected to the thin film transistor TFT via the source electrode SD1, and the counter electrode CT is also electrically connected to the counter voltage signal line CL.

The pixel electrode PX and the counter electrode CT face each other, and the optical state of the liquid crystal composition LC is controlled by an electric field generated between each pixel electrode PX and the counter electrode CT and substantially parallel to the substrate surface. Control the display. The pixel electrode PX and the counter electrode CT are formed in a comb shape, and each is an electrode that is elongated in the vertical direction in the figure.

The electrode width of each of the pixel electrode PX and the counter electrode CT is 6 μm. In order to apply a sufficient electric field to the entire liquid crystal layer in the thickness direction of the liquid crystal layer, the thickness is set to be sufficiently larger than 3.9 μm of a liquid crystal composition layer described later. Desirably, the thickness is set to 1.5 times or more of the liquid crystal composition layer. In addition, it is made as thin as possible to increase the aperture ratio. The video signal line DL is also 6 μm. The line width of the video signal line DL may be slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection.

The line width of the scanning signal line GL is set so as to satisfy a resistance value enough to transmit a scanning voltage to a gate electrode GT of a terminal pixel (opposite to a scanning electrode terminal GTM described later). . Further, the counter voltage signal line CL also has a resistance value that allows a sufficient counter voltage to be applied to the counter electrode CT of the terminal pixel (the pixel farthest from the later-described common bus lines CB1 and CB2, that is, the pixel between CB1 and CB2). Set the line width to satisfy.

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. this is,
Since the electric field strength that achieves the maximum transmittance varies depending on the liquid crystal material, the electrode spacing is set according to the liquid crystal material, and within the range of the maximum amplitude of the signal voltage set by the withstand voltage of the video signal driving circuit (signal side driver) used. , So that the maximum transmittance can be obtained. When a liquid crystal material described later is used, the electrode interval is about 12 μm.

<< Cross-Sectional Structure of Matrix (Pixel) >> FIG. 5 is a cross-sectional view taken along the line 6-6 in FIG. 4, and FIG. 6 is a cross-sectional view of the thin film transistor TFT taken along the line 7-7 in FIG. 7 is the storage capacitance C at the 8-8 section line in FIG.
It is a figure showing the section of stg. As shown in FIGS.
The lower transparent glass substrate SU based on the liquid crystal composition layer LC
A thin film transistor TFT, a storage capacitor Cstg, and an electrode group are formed on the B1 side, and a color filter FIL and a light shielding film (black matrix) BM are formed on the upper transparent glass substrate SUB2 side.

Further, the transparent glass substrates SUB1, SUB2
Alignment films AF1 and AF2 for controlling the initial alignment of the liquid crystal are provided on the inner surface (on the liquid crystal LC side) of each of the above, and a polarizing plate is provided on each outer surface of the transparent glass substrates SUB1 and SUB2. Is provided.

<< TFT Substrate >> First, the structure of the lower transparent glass substrate SUB1 (TFT substrate) will be described in detail.

<< Thin Film Transistor TFT >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is set to zero.

As shown in FIG. 6, the thin film transistor TFT has a gate electrode GT, an insulating film GI, an i-type (intrinsic, intr
It has an insic, i-type semiconductor layer AS made of amorphous silicon (Si not doped with a conductivity type determining impurity), a pair of source electrode SD1, and a drain electrode SD2. In addition,
It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are switched during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

<< Gate Electrode GT >> The gate electrode GT is formed continuously with the scanning signal line GL.
Is configured to be a gate electrode GT. The gate electrode GT is a portion beyond the active area of the thin film transistor TFT. In this example, the gate electrode GT
Is formed of a single-layer conductive film g3. As the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used, but not limited thereto.

<< Scanning Signal Line GL >> The scanning signal line GL is made of a conductive film g3. The conductive film g3 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally formed. This scanning signal line G
By L, a gate voltage (scanning voltage) Vg is supplied from an external circuit to the gate electrode GT. In this example, as the conductive film g3, for example, a chromium-molybdenum alloy (Cr-Mo) film formed by sputtering is used. Also, the scanning signal line G
The L and the gate electrode GT are not limited to the chromium-molybdenum alloy, but may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum for low resistance. further,
The portion that intersects with the video signal line DL is thinned to reduce the probability of short circuit with the video signal line DL.
It may be bifurcated so that it can be separated by laser trimming.

<< Counter Voltage Signal Line CL >> Counter Voltage Signal Line C
L is composed of a conductive film g3. The conductive film g3 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is configured to be electrically connected to the counter electrode CT. I have. The counter voltage Vcom is supplied from the external circuit to the counter electrode CT through the counter voltage signal line CL. Also,
The counter voltage signal line CL is not limited to the chromium-molybdenum alloy, but may have a two-layer structure in which aluminum or an aluminum alloy is wrapped with chromium-molybdenum for low resistance. Further, the portion that intersects with the video signal line DL may be narrowed in order to reduce the probability of a short circuit with the video signal line DL, or may be bifurcated so that even if a short circuit occurs, it can be separated by laser trimming.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI includes the gate electrode GT and the scanning signal line GL.
Is formed in the upper layer. As the insulating film GI, for example, a silicon nitride film formed by plasma CVD is selected.
000-4500 mm (in this embodiment, 3500
Å) formed. Further, the insulating film GI is provided with the scanning signal line G.
It also functions as an interlayer insulating film between the L and counter voltage signal lines CL and the video signal lines DL, and contributes to their electrical insulation.

<< i-type semiconductor layer AS >> i-type semiconductor layer AS
Is amorphous silicon and is formed to a thickness of 150 to 2500 ° (about 1200 ° in this embodiment). The layer d0 is an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact, and is provided only in a region where the i-type semiconductor layer AS is present on the lower side and the conductive layer d3 is present on the upper side. Has been left.

The i-type semiconductor layer AS and the layer d0 are also provided between the scanning signal line GL and the intersection (crossover portion) between the counter voltage signal line CL and the video signal line DL. The i-type semiconductor layer AS at the intersection is provided with the scanning signal line GL, the counter voltage signal line CL, and the video signal line D at the intersection.
Short circuit with L is reduced.

<< Source electrode SD1, drain electrode SD
2 >> Each of the source electrode SD1 and the drain electrode SD2 is formed of a conductive film d3 which is in contact with the N (+) type semiconductor layer d0.

The conductive film d3 is made of chromium-
Using a molybdenum alloy (Cr-Mo) film,
It is formed to a thickness of 00 ° (about 2500 ° in this embodiment). Since the Cr-Mo film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring.

Further, the Cr—Mo film is an N (+) type semiconductor layer d.
The adhesiveness with 0 is also good. As the conductive film d3, Cr-
In addition to the Mo film, a high melting point metal (Mo, Ti, Ta, W) film,
Refractory metal silicide (MoSi ₂ , TiSi ₂ , TaS
i _2, WSi ₂₎ film may be used, or may be a laminated structure with aluminum or the like.

<< Video Signal Line DL >> The video signal line DL is a conductive film d3 of the same layer as the source electrode SD1 and the drain electrode SD2.
It is composed of The video signal line DL is formed integrally with the drain electrode SD2. In this example, the conductive film d
3 is a chromium-molybdenum alloy (Cr
-Mo) The film is formed to a thickness of 500 to 3000 ° (about 2500 ° in this embodiment) using a film. Cr-Mo
Since the film has low stress, it can be formed relatively thick, which contributes to lowering the resistance of the wiring. Further, the Cr—Mo film has good adhesion to the N (+) type semiconductor layer d0. As the conductive film d3, a refractory metal (Mo,
Ti, Ta, W) film, refractory metal silicide (MoSi)
₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film, or a laminated structure with aluminum or the like to prevent disconnection.

<< Storage Capacitor Cstg >> The conductive film d3 is formed so as to overlap the counter voltage signal line CL in the source electrode SD2 portion of the thin film transistor TFT. This superposition constitutes a storage capacitor (capacitance element) Cstg in which the source electrode SD2 (d3) is used as one electrode and the counter voltage signal CL is used as the other electrode, as is clear from FIG. The dielectric film of the storage capacitor Cstg is an insulating film G used as a gate insulating film of the thin film transistor TFT.
I.

As shown in FIG. 4, the storage capacitance Cst
g is formed in a part of the counter voltage signal line CL.

<< Protective Film PSV1 >> Thin Film Transistor TF
On T, a protective film PSV1 is provided. Protective film PS
V1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a material having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 0.1 to 1 μm.

The protective film PSV1 is connected to external connection terminals DTM,
Removed to expose GTM. Protective film PSV1
And the thickness of the insulating film GI, the former is made thicker in consideration of the protection effect, and the latter is made thinner in consideration of the transconductance gm of the transistor.

In the pixel portion, through holes TH2 and TH1 are provided for electrical connection between the counter voltage signal line CL and a counter electrode CT described later, and for electrical connection between the source electrode SD2 and the pixel electrode PX. Provided. In the through hole TH2, since the protective film PSV1 and the insulating film GI are processed at a time, a hole up to the g3 layer is formed, and the through hole TH2 is formed.
In the case of 1, since blocking is performed at d3, holes are formed up to the d3 layer.

The protective film PSV1 may have a laminated structure with a thick organic film such as polyimide.

<< Pixel Electrode PX >> The pixel electrode PX is formed of the transparent conductive layer i1. This transparent conductive film i1 is a transparent conductive film (Indium-Tin-Oxide) formed by sputtering.
It is made of ITO (a Nesa film) and is formed to a thickness of 100 to 2000 （(in this embodiment, about 1400 、 １). The pixel electrode PX is connected to the source electrode SD2 via the through hole TH1.

When the pixel electrode is made transparent as in the present embodiment, the maximum transmittance in white display is improved due to the transmitted light in that portion, so that the pixel electrode is brighter than when the pixel electrode is opaque. Display can be performed. At this time, as described later, when no voltage is applied, the liquid crystal molecules maintain the initial alignment state, and the arrangement of the polarizers is set so as to perform black display in that state (normal black mode). Even if the pixel electrode is transparent, it is possible to display high-quality black without transmitting light in that portion. Thereby, the maximum transmittance can be improved and a sufficient contrast ratio can be achieved.

<< Counter Electrode CT >> The counter electrode CT is formed of the transparent conductive layer i1. This transparent conductive film i1 is a transparent conductive film (Indium-Tin-Oxide) formed by sputtering.
It is made of ITO (a Nesa film) and is formed to a thickness of 100 to 2000 （(in this embodiment, about 1400 、 １). The counter electrode CT is connected to the counter voltage signal line CL via the through hole TH2. Pixel electrode P
Similarly to X, by making the opposing electrode transparent, the maximum transmittance when white display is performed is improved.

The counter electrode CT is configured to apply a counter voltage Vcom. In this embodiment, the counter voltage V
com is a potential lower than the intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL by a feedthrough voltage ΔVs generated when the thin film transistor element TFT is turned off. Is set to

<< Color Filter Substrate >> Next, FIGS.
Returning to, the configuration of the upper transparent glass substrate SUB2 side (color filter substrate) will be described in detail.

<< Light shielding film BM >> Upper transparent glass substrate SUB
On the second side, an unnecessary gap (pixel electrode PX and counter electrode CT)
Transmitted light from the gap other than the gap between
A light-shielding film BM (a so-called black matrix) is formed so as not to lower the contrast ratio and the like. Light shielding film B
M indicates that the external light or the backlight light is the i-type semiconductor layer AS
It also plays a role in preventing light from entering. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light-shielding films BM and the large gate electrode GT, so that external natural light or backlight does not shine.

FIG. 4 shows an example of a pattern of the light shielding film BM.

The light-shielding film BM is formed of a metal film having conductivity and light-shielding properties, and is formed in a matrix pattern in which holes are formed in a display portion of a pixel. In this embodiment, the light shielding film BM is
Use a chromium thin film. Chromium oxide and chromium nitride are formed on the glass surface side of the chromium thin film. This is to reduce the reflectance on the glass surface side and to reduce the reflection of the display surface of the liquid crystal display device. Further, the light shielding film BM is configured to completely cover the video signal line DL, and most of the lines of electric force from the video signal line DL are terminated in the light shielding film BM. In this state, the potential of the light-shielding film BM fluctuates due to the potential of the video signal line DL. Therefore, crosstalk is not reduced. However, the portion extending in the left-right direction of the light-shielding film BM causes a reverse effect from the adjacent video signal line DL. Between the potential fluctuations of the polarity, a current flows that cancels each other out,
The potential of the light shielding film BM is stabilized. Thereby, the pixel electrode P
The electric field between X and the counter electrode CT does not receive the fluctuation of the potential of the video signal line DL. Therefore, crosstalk is greatly reduced. This is an effect newly generated by using the driving method in which the polarity of the video signal applied to the video signal line DL is reversed for each column by using the conductive light shielding film BM as described above. This is an effect unique to an active matrix type liquid crystal display device using a horizontal electric field method. According to the present invention, the light-shielding film B
Since the width of M in the left-right direction can be made 30 μm or less, the aperture ratio can be greatly improved. Therefore, in the present embodiment, an aperture ratio of about 40% could be obtained with a 13.3 diagonal XGA resolution.

The effective display area of each row is partitioned by the light shielding film BM. Therefore, the contour of the pixel in each row is
M clarifies. Furthermore, the light-shielding film BM is .i
It also has a light shielding function for the type semiconductor layer AS.

Further, in the present invention, since a metal film (0.05 to 0.2 μm) having a high light-shielding property is used even if it is a thin film, the unevenness of the color filter uses an insulating light-shielding film (1 to 3 μm). Since the thickness becomes smaller and the flatness increases, the thickness of the liquid crystal layer becomes uniform, and the unevenness of the luminance due to the change in the thickness of the liquid crystal layer is eliminated.

The light-shielding film BM is also formed in a frame shape at the peripheral portion, and its pattern is formed continuously with the pattern of the matrix portion shown in FIG. The light-shielding film BM at the peripheral portion is extended outside the seal portion SL to prevent leakage light such as reflected light due to a mounting machine such as a personal computer from entering the matrix portion, and light from the backlight or the like to the display area. It also prevents it from leaking outside. On the other hand, this light shielding film BM is
It is held about 0.3 to 1.0 mm inside the edge of B2, and is formed avoiding the cutting area of the substrate SUB2.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel. The color filter FIL is formed so as to overlap the edge portion of the light shielding film BM.

The color filter FIL can be formed as follows. First, a dye base such as an acrylic resin is formed on the surface of the upper transparent glass substrate SUB2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red pigment and subjected to a fixing treatment to form a red filter R. Next, a green filter G and a blue filter B are sequentially formed by performing a similar process. Note that a dye may be used for dyeing.

<< Overcoat Film OC >> The overcoat film OC is a liquid crystal composition layer L of the dye of the color filter FIL.
C is provided to prevent leakage to C and to flatten a step due to the color filter FIL and the light shielding film BM.
The overcoat film OC is formed of a transparent resin material such as an acrylic resin and an epoxy resin. Further, as the overcoat film OC, an organic film such as polyimide having good fluidity may be used. The thickness of the overcoat film OC is usually about 2 μm. However, in order to exhibit the effect of the present invention, the thinner the light shielding film BM is, the closer to the video signal line DL. Since the electric lines of force from the video signal lines DL do not spread in the horizontal direction (lateral direction) with the substrate and terminate at the light shielding film BM, the shielding efficiency is improved. Specifically, it is preferable that the thickness be from 0.2 μm which can provide flatness to 1.0 μm or less which can sufficiently maintain the shielding efficiency.

<< Liquid Crystal Layer and Polarizing Plate >> Next, the liquid crystal layer, the alignment film, the polarizing plate and the like will be described.

<< Liquid Crystal Layer >> The liquid crystal material LC has a positive dielectric anisotropy Δε of 13.2 and a refractive index anisotropy Δn of 0.0.
A nematic liquid crystal of 81 (589 nm, 20 ° C.) is used. The thickness (gap) of the liquid crystal layer is 3.9 μm, and the retardation Δn · d is 0.316. By the value of this retardation Δn · d, the maximum transmittance can be obtained when the liquid crystal molecules are rotated by 45 ° from the rubbing direction to the electric field direction in combination with the alignment film and the polarizing plate described later, and the wavelength dependence within the visible light range. It is possible to obtain transmitted light having little property. The range of this retardation is preferably in the range of 0.25 to 0.32 μm in order to obtain sufficient transmitted light.

The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

The liquid crystal material LC is not particularly limited, and the dielectric anisotropy Δε may be negative. In addition, the larger the value of the dielectric anisotropy Δε, the lower the driving voltage. In addition, the smaller the refractive index anisotropy Δn, the thicker the gap (gap) of the liquid crystal layer, the shorter the liquid crystal filling time, and the smaller the gap variation.

The specific resistance of the liquid crystal composition is 10
⁹ [Omega] cm or more ^{10 1 4} [Omega] cm or less, preferably ^{10 1 1}
[Omega] cm or more ^{10 1 3} [Omega] cm using the following things. In this method, even at low resistance of the liquid crystal composition, the voltage charged between the pixel electrode and the counter electrode can be sufficiently held, the lower limit of 10 ⁹ [Omega] cm, preferably 10 ^{1 1} [Omega] cm. This is because the pixel electrode and the counter electrode are formed on the same substrate. Further, when the resistance is too high, the hard alleviate static electricity entering the production process, 10 ^{1 4} .omega.c
m or less, preferably ^{10 1 3} [Omega] cm or less.

It is preferable that the twist elastic constant K2 of the liquid crystal material is small. Specifically, 2pN or more is good.

<< Orientation Film >> Polyimide is used as the orientation film ORI. The rubbing direction RDR is parallel to the upper and lower substrates, and the angle between the rubbing direction RDR and the applied electric field direction EDR is 75.
°. FIG. 20 shows the relationship.

The angle between the rubbing direction RDR and the applied electric field direction EDR is 45 ° or more and less than 90 ° when the dielectric anisotropy Δε of the liquid crystal material is positive.
If is negative, it must be greater than 0 ° and less than or equal to 45 °.

<< Polarizing Plate >> As the polarizing plate POL, the polarization transmission axis MAX1 of the lower polarizing plate POL1 is set in the rubbing direction R.
DR and the polarization transmission axis M of the upper deflector POL2.
AX2 is made orthogonal to it. FIG. 3 shows the relationship.
Accordingly, as the voltage (voltage between the pixel electrode PX and the counter electrode CT) applied to the pixel of the present invention increases,
It is possible to obtain a normally closed characteristic in which the transmittance is increased, and it is possible to display a high quality black display when no voltage is applied.
The relationship between the upper and lower polarizing plates may be reversed, and there is no significant change in characteristics.

In this embodiment, a display failure due to external static electricity and a measure against EMI are taken by imparting conductivity to the polarizing plate. Regarding the conductivity, the sheet resistance is desirably set to 10 ⁸ Ω / b or less if only to take measures against the influence of static electricity, and is set to 10 ⁴ Ω / b or less if EMI is also taken. Further, a conductive layer may be provided on the back surface (the surface on which the polarizing plate is adhered) of the sandwiching surface of the liquid crystal composition of the glass substrate.

<< Structure around the Matrix >> FIG. 8 is a diagram showing a main part plane around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. FIG. 9 is a diagram showing a cross section near the external connection terminal GTM to which the scanning circuit is to be connected on the left side, and a cross section near the seal portion where there is no external connection terminal on the right side.

[0070] Any For this panel In the manufacture of, if small size divided from simultaneously processing a plurality fraction of the device in one glass substrate for increased throughput, manufacturing facilities if large size shared A glass substrate of a standardized size is processed even in a variety, and the size is reduced to a size suitable for each type. In each case, the glass is cut after passing through one process. 8 and 9 show an example of the latter. Both FIGS. 8 and 9 show the upper and lower substrates SUB1 and SUB.
2 shows the state after cutting, and LN indicates the edge of both substrates before cutting. In any case, in the completed state, the external connection terminal group T
The size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so that g, Td, and the terminal COT (subscripts omitted) (the upper side and the left side in the figure) are exposed so that they are exposed. The terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DTM described later.
A tape carrier package TCP on which an integrated circuit chip CHI is mounted (see FIGS. 19 and 2)
A plurality of units are collectively named in the unit of 0). The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is because the terminals DTM of the display panel PNL are arranged at the arrangement pitch of the package TCP and the connection terminal pitch of each package TCP.
This is for matching GTM. Also, the counter electrode terminal CO
T is a terminal for applying a counter voltage to the counter electrode CT from an external circuit. Counter voltage signal line CL in matrix section
Are drawn out on the opposite side (right side in the figure) of the scanning circuit terminal GTM, and the common voltage signal lines are grouped together by a common bus line CB and connected to the common electrode terminal COT.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal filling opening INJ, the liquid crystal LC
The seal pattern SL is formed so as to seal.
The sealing material is made of, for example, an epoxy resin.

The layers of the orientation films ORI1 and ORI2 are formed inside the seal pattern SL. Polarizing plates POL1, P
OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.
The liquid crystal LC is a lower alignment film ORI for setting the direction of liquid crystal molecules.
1 and the upper alignment film ORI2 are sealed in a region partitioned by a seal pattern SL. Lower alignment film ORI1
Is formed on the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and the seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped, liquid crystal LC is injected from the opening INJ of the sealing material SL, the injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are sealed. Assembled by cutting.

<< Gate Terminal Portion >> FIG. 10 is a diagram showing a connection structure from the scanning signal line GL of the display matrix to its external connection terminal GTM, (A) is a plan view, and (B) is a diagram of (A). FIG. 3 shows a cross-sectional view taken along the line BB. This figure corresponds to the vicinity of the lower part of FIG. 8, and the diagonal wiring portion is represented by a straight line for convenience.

In the figure, the Cr-Mo layer g3 is hatched for easy understanding.

The gate terminal GTM has a Cr—Mo layer g3,
Further, the surface is protected and TCP (Tape Ca
(rear package) and a transparent conductive layer i1 for improving the reliability of connection. This transparent conductive layer i1 uses a transparent conductive film ITO formed in the same step as the pixel electrode PX.

In the plan view, the insulating film GI and the protective film PSV1 are formed on the right side of the boundary line, and the terminal portion GTM located on the left end is exposed therefrom so that it can make electrical contact with an external circuit. Has become. In the figure, only one pair of the gate line GL and the gate terminal is shown. However, in practice, a plurality of such pairs are arranged vertically as shown in FIG. 8 to form a terminal group Tg (FIG. 8). In the manufacturing process, the left end of the gate terminal extends beyond the cutting region of the substrate and is short-circuited by a wiring SHg (not shown). This is useful for preventing electrostatic breakdown at the time of rubbing of the alignment film ORI1 in the manufacturing process.

<< Drain Terminal DTM >> FIGS. 11A and 11B are diagrams showing the connection from the video signal line DL to the external connection terminal DTM, FIG. 11A is a plan view thereof, and FIG. FIG. 3 shows a cross-sectional view taken along section line B. FIG. 8 shows FIG.
Corresponding to the vicinity of the upper right, the direction of the drawing is changed for convenience, but the right end corresponds to the upper end of the substrate SUB1.

TSTd is an inspection terminal, which is not connected to an external circuit, but is wider than a wiring portion so that a probe needle or the like can be contacted. Similarly, the drain terminal D
The TM is also wider than the wiring part so that it can be connected to an external circuit. The external connection drain terminals DTM are arranged in the vertical direction, and the drain terminals DTM constitute a terminal group Td (subscript omitted) as shown in FIG. 5 and are further extended beyond the cutting line of the substrate SUB1. All of them are short-circuited to each other by a wiring SHd (not shown) to prevent electrostatic breakdown. The inspection terminal TSTd is formed on every other video signal line DL as shown in FIG.

The drain connection terminal DTM is connected to the transparent conductive layer i1.
The portion where the protective film PSV1 is removed is connected to the video signal line DL. This transparent conductive film i1 uses a transparent conductive film ITO formed in the same step as the pixel electrode PX, as in the case of the gate terminal GTM.

The lead wiring from the matrix portion to the drain terminal portion DTM is connected to the layer d3 of the same level as the video signal line DL.
Is configured.

<< Counter Electrode Terminal CTM >> FIGS. 12A and 12B are diagrams showing the connection from the counter voltage signal line CL to the external connection terminal CTM, FIG. 12A is a plan view thereof, and FIG. FIG. 4 shows a cross-sectional view taken along the line BB. This figure corresponds to the vicinity of the upper left of FIG.

Each common voltage signal line CL is connected to a common bus line C
B1 collectively leads to the counter electrode terminal CTM. The common bus line CB has a structure in which the conductive layer 3 is stacked on the conductive layer g3, and they are electrically connected by the transparent conductive layer i1. This reduces the resistance of the common bus line CB, and the opposing voltage is supplied from an external circuit to each opposing voltage signal line CL.
In order to be supplied sufficiently. This structure is characterized in that the resistance of the common bus line can be reduced without particularly adding a new conductive layer.

The counter electrode terminal CTM has a structure in which a transparent conductive layer i1 is laminated on a conductive layer g3. This transparent conductive film i1 uses a transparent conductive film ITO formed in the same step as the pixel electrode PX, as in the case of the other terminals. The conductive layer g3 is covered with the transparent conductive layer i1 having good durability in order to protect the surface with the transparent conductive layer i1 and prevent electrolytic corrosion and the like. The connection between the transparent conductive layer i1 and the conductive layers g3 and d3 is made conductive by forming through holes in the protective film PSV1 and the insulating film GI.

On the other hand, FIG. 13 is a diagram showing the connection from the other end of the counter voltage signal line CL to the external connection terminal CTM2, (A) is a plan view, and (B) is (A). 2 is a sectional view taken along line BB of FIG. This figure corresponds to the vicinity of the upper right of FIG. Here, in the common bus line CB2, the other end (the gate terminal GTM side) of each counter voltage signal line CL is put together to form the counter electrode terminal CTM2.
Has been drawn to. The difference from the common bus line CB1 is that the conductive layer d3 is insulated from the scanning signal line GL.
And the transparent conductive layer i1. Further, insulation with the scanning signal line GL is performed by the insulating film GI.

<< Equivalent Circuit of Entire Display Device >> FIG. 14 shows a connection diagram of the equivalent circuit of the display matrix portion and its peripheral circuits.
Although the figure is a circuit diagram, it is drawn corresponding to an actual geometric arrangement. AR is a matrix array in which a plurality of pixels are two-dimensionally arranged.

In the figure, X represents a video signal line DL, and suffixes G, B and R are added corresponding to green, blue and red pixels, respectively. Y indicates the scanning signal line GL, and the suffixes 1, 2, 3,..., End are added according to the order of the scanning timing.

The scanning signal line Y (subscript omitted) is connected to the vertical scanning circuit V, and the video signal line X (subscript omitted) is connected to the video signal driving circuit H.

The SUP uses a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source and information for a CRT (cathode ray tube) from a host (upper processing unit) as a TFT liquid crystal display device. This is a circuit that includes a circuit that exchanges information for use.

<< Driving Method >> FIG. 15 shows a driving waveform of the liquid crystal display device of this embodiment. The counter voltage VC is a constant voltage. The scanning signal VG takes an on level every scanning period, and takes an off level in the other scanning periods. The video signal voltage is applied so that the positive and negative polarities are inverted every frame and transmitted to one pixel with twice the amplitude of the voltage to be applied to the liquid crystal layer.
Here, the polarity of the video signal voltage Vd is inverted for each column,
The polarity is also inverted for each row. As a result, pixels having inverted polarities are arranged vertically and horizontally, so that flicker and crosstalk (smear in the left and right directions) can be suppressed. In addition, the counter voltage Vc is set to a voltage that is reduced by a fixed amount from the center voltage of the polarity inversion of the video signal voltage. This is to correct the feed-through voltage generated when the thin film transistor element changes from on to off, and is performed to apply an AC voltage having a small DC component to the liquid crystal. , Deterioration, etc.).

<< Function of Storage Capacitance Cstg >> Storage Capacitance Cstg
Is provided in order to accumulate video information (after the thin film transistor TFT is turned off) written in the pixel for a long time.
In the method of applying an electric field parallel to the substrate surface used in the present invention, unlike the method of applying the electric field perpendicular to the substrate surface, there is almost no capacitance (so-called liquid crystal capacitance) formed by the pixel electrode and the counter electrode. However, the storage capacity Cstg cannot store video information in the pixel. Therefore, in a system in which an electric field is applied in parallel with the substrate surface, the storage capacitor Cstg is an essential component.

The storage capacitor Cstg also works to reduce the effect of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.

ΔVs = {Cgs / (Cgs + Cstg + Cpix)} × ΔVg where Cgs is the gate electrode G of the thin film transistor TFT.
Parasitic capacitance formed between T and the source electrode SD1, C
pix represents a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs represents a so-called feed-through voltage corresponding to a change in pixel electrode potential due to ΔVg. This change ΔVs causes a DC component applied to the liquid crystal LC, but the storage capacitance Cst
The larger the value of g, the smaller the value. The reduction of the DC component applied to the liquid crystal LC
The life of C can be improved, and so-called burn-in in which the previous image remains when the liquid crystal display screen is switched can be reduced.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the overlap area with the source electrode SD1 and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The pixel electrode potential Vs is susceptible to the gate (scanning) signal Vg. However, this disadvantage can be eliminated by providing the storage capacitor Cstg.

<< Manufacturing Method >> Next, a method of manufacturing the liquid crystal display device on the substrate SUB1 side will be described with reference to FIGS.
This will be described with reference to FIG. In the same figure, the letters at the center are abbreviations of the process names, and the left side shows the processing flow as viewed from the cross-sectional shape near the gate terminal shown in FIG. Except for Step B and Step D, Step A to Step I are classified according to each photographic process, and any cross-sectional view of each process shows a stage where the processing after the photographic process is completed and the photoresist is removed. . In the present description, photographic processing refers to a series of operations from application of a photoresist to selective exposure using a mask to development thereof, and a repeated description will be omitted. Description will be given below according to the divided steps.

Step A, FIG. 16 On the lower transparent glass substrate SUB1 made of AN635 glass (trade name), a conductive film g3 made of Cr—Mo or the like having a thickness of 2000 ° is provided by sputtering. After the photographic processing, the conductive film g3 is selectively etched with ceric ammonium nitrate. Thereby, the gate electrode GT, the scanning signal line GL, the counter voltage signal line CL, the gate terminal GTM,
First conductive layer of common bus line CB1, counter electrode terminal CT
A bus line SHg (not shown) connecting the first conductive layer of M1 and the gate terminal GTM is formed.

Step B, FIG. 16 An ammonia gas, a silane gas and a nitrogen gas are introduced into a plasma CVD apparatus to provide a Si nitride film having a thickness of 3500 °, and a silane gas and a hydrogen gas are introduced into the plasma CVD apparatus to form a film. After providing an i-type amorphous Si film having a thickness of 1200 °, a hydrogen gas and a phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 300 °.

Step C, FIG. 16 After photographic processing, SF6 and CC were used as dry etching gases.
N @ + type amorphous Si film using i @ 4, i type amorphous Si
By selectively etching the film, islands of the i-type semiconductor layer AS are formed.

Step D, FIG. 17 A conductive film d3 made of Cr having a thickness of 300 ° is provided by sputtering. After the photographic processing, the conductive film d3 is etched with the same liquid as in step A, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the first conductive layer of the common bus line CB2, and the bus line for short-circuiting the drain terminal DTM. SHd (not shown) is formed. Next, the N (+) type semiconductor layer d0 between the source and the drain is selectively removed by introducing CCl4 and SF6 into the dry etching apparatus and etching the N (+) type amorphous Si film. .
After patterning the conductive film d3 with a mask pattern, the N (+) type semiconductor layer d0 is removed using the conductive film d3 as a mask. That is, the N remaining on the i-type semiconductor layer AS
In the (+) type semiconductor layer d0, portions other than the conductive films d1 and d2 are removed by self-alignment. At this time, since the N (+)-type semiconductor layer d0 is etched so as to entirely remove the thickness thereof, the surface of the i-type semiconductor layer AS is also slightly etched, but the degree is controlled by the etching time. do it.

Step E, FIG. 17 An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 0.4 μm-thick Si nitride film. After photo processing, SF6 is used as dry etching gas.
Then, the protective film PSV1 and the insulating film GI are patterned by selectively etching the Si nitride film using the method described above. Here, the protective film PSV1 and the insulating film GI are patterned with the same photomask and are processed collectively.

Step F, FIG. 18 A transparent conductive film i1 made of an ITO film having a thickness of 1400 ° is provided by sputtering. After the photographic processing, the transparent conductive film i1 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the counter electrode terminal CTM1.
And a second conductive layer of CTM2 is formed.

<< Display Panel PNL and Drive Circuit Board PCB
1 >> FIG. 19 is a top view showing a state where the video signal driving circuit H and the vertical scanning circuit V are connected to the display panel PNL shown in FIG. 8 and the like.

CHI is a drive IC chip for driving the display panel PNL (the lower five are drive ICs on the vertical scanning circuit side)
The left and right chips are the driving I on the video signal driving circuit side.
C chip). TCP is a tape carrier package in which a driving IC chip CHI is mounted by a tape automated bonding method (TAB), as will be described later with reference to FIGS. 16 and 17, and PCB1 is a driving circuit in which the above-described TCP, capacitors and the like are mounted. The substrate is divided into two, one for a video signal drive circuit and one for a scan signal drive circuit. FG
P is a frame ground pad, and a shield case S
A spring-shaped fragment provided by cutting into the HD is soldered. FC is a flat cable that electrically connects the lower drive circuit board PCB1 and the left drive circuit board PCB1. As shown in the drawing, a flat cable FC is used in which a plurality of lead wires (phosphor bronze material plated with Sn) are sandwiched and supported by a striped polyethylene layer and a polyvinyl alcohol layer.

<< Connection Structure of TCP >> FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP which forms the scanning signal drive circuit V and the video signal drive circuit H and has the integrated circuit chip CHI mounted on a flexible wiring board. Yes,
FIG. 21 is a cross-sectional view of a main part of the liquid crystal display panel, showing a state where it is connected to a scanning signal circuit terminal GTM in this example.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, for example, made of Cu. ) Is the integrated circuit C
The HI bonding pads PAD are connected by a so-called face-down bonding method. Terminal TTB, T
The outer ends (commonly called outer leads) of the TM correspond to the input and output of the semiconductor integrated circuit chip CHI, respectively.
CRT / TFT conversion circuit / power supply circuit S by soldering
A liquid crystal display panel P is formed on the UP by using an anisotropic conductive film ACF.
NL. The package TCP has a protective film PS whose leading end exposes the connection terminal GTM on the panel PNL side.
Since the external connection terminal GTM (DTM) is covered with at least one of the protection film PSV1 and the package TCP, the external connection terminal GTM (DTM) is covered with the panel so as to cover V1.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is washed and protected by an epoxy resin EPX or the like, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicone resin SIL to multiplex protection.

<< Drive Circuit Board PCB2 >> Drive Circuit Board P
The CB2 has electronic components such as an IC, a capacitor, and a resistor mounted thereon. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a CR (Crystal Control Unit) from a host (upper processing unit).
A circuit SUP including a circuit for converting information for T (cathode ray tube) into information for a TFT liquid crystal display device is mounted. C
J is a connector connection portion to which a connector (not shown) connected to the outside is connected.

The drive circuit board PCB1 and the drive circuit board PC
B2 is electrically connected by a flat cable FC.

<< Overall Configuration of Liquid Crystal Display Module >> FIG.
FIG. 3 is an exploded perspective view showing each component of the liquid crystal display module MDL.

SHD is a frame-shaped shield case (metal frame) made of a metal plate, LCW and its display window, PNL is a liquid crystal display panel, SPB is a light diffusion plate, LCB is a light guide,
RM is a reflection plate, BL is a backlight fluorescent tube, LCA is a backlight case, and the respective members are stacked in a vertical arrangement as shown in the figure to assemble a module MDL.

The module MDL is a shield case SH
The entirety is fixed by claws and hooks provided on D.

The backlight case LCA includes a backlight fluorescent tube BL, a light diffusion plate SPB, a light diffusion plate, a light guide LCB,
The light guide LCB has a shape to accommodate the reflection plate RM.
The light of the backlight fluorescent tube BL arranged on the side surface is made uniform on the display surface by the light guide LCB, the reflection plate RM, and the light diffusion plate SPB, and emitted to the liquid crystal display panel PNL side.

An inverter circuit board PCB3 is connected to the backlight fluorescent tube BL, and serves as a power supply for the backlight fluorescent tube BL.

As is apparent from the above description, the liquid crystal display device of this embodiment suppresses so-called vertical smear, which is an essential problem in a liquid crystal display device having an ultra-wide viewing angle using a horizontal electric field method. However, power consumption and peripheral circuit scale can be reduced at the same time.

(Embodiment 2) This embodiment is the same as Embodiment 1 except for the following requirements. FIG. 23 shows a plan view of a pixel. The hatched portion in the figure indicates the transparent conductive film i1.

<< Counter Electrode CT >> In this embodiment, the counter electrode CT is formed integrally with the counter voltage signal line CL by the conductive film g3.

In this embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but the counter electrode CT and the counter voltage signal line C
L contact failure can be avoided. Further, since one of the electrodes is covered with the insulating film (protective film PSV1), the possibility that a direct current flows through the liquid crystal when there is an alignment film defect is reduced, the liquid crystal is not degraded, and the reliability is improved.

(Embodiment 3) This embodiment is the same as Embodiment 1 except for the following requirements. FIG. 24 shows a plan view of a pixel.

<< Pixel Electrode PX >> In this embodiment, the pixel electrode PX is formed of the same conductive film d3 as the source electrode SD1 and the drain electrode SD2. Further, the pixel electrode PX is formed integrally with the source electrode SD1.

<< Counter Electrode CT >> In this embodiment, the counter electrode CT is formed integrally with the counter voltage signal line CL by the conductive film g3.

In this embodiment, in addition to the effects of the first embodiment, the transmittance is sacrificed, but the pixel electrode PX and the source electrode SD1
In addition, a contact failure between the counter electrode CT and the counter voltage signal line CL can be avoided.
In addition, since both electrodes are covered with the insulating film (protective film PSV1), the possibility of direct current flowing through the liquid crystal when there is an alignment film defect is reduced, and the liquid crystal is not deteriorated.
The reliability is further improved as compared with.

(Embodiment 4) This embodiment is the same as Embodiment 1 except for the following.

<< Driving Method >> FIG. 25 shows a driving waveform of the liquid crystal display device of this embodiment. In this embodiment, the polarity of the video signal voltage Vd is inverted for each column as in the first embodiment, but unlike the first embodiment, the polarity is inverted for each frame without being inverted for each row. Let it. Also in this embodiment, since the pixels whose polarities are inverted are arranged on the left and right sides, flicker and crosstalk (horizontal smear) can be hardly generated as in the first embodiment.

In this embodiment, in addition to the effects of the first embodiment,
Since the cycle of the polarity inversion of the video signal can be lengthened by the number of rows, the frequency of the polarity inversion of the video signal becomes 1 / number of rows. Since the power consumption for charging / discharging the video signal to / from the video signal line DL is proportional to the frequency of the polarity inversion, the power consumption of the driving IC chip of the video signal driving circuit is greatly reduced. In addition, since the driving capability of the driving IC chip can be reduced, the circuit scale of the driving IC chip can be reduced, and the frame of the liquid crystal display panel can be a narrow frame.

Further, in the present embodiment, the polarity of the video signal is inverted for each frame. However, the same effect as in the present embodiment can be obtained as long as it is equal to or longer than every two scanning periods.

(Embodiment 5) This embodiment is the same as Embodiment 1 except for the following.

<< Planar Configuration of Matrix Section (Pixel Section) >> FIG. 26 is a plan view showing one pixel of the active matrix type color liquid crystal display device of this embodiment and its periphery.

In the present embodiment, unlike the first embodiment, the counter voltage signal lines CL extend in the vertical direction in the figure and are arranged in a plurality in the horizontal direction. Further, the counter voltage signal line CL is formed of the same material in the same layer as the video signal line DL.

In this embodiment, half of each common voltage signal line CL is collectively connected to the common bus line CB1 and the common electrode line C
The other half has been drawn to TM1. The common bus line CB2 collectively leads to the counter electrode terminal CTM2.

<< Equivalent Circuit of Entire Display Device >> FIG. 27 shows a connection diagram of an equivalent circuit of the display matrix portion and its peripheral circuits.

In the present embodiment, half of each of the common voltage signal lines CL is grouped together by the common bus line CB1 and the common electrode line C
The other half has been drawn to TM1. The common bus line CB2 collectively leads to the counter electrode terminal CTM2. In the present embodiment, two different driving waveforms are used.
Various voltages are applied to the counter electrode terminals CTM1 and CTM2, and are applied to the counter electrode CT.

<< Driving Method >> FIG. 28 shows a driving waveform of the liquid crystal display device of this embodiment. An AC voltage is applied to the counter voltage Vch, and rectangular waves whose phases are shifted from each other by 180 ° are applied to the counter electrode terminals CTM1 and CTM2 to Vch1 and Vch2, respectively. The video signal voltage Vd is inverted in polarity for each column and inverted for each row as in the first embodiment. However, unlike the first embodiment, the video signal line DL is connected to the liquid crystal layer. Of the voltages to be applied, only the voltage at the portion where the transmittance of the liquid crystal display panel changes need be applied, and the maximum amplitude of the voltage applied to the video signal line DL can be reduced to １ ／ or less.

Since the power consumption is proportional to the square of the driving voltage, the power consumption can be reduced to １ ／ or less. In addition, since the withstand voltage of the driving IC chip of the video signal driving circuit can be reduced to 5 V or less, a driving IC chip with good mass productivity can be used, and the mass productivity of the entire liquid crystal display device is improved. be able to.

If the driving method according to the second embodiment is adopted,
The same effects as in the second embodiment can be obtained, and further lower power consumption can be achieved. In addition to the effects of the present embodiment, the circuit scale of the driving IC chip can be further reduced, and the frame can be narrowed.

Further, in this embodiment, the polarity of the video signal and the polarity of the AC rectangular wave are inverted for each column. The effect of is obtained.

[0136]

As is apparent from the above description,
In the liquid crystal display device of this embodiment, suppressing so-called vertical smear, which is an essential problem in a liquid crystal display device with an ultra-wide viewing angle using a horizontal electric field method, reduces power consumption and reduces the scale of peripheral circuits. Can be achieved at the same time.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing an operation 1 of the present invention.

FIG. 2 is a schematic diagram showing an operation 2 of the present invention.

FIG. 3 is a diagram illustrating a distribution of transmittance in the left-right direction due to an electric field of a video signal line. (A) In the case of a conductive light shielding film, (b)
In the case of an insulating light-shielding film.

FIG. 4 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in the active matrix type color liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a pixel taken along section line 6-6 in FIG. 4;

FIG. 6 is a cross-sectional view of the thin film transistor element TFT taken along section line 7-7 in FIG.

FIG. 7 is a cross-sectional view of the storage capacitor Cstg taken along section line 8-8 in FIG. 4;

FIG. 8 is a plan view for explaining a configuration of a matrix peripheral portion of the display panel.

FIG. 9 is a cross-sectional view showing a scanning signal terminal on the left side and a panel edge portion without an external connection terminal on the right side.

FIG. 10 is a plan view and a cross-sectional view showing the vicinity of a connection portion between a gate terminal GTM and a gate wiring GL.

FIG. 11 is a plan view and a sectional view showing the vicinity of a connection portion between a drain terminal DTM and a video signal line DL.

FIG. 12 shows a common electrode terminal CTM1 and a common bus line CB.
FIG. 2 is a plan view and a cross-sectional view showing the vicinity of a connection portion between the first and common voltage signal lines CL.

FIG. 13 shows a common electrode terminal CTM2 and a common bus line CB.
2A and 2B are a plan view and a cross-sectional view showing the vicinity of a connection portion between the second and common voltage signal lines CL.

FIG. 14 is a circuit diagram including a matrix portion and its periphery of the active matrix type color liquid crystal display device of the present invention.

FIG. 15 is a diagram showing driving waveforms of the active matrix type color liquid crystal display device according to the first embodiment of the present invention.

FIG. 16 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing a manufacturing process of processes A to C on the substrate SUB1 side.

FIG. 17 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes D to F on the substrate SUB1 side.

FIG. 18 is a flowchart of a cross-sectional view of a pixel portion and a gate terminal portion showing manufacturing processes of processes G to H on the substrate SUB1 side.

FIG. 19 is a top view showing a state where peripheral driving circuits are mounted on a liquid crystal display panel.

FIG. 20 is a diagram showing a cross-sectional structure of a tape carrier package TCP in which an integrated circuit chip CHI constituting a drive circuit is mounted on a flexible wiring board.

FIG. 21 is a cross-sectional view of a main part showing a state where the tape carrier package TCP is connected to a scanning signal circuit terminal GTM of the liquid crystal display panel PNL.

FIG. 22 is an exploded perspective view of the liquid crystal display module.

FIG. 23 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix color liquid crystal display device according to a second embodiment of the present invention.

FIG. 24 is a main part plan view showing one pixel of a liquid crystal display unit and its periphery in an active matrix type color liquid crystal display device according to a third embodiment of the present invention.

FIG. 25 is a diagram showing driving waveforms of the active matrix type color liquid crystal display device according to the second embodiment of the present invention.

FIG. 26 is a plan view of a principal part showing one pixel of a liquid crystal display unit and its periphery in an active matrix color liquid crystal display device according to a third embodiment of the present invention;

FIG. 27 is a circuit diagram including a matrix portion and its periphery of the active matrix type color liquid crystal display device of the present invention.

FIG. 28 is a diagram showing driving waveforms of the active matrix type color liquid crystal display device according to the third embodiment of the present invention.

[Explanation of symbols]

SUB: transparent glass substrate, GL: scanning signal line, DL: video signal line, CL: counter voltage signal line, PX: pixel electrode, C
T: counter electrode, GI: insulating film, GT: gate electrode, A
S: i-type semiconductor layer, SD: source or drain electrode, PSV: protective film, BM: light shielding film, LC: liquid crystal, TF
T: thin film transistor, PH: through hole, g, d ...
Conductive film, Cstg: storage capacitance, AOF: anodic oxide film, AO
... anodization mask, GTM ... gate terminal, DTM ... drain terminal, CB ... common bus line, DTM ... common electrode terminal, SHD ... shield case, PNL ... liquid crystal display panel, SPB ... light diffusion plate, LCB ... light guide, BL: Backlight fluorescent tube; LCA: Backlight case; RM: Reflector (abbreviated above).

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁶ Identification code FI G09G 3/36 G09G 3/36 (72) Inventor Norihisa Ono 3300 Hayano, Mobara-shi, Chiba Pref. 72) Inventor Hiroaki Asuma 3300 Hayano Mobara-shi, Chiba Electronic Device Division, Hitachi, Ltd.

Claims (7)

[Claims] A plurality of pixels including a plurality of video signal lines and a plurality of scanning electrodes, wherein the pixel has a pixel electrode and a counter electrode capable of applying an electric field parallel to a substrate surface; In an active matrix liquid crystal display device in which a video signal can be supplied from a thin film transistor connected to the video signal line and the scanning signal line to the pixel electrode, a conductive light shielding film is provided on a surface facing the video signal line. An active matrix type liquid crystal display device, wherein the polarities of video signal voltages applied to adjacent video signal lines are mutually inverted during the same period. 2. The active matrix type liquid crystal display device according to claim 1, wherein said conductive light-shielding film has a laminated structure of chromium, chromium nitride, and chromium oxide. 3. The active matrix type liquid crystal display device according to claim 1, wherein the period of the polarity inversion of the video signal voltage of said video signal line is at least every two scanning periods. 4. The active matrix type liquid crystal display device according to claim 1, wherein alternating rectangular waves having opposite polarities are applied to opposing electrodes of pixels adjacent in the longitudinal direction of the scanning electrodes. 5. The active matrix type liquid crystal display device according to claim 4, wherein the polarity inversion cycle of said AC rectangular wave is at least every two scanning periods. 6. The light-shielding film has a thickness of 0.05 μm to 0.5 μm.
6. The active matrix liquid crystal display device according to claim 1, wherein the thickness is 2 μm. 7. The active matrix type liquid crystal display device according to claim 1, wherein a horizontal width of said light shielding film is 30 μm or less.