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JPH1145907A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH1145907A
JPH1145907A JP9201652A JP20165297A JPH1145907A JP H1145907 A JPH1145907 A JP H1145907A JP 9201652 A JP9201652 A JP 9201652A JP 20165297 A JP20165297 A JP 20165297A JP H1145907 A JPH1145907 A JP H1145907A
Authority
JP
Japan
Prior art keywords
layer
tab
semiconductor element
wiring board
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9201652A
Other languages
Japanese (ja)
Other versions
JP3441340B2 (en
Inventor
Katsura Hayashi
桂 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP20165297A priority Critical patent/JP3441340B2/en
Publication of JPH1145907A publication Critical patent/JPH1145907A/en
Application granted granted Critical
Publication of JP3441340B2 publication Critical patent/JP3441340B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4092Integral conductive tabs, i.e. conductive parts partly detached from the substrate

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacture thereof which can conveniently realize at a high productivity the mounting of semiconductor elements on a lead wiring layer formed on a multilayer wiring board having an insulation board made of an insulation material contg. an org. resin, and which is applicable to MCMs. SOLUTION: The semiconductor device having TAB-connected semiconductor elements is manufactured by TAB-connecting semiconductor elements 6 to a lead wiring layer 4 of a TAB tape 5 which is composed of a metal foil 3 formed on a transfer film 1, transferring the lead wiring layer 4 having the TAB-connected semiconductor elements 6 to the surface of an unhardened multilayer board 7 having a wiring circuit layer 10 and via-hole conductors 11 for electrically interconnecting the wiring layers on an insulation board 9 having laminated insulation layers contg. thermosetting resins, and heating it to perfectly harden the wiring board.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば、多層配線
基板に半導体素子を搭載した半導体装置と、その製造方
法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, for example, a semiconductor device having a semiconductor element mounted on a multilayer wiring board and a method of manufacturing the same.

【0002】[0002]

【従来技術】従来より、半導体素子収納用パッケージ
は、絶縁基板の一部にシリコンチップ等の半導体素子を
収納するためのキャビティが形成され、そのキャビティ
内の絶縁基板表面には、配線回路層が被着形成されてお
り、この配線回路層に半導体素子が実装される。
2. Description of the Related Art Conventionally, in a package for housing a semiconductor element, a cavity for housing a semiconductor element such as a silicon chip is formed in a part of an insulating substrate, and a wiring circuit layer is formed on the surface of the insulating substrate in the cavity. The semiconductor element is mounted on the wiring circuit layer.

【0003】半導体素子の実装方法としては、ワイヤー
ボンディングが最も一般的であるが、ワイヤボンディン
グによる場合、接続パッドは200μm程度のピッチが
必要なので、それより小さいピッチでの接続が難しくな
り、小型化に対応できないものであった。また、個々の
端子間を接続する必要があるために、接続に要する時間
が長くなり、生産性が落ちるという問題があった。
[0003] Wire bonding is the most common method of mounting a semiconductor element. However, in the case of wire bonding, a connection pad needs to have a pitch of about 200 µm. It was not able to respond to. Further, since it is necessary to connect the individual terminals, there is a problem that the time required for the connection is lengthened and the productivity is reduced.

【0004】そこで、最近では、TAB(tape automat
ed bonding)といわれる方法も実用化されている。この
TAB接続法は、所定箇所に半導体素子を収納する穴が
設けられたポリイミド樹脂などのフィルムの全面に金属
箔を接着した後、この金属箔をホトエッチングにより半
導体素子の接続するためのインナーリードとアウターリ
ードからなるリード配線層が形成された,いわゆるTA
Bテープに対して、半導体素子のバンプとインナーリー
ドとを接続する方法である。この方法は、半導体素子と
リードとを一度の接続処理で接続できることから、短時
間で接続できるため、量産性に優れ、また、金メッキし
た端子を圧着するので、不純物の混入が少なく、信頼性
の点で優れている。また、半田などの鉛合金を含まない
ので、環境への負荷が少ない点でも優れている。さら
に、TAB(tape automated bonding )は60μm
程度のピッチでも接続が可能でしかも短時間に一括して
接続が可能である点でも優れている。
Therefore, recently, TAB (tape automat)
A method called ed bonding) has also been put to practical use. In this TAB connection method, a metal foil is adhered to the entire surface of a film of a polyimide resin or the like in which a hole for accommodating a semiconductor element is provided at a predetermined position, and then the metal foil is subjected to an inner lead for connecting the semiconductor element by photoetching. So-called TA on which a lead wiring layer composed of
This is a method of connecting bumps and inner leads of a semiconductor element to a B tape. In this method, since the semiconductor element and the lead can be connected in a single connection process, the connection can be made in a short time, so that mass production is excellent, and since the gold-plated terminal is crimped, contamination of impurities is small, and reliability is improved. Excellent in point. In addition, since it does not contain a lead alloy such as solder, it is also excellent in that the load on the environment is small. Furthermore, TAB (tape automated bonding) is 60 μm
It is also excellent in that connection can be made even at a small pitch and connection can be made collectively in a short time.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、従来の
TAB接続は、TABテープと呼ばれる銅箔を片面に接
着したポリイミド樹脂フィルムを使用することのみ実現
可能な接続方法であるため、リード配線層を展開する際
に接続端子を設ける領域が狭いために、接続端子が50
0を越えると、パッケージ自体が大きくなりすぎる問題
があった。
However, the conventional TAB connection is a connection method that can be realized only by using a polyimide resin film having a copper foil adhered to one side, which is called a TAB tape. When the connection terminal is provided, the area for providing the connection terminal is small,
If it exceeds 0, there is a problem that the package itself becomes too large.

【0006】また、最近では、半導体素子を搭載した配
線基板の小型化および多素子化に対して、MCM(マル
チチップモジュール)と呼ばれる1つの基板に多数の半
導体素子を実装した配線基板が要求されているが、TA
Bテープのように、片面のみに銅箔を接着したポリイミ
ド樹脂フィルムでは、導体および支持体となるポリイミ
ド樹脂がそれぞれ1層のみからなるため、回路の交差が
不可能であり、多層化および多素子化が難しいものであ
った。このため、半導体素子の多ピン化と、MCMが普
及するに伴い、TAB接続はその優れた特性にもかかわ
らず、衰退すると推測されている。このため、最近で
は,MCMにも対応できる接続方法として、半田によっ
て半導体素子と基板とを半田バンプにより接続する方法
や、導電性接着剤を使用して半導体素子の接続を行うス
タッドバンプボンディング、導電性粒子を配合した異方
性導電性シートなどを利用した各種フリップチップ接続
が開発されてつつある。しかし、これらはいずれも複雑
な工程を経て実現可能なもので作業性は極度に悪化す
る。また、これらの実施にあたっては新たな設備投資が
必要であり、コストダウンの観点からは不利であった。
In recent years, in order to reduce the size and increase the number of wiring boards on which semiconductor elements are mounted, a wiring board called an MCM (multi-chip module) in which a large number of semiconductor elements are mounted on one board has been required. But TA
In the case of a polyimide resin film having a copper foil adhered to only one side, such as a B tape, the conductor and the polyimide resin serving as a support consist of only one layer each. Was difficult. For this reason, with the increase in the number of pins of the semiconductor element and the spread of the MCM, it is estimated that the TAB connection will decline despite its excellent characteristics. For this reason, recently, as a connection method compatible with MCM, a method of connecting a semiconductor element and a substrate by solder bumps by solder, a method of connecting a semiconductor element by using a conductive adhesive, a stud bump bonding, Various flip-chip connections using an anisotropic conductive sheet mixed with conductive particles are being developed. However, all of these can be realized through complicated steps, and workability is extremely deteriorated. In addition, these implementations require new capital investment, which is disadvantageous from the viewpoint of cost reduction.

【0007】従って、本発明は、有機樹脂を含む絶縁材
料からなる絶縁基板とする多層配線基板に対して、半導
体素子のリード配線層への実装を簡便で高い生産性をも
って実現することのできるとともに、MCMに適用可能
な半導体装置とその製造方法を提供するものである。
Accordingly, the present invention can easily and with high productivity mount a semiconductor element on a lead wiring layer for a multilayer wiring board which is an insulating substrate made of an insulating material containing an organic resin. , An MCM, and a method of manufacturing the same.

【0008】[0008]

【課題を解決するための手段】本発明者は、半導体素子
のリード配線層への実装方法について鋭意検討した結
果、転写フィルム表面に金属箔をエッチングしてリード
配線層を形成したTABテープに半導体素子をTAB接
続した後、それを多層配線基板表面に転写して形成する
ことにより簡便で生産性の高い半導体装置が作製できる
ことを見いだし、本発明に至った。
The inventor of the present invention has intensively studied a method of mounting a semiconductor element on a lead wiring layer, and has found that a TAB tape having a lead wiring layer formed by etching a metal foil on the surface of a transfer film. The inventors have found that a simple and highly productive semiconductor device can be manufactured by transferring the element to the surface of the multilayer wiring board and forming it after TAB connection of the element, and have reached the present invention.

【0009】即ち、本発明の半導体装置は、熱硬化性樹
脂を含有する複数の絶縁層を積層した絶縁基板と、該絶
縁基板表面に形成されたリード配線層と、前記絶縁基板
表面および/または内部に形成された配線回路層と、前
記配線回路層間を電気的に接続するためのビアホール導
体とを具備する多層配線基板と、前記リード配線層にT
AB接続された半導体素子とを具備することを特徴とす
るものであり、さらに前記絶縁基板表面のリード配線層
と半導体素子とが、転写フィルム表面にて前記半導体素
子と前記リード配線層をTAB接続した後、前記絶縁基
板表面に転写されたものであること、前記ビアホール導
体を、金属粉末を含む導体ペーストの充填によって形成
し、且つ前記配線回路層を金属箔により形成してなるこ
とを特徴とする。
That is, a semiconductor device according to the present invention comprises an insulating substrate having a plurality of insulating layers containing a thermosetting resin laminated thereon, a lead wiring layer formed on the surface of the insulating substrate, and the surface of the insulating substrate and / or A multilayer wiring board including a wiring circuit layer formed therein and a via hole conductor for electrically connecting the wiring circuit layers;
A semiconductor element connected to the semiconductor substrate and an AB connection, wherein the lead wiring layer and the semiconductor element on the surface of the insulating substrate are connected by a TAB connection between the semiconductor element and the lead wiring layer on the surface of the transfer film. And then transferred to the surface of the insulating substrate, the via-hole conductor is formed by filling a conductive paste containing metal powder, and the wiring circuit layer is formed of metal foil. I do.

【0010】また、本発明の半導体装置の製造方法は、
転写フィルム表面に、金属箔からなるリード配線層を形
成したTABテープを作製する工程と、該TABテープ
の前記リード配線層に半導体素子をTAB接続する工程
と、熱硬化性樹脂を含有する複数の絶縁層を積層した絶
縁基板に、配線回路層と、該配線回路層間を電気的に接
続するためのビアホール導体とが形成された未硬化状態
の多層配線基板を作製する工程と、前記半導体素子をT
AB接続したTABテープを前記多層配線基板表面に積
層した後、前記転写フィルムを剥がすことにより、前記
リード配線層とそれにTAB接続された半導体素子とを
前記多層配線基板表面に転写する工程と、該多層配線基
板を加熱して完全硬化する工程とを具備することを特徴
とするものである。
Further, the method of manufacturing a semiconductor device according to the present invention comprises:
A step of producing a TAB tape in which a lead wiring layer made of a metal foil is formed on the surface of the transfer film, a step of TAB connecting a semiconductor element to the lead wiring layer of the TAB tape, and a plurality of steps containing a thermosetting resin. Forming an uncured multilayer wiring board in which a wiring circuit layer and a via-hole conductor for electrically connecting the wiring circuit layers are formed on an insulating substrate having an insulating layer laminated thereon; and T
After laminating the AB-connected TAB tape on the surface of the multilayer wiring board, peeling off the transfer film to transfer the lead wiring layer and the semiconductor element TAB-connected thereto to the surface of the multilayer wiring board; Heating and completely curing the multilayer wiring board.

【0011】[0011]

【発明の実施の形態】以下、本発明を図面をもとに説明
する。図1は、本発明における半導体装置を製造するた
めの工程を説明するための図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a view for explaining steps for manufacturing a semiconductor device according to the present invention.

【0012】本発明によれば、まず、TABテープを準
備する。このTABテープは、例えば、図1(a)に示
すように、まず、樹脂フィルム1に対して、半導体素子
を実装する箇所に穴2を形成し、その穴2を含むフィル
ム1表面に金属箔3を接着する。その後、図1(b)に
示すように、その金属箔をフォトエッチング(ドライフ
ィルムなどのフォトレジストを用いた銅箔をエッチング
し、回路を形成する方法)等を用いて、半導体素子と接
続可能なリード配線層4を形成する。このリード配線層
4は、一般には、半導体素子が実装されるインナーリー
ド4aと、外部電気回路に接続するためのアウターリー
ド4bから構成され、インナーリード4aは、フィルム
1に設けられた穴2内に延設される。その結果、図1
(a)に示されるようなTABテープ5が作製される。
According to the present invention, first, a TAB tape is prepared. In this TAB tape, for example, as shown in FIG. 1A, first, a hole 2 is formed at a position where a semiconductor element is mounted on a resin film 1, and a metal foil is 3 is adhered. Thereafter, as shown in FIG. 1B, the metal foil can be connected to the semiconductor element by photo-etching (a method of forming a circuit by etching a copper foil using a photoresist such as a dry film). A suitable lead wiring layer 4 is formed. The lead wiring layer 4 generally includes an inner lead 4a on which a semiconductor element is mounted and an outer lead 4b for connecting to an external electric circuit. Will be extended. As a result, FIG.
A TAB tape 5 as shown in FIG.

【0013】なお、リード配線層4を形成する樹脂フィ
ルム1は、ポリエステル、ポリエチレンテレフタレー
ト、ポリイミド、ポリフェニレンサルファイド、塩化ビ
ニル、ポリプロピレン等公知のものが使用できる。樹脂
フィルムの厚みは、10〜500μmが適当であり、望
ましくは20〜300μmが良い。これは、樹脂フィル
ムの厚みが10μmより小さいとフィルムの変形や折れ
曲がりにより形成したリード配線層が断線を引き起こし
易くなり、厚みが500μmより大きいとフィルムの柔
軟性がなくなるため転写時のフィルムの剥離が難しくな
るためである。
The resin film 1 for forming the lead wiring layer 4 may be a known one such as polyester, polyethylene terephthalate, polyimide, polyphenylene sulfide, vinyl chloride, and polypropylene. The thickness of the resin film is suitably from 10 to 500 μm, and preferably from 20 to 300 μm. This is because when the thickness of the resin film is less than 10 μm, the lead wiring layer formed by deformation or bending of the film is liable to cause disconnection, and when the thickness is more than 500 μm, the flexibility of the film is lost, so that peeling of the film at the time of transfer is difficult. Because it becomes difficult.

【0014】この樹脂フィルム1の表面の金属箔3の接
着は、アクリル系、ゴム系、シリコン系、エポキシ系等
公知の接着剤が使用できる。また、接着層の厚みは、接
着力とも関係するが、1〜20μmが適当である。ま
た、上記樹脂フィルム上に、PVD、メッキなどの方法
で直接銅を被着形成したものであってもよい。
For bonding the metal foil 3 on the surface of the resin film 1, a known adhesive such as an acrylic, rubber, silicon, epoxy or the like can be used. Although the thickness of the adhesive layer is related to the adhesive strength, it is preferably 1 to 20 μm. Alternatively, copper may be directly formed on the resin film by a method such as PVD or plating.

【0015】次に、図1(c)に示すように、このTA
Bテープ5に、半導体素子6を実装する。実装には、半
導体素子6に金メッキを施したバンプを形成した後、T
ABテープ5の穴2内に設置して、同じく金メッキを施
したインナーリード4aと加圧圧着することにより強固
に接続される。所望によりTAB接続後の半導体素子6
をエポキシ樹脂等の封止材で保護してもよい。
Next, as shown in FIG.
The semiconductor element 6 is mounted on the B tape 5. For mounting, after forming a gold-plated bump on the semiconductor element 6, T
It is placed in the hole 2 of the AB tape 5 and is firmly connected to the inner lead 4a, which is also plated with gold, by pressure and pressure bonding. Semiconductor element 6 after TAB connection if desired
May be protected by a sealing material such as an epoxy resin.

【0016】一方、図1(d)に示すような多層配線基
板を作製する。この多層配線基板7は、熱硬化性樹脂を
含有する複数の絶縁層8を積層した絶縁基板9の表面お
よび内部に複数の配線回路層10と、該配線回路層10
間を電気的に接続するためのビアホール導体11とを具
備するものであり、その表面は、熱硬化性樹脂や半硬化
または未硬化状態であることが必要である。
On the other hand, a multilayer wiring board as shown in FIG. The multilayer wiring board 7 includes a plurality of wiring circuit layers 10 on the surface and inside of an insulating substrate 9 on which a plurality of insulating layers 8 containing a thermosetting resin are laminated.
And a via-hole conductor 11 for electrically connecting between them, and the surface thereof needs to be a thermosetting resin or a semi-cured or uncured state.

【0017】このような多層配線基板7は、例えば、図
2(a)に示すように、まず、熱硬化性樹脂を含む軟質
(Bステージ状態)の絶縁層21を作製する。また、こ
の絶縁層21には、所望により厚み方向に貫通するビア
ホールを形成し、そのビアホール内に金属粉末を含む導
体ペーストをスクリーン印刷や吸引処理しながら充填し
て、ビアホール導体11を形成する。ビアホールの形成
は、ドリル、パンチング、サンドブラスト、あるいは炭
酸ガスレーザ、YAGレーザ、及びエキシマレーザ等の
照射による加工など公知の方法が採用される。
For such a multilayer wiring board 7, for example, as shown in FIG. 2A, first, a soft (B-stage) insulating layer 21 containing a thermosetting resin is prepared. Further, a via hole penetrating in the thickness direction is formed in the insulating layer 21 as required, and the via hole conductor 11 is formed by filling the via hole with a conductive paste containing a metal powder while performing screen printing or suction processing. A well-known method such as drilling, punching, sandblasting, or processing by irradiation with a carbon dioxide gas laser, a YAG laser, an excimer laser, or the like is used for forming the via hole.

【0018】次に、図2(b)に示すように、絶縁層2
1の表面に配線回路層10を形成して単層の配線基板2
2を作製する。配線回路層10は、1)絶縁層21の表
面に金属箔を貼り付けた後、エッチング処理して回路パ
ターンを形成する方法、2)絶縁層21表面にレジスト
を形成して、メッキにより形成する方法、3)転写フィ
ルム表面に金属箔を貼り付け、金属箔をエッチング処理
して回路パターンを形成した後、この金属箔からなる回
路パターンを絶縁層21表面に転写させる方法等が挙げ
られる。その後、図2(c)に示すように、図2(a)
(b)と同様にしてビアホール導体または配線回路層を
形成した配線基板23、24を作製し、これを配線基板
22とともに積層する。
Next, as shown in FIG.
1 is a single-layer wiring board 2 having a wiring circuit layer 10 formed on the surface thereof.
2 is produced. The wiring circuit layer 10 is formed by: 1) a method of forming a circuit pattern by attaching a metal foil to the surface of the insulating layer 21 and then performing an etching process; 2) forming a resist on the surface of the insulating layer 21 and plating. Method 3) A method of attaching a metal foil to the surface of the transfer film, etching the metal foil to form a circuit pattern, and then transferring the circuit pattern made of the metal foil to the surface of the insulating layer 21. Thereafter, as shown in FIG.
Wiring boards 23 and 24 on which via-hole conductors or wiring circuit layers are formed are produced in the same manner as in (b), and these are laminated together with the wiring board 22.

【0019】図2に示した方法によって作製される多層
配線基板7は、熱硬化性樹脂を含む絶縁基板を用いなが
ら、ビアホール導体を任意の箇所に複数形成することが
できるとともに、ビアホール導体を金属箔からなる金属
層によって封止した構造からなるためにビアホール導体
の長期安定性に優れる等のメリットを有する。また、従
来のメッキに比較すると生産性が高く、有害が薬品も使
用することもない。
In the multilayer wiring board 7 manufactured by the method shown in FIG. 2, a plurality of via-hole conductors can be formed at arbitrary locations while using an insulating substrate containing a thermosetting resin. Since it has a structure sealed by a metal layer made of foil, it has advantages such as excellent long-term stability of the via-hole conductor. In addition, productivity is higher than conventional plating, and no harmful chemicals are used.

【0020】なお、図2の製造方法において、用いられ
る熱硬化性樹脂を含有する絶縁層は、熱硬化性樹脂、ま
たは熱硬化性樹脂とフィラーなどの組成物を混練機や3
本ロールなどの手段によって十分に混合し、これを圧延
法、押し出し法、射出法、ドクターブレード法などによ
ってシート状に成形する。そして、所望により熱処理し
て熱硬化性樹脂を半硬化させる。半硬化には、樹脂が完
全硬化するに十分な温度よりもやや低い温度に加熱す
る。
In the manufacturing method shown in FIG. 2, the insulating layer containing the thermosetting resin to be used is made of a thermosetting resin or a composition such as a thermosetting resin and a filler.
The mixture is sufficiently mixed by means such as a main roll and formed into a sheet by a rolling method, an extrusion method, an injection method, a doctor blade method, or the like. Then, the thermosetting resin is semi-cured by heat treatment if desired. For semi-curing, the resin is heated to a temperature slightly lower than a temperature sufficient to completely cure the resin.

【0021】なお、絶縁層を形成する熱硬化性樹脂とし
ては、絶縁材料としての電気的特性、耐熱性、および機
械的強度を有する熱硬化性樹脂であれば特に限定される
ものでなく、例えば、アラミド樹脂、フェノール樹脂、
エポキシ樹脂、イミド樹脂、フッ素樹脂、フェニレンエ
ーテル樹脂、ビスマイレイドトリアジン樹脂、ユリア樹
脂、メラミン樹脂、シリコーン樹脂、ウレタン樹脂、不
飽和ポリエステル樹脂、アリル樹脂等が、単独または組
み合わせて使用できる。
The thermosetting resin forming the insulating layer is not particularly limited as long as the thermosetting resin has electrical properties, heat resistance and mechanical strength as an insulating material. , Aramid resin, phenolic resin,
Epoxy resins, imide resins, fluororesins, phenylene ether resins, bismaleide triazine resins, urea resins, melamine resins, silicone resins, urethane resins, unsaturated polyester resins, allyl resins and the like can be used alone or in combination.

【0022】また、上記の絶縁層中には、絶縁基板ある
いは配線基板全体の強度を高めるために、有機樹脂に対
してフィラーを複合化させることもできる。有機樹脂と
複合化されるフィラーとしては、SiO2 、Al
2 3 、ZrO2 、TiO2 、AlN、SiC、BaT
iO3 、SrTiO3 、ゼオライト、CaTiO3 、ほ
う酸アルミニウム等の無機質フィラーが好適に用いられ
る。また、ガラスやアラミド樹脂からなる不織布、織布
などに上記樹脂を含浸させて用いてもよい。なお、有機
樹脂とフィラーとは、体積比率で15:85〜50:5
0の比率で複合化されるのが適当である。
In the above-mentioned insulating layer, a filler can be compounded with an organic resin in order to increase the strength of the entire insulating substrate or wiring substrate. SiO 2 , Al
2 O 3 , ZrO 2 , TiO 2 , AlN, SiC, BaT
Inorganic fillers such as iO 3 , SrTiO 3 , zeolite, CaTiO 3 and aluminum borate are preferably used. Further, a nonwoven fabric or a woven fabric made of glass or aramid resin may be used by impregnating the above resin. The organic resin and the filler are in a volume ratio of 15:85 to 50: 5.
Suitably, the compound is formed in a ratio of 0.

【0023】一方、ビアホール導体11を形成する金属
ペーストは、銅粉末、銀粉末、銀被覆銅粉末、銅銀合金
などの、平均粒径が0.5〜50μmの金属粉末を含
む。金属粉末の平均粒径が0.5μmよりも小さいと、
金属粉末同士の接触抵抗が増加してスルーホール導体の
抵抗が高くなる傾向にあり、50μmを越えるとスルー
ホール導体の低抵抗化が難しくなる傾向にある。
On the other hand, the metal paste forming via-hole conductor 11 includes metal powder having an average particle size of 0.5 to 50 μm, such as copper powder, silver powder, silver-coated copper powder, and copper-silver alloy. When the average particle size of the metal powder is smaller than 0.5 μm,
The contact resistance between the metal powders tends to increase and the resistance of the through-hole conductor tends to increase. If it exceeds 50 μm, it tends to be difficult to reduce the resistance of the through-hole conductor.

【0024】また、導体ペーストは、前述したような金
属粉末に対して、結合用有機樹脂や溶剤を添加混合して
調製される。ペースト中に添加される溶剤としては、用
いる結合用有機樹脂が溶解可能な溶剤であればよく、例
えば、イソプロピルアルコール、テルピネオール、2−
オクタノール、ブチルカルビトールアセテート等が用い
られる。
The conductive paste is prepared by adding an organic resin for binding and a solvent to the metal powder as described above. The solvent to be added to the paste may be any solvent that can dissolve the binding organic resin to be used. For example, isopropyl alcohol, terpineol, 2-
Octanol, butyl carbitol acetate and the like are used.

【0025】導体ペースト中の結合用有機樹脂として
は、前述した種々の絶縁層を構成する有機樹脂の他、セ
ルロースなども使用される。この有機樹脂は、前記金属
粉末同士を互いに接触させた状態で結合するとともに、
金属粉末を絶縁シートに接着させる作用をなしている。
この有機樹脂は、金属ペースト中において、0.1乃至
40体積%、特に0.3乃至30体積%の割合で含有さ
れることが望ましい。これは、樹脂量が0.1体積%よ
りも少ないと、金属粉末同士を強固に結合することが難
しく、低抵抗金属を絶縁層に強固に接着させることが困
難となり、逆に40体積%を越えると、金属粉末間に樹
脂が介在することになり粉末同士を十分に接触させるこ
とが難しくなり、ビアホール導体の抵抗が大きくなるた
めである。
As the organic resin for bonding in the conductor paste, cellulose and the like are used in addition to the above-mentioned organic resins constituting the various insulating layers. This organic resin is bonded while the metal powders are in contact with each other,
It functions to adhere the metal powder to the insulating sheet.
This organic resin is desirably contained in the metal paste at a ratio of 0.1 to 40% by volume, particularly 0.3 to 30% by volume. If the amount of the resin is less than 0.1% by volume, it is difficult to firmly bond the metal powders to each other, and it is difficult to firmly bond the low-resistance metal to the insulating layer. If it exceeds, the resin is interposed between the metal powders, making it difficult to bring the powders into sufficient contact with each other and increasing the resistance of the via-hole conductor.

【0026】次に、図1(e)に示すように、図1
(c)によって半導体素子6がTAB接続されたTAB
テープ5を多層配線基板7の表面に積層圧着した後、T
ABテープ5の樹脂フィルム1を剥がすことにより、多
層配線基板7の表面に、インナーリード4aとアウター
リード4bからなるリード配線層4とともに、半導体素
子6を多層配線基板7の表面に転写する。
Next, as shown in FIG.
TAB in which the semiconductor element 6 is TAB-connected by (c)
After the tape 5 is laminated and pressed on the surface of the multilayer wiring board 7,
By peeling off the resin film 1 of the AB tape 5, the semiconductor element 6 is transferred onto the surface of the multilayer wiring board 7 together with the lead wiring layer 4 including the inner leads 4a and the outer leads 4b.

【0027】そして、転写後の多層配線基板7を熱硬化
性樹脂が完全に硬化するに十分な温度で加熱して多層配
線基板を完全硬化させて、図1(f)の半導体素子6を
多層配線基板7に実装した半導体装置を作製することが
できる。
Then, the multilayer wiring board 7 after the transfer is heated at a temperature sufficient to completely cure the thermosetting resin, and the multilayer wiring board is completely cured, so that the semiconductor element 6 of FIG. A semiconductor device mounted on the wiring board 7 can be manufactured.

【0028】また、本発明の半導体装置において、リー
ド配線層4や、多層配線基板7の配線回路層10を形成
する金属層は、銅、アルミニウム、金、銀の群から選ば
れる少なくとも1種、または2種以上の合金からなるこ
とが望ましく、特に、銅、または銅を含む合金が最も望
ましい。また、場合によっては、導体組成物として回路
の抵抗調整のためにNi−Cr合金などの高抵抗の金属
を混合、または合金化してもよい。さらには、配線層の
低抵抗化のために、前記低抵抗金属よりも低融点の金
属、例えば、半田、錫などの低融点金属を導体組成物中
の金属成分中にて2〜20重量%の割合で含んでもよ
い。
In the semiconductor device of the present invention, the metal layer forming the lead wiring layer 4 and the wiring circuit layer 10 of the multilayer wiring board 7 is at least one selected from the group consisting of copper, aluminum, gold and silver. Or, it is desirable to be composed of two or more alloys, and particularly, copper or an alloy containing copper is most desirable. In some cases, a high-resistance metal such as a Ni—Cr alloy may be mixed or alloyed as the conductor composition for adjusting the resistance of the circuit. Further, in order to reduce the resistance of the wiring layer, a metal having a lower melting point than the low-resistance metal, for example, a low-melting metal such as solder or tin is used in an amount of 2 to 20% by weight in the metal component in the conductor composition. May be included.

【0029】前記配線層4の厚みは1〜100μmが良
く、望ましくは5〜50μmが良い。これらの金属層の
厚みが1μmより小さいとリードとしての抵抗率が高く
なり、また、100μmより大きいと、積層時に絶縁基
板の変形が大きくなったり、絶縁基板への金属層の埋め
込み量が多くなり、絶縁基板の歪みが大きくなり金属層
の埋め込み時に基板が変形を起こしやすいなどの問題が
ある。また、エッチングしにくくなるため精度のよい微
細な回路が得られないという問題もある。好適には、5
〜18μmのの電解銅箔が良好に用いられる。
The thickness of the wiring layer 4 is preferably 1 to 100 μm, and more preferably 5 to 50 μm. When the thickness of these metal layers is less than 1 μm, the resistivity as a lead increases, and when the thickness is more than 100 μm, the deformation of the insulating substrate during lamination increases or the amount of the metal layer embedded in the insulating substrate increases. In addition, there is a problem that the distortion of the insulating substrate is increased and the substrate is easily deformed when the metal layer is embedded. In addition, there is a problem that a fine circuit with high accuracy cannot be obtained because etching becomes difficult. Preferably 5
An electrolytic copper foil of 1818 μm is preferably used.

【0030】また、多層配線基板7とリード配線層4と
の密着強度を高める上では、多層配線基板7の絶縁層表
面の絶縁層のリード配線層4の転写箇所および/または
リード配線層4の表面粗さが0.1μm以上、特に0.
3μm〜3μm、最適には0.3〜1.5μmとなるよ
うに粗面加工することが望ましい。
In order to increase the adhesion strength between the multilayer wiring board 7 and the lead wiring layer 4, the transfer position of the lead wiring layer 4 of the insulating layer on the insulating layer surface of the multilayer wiring board 7 and / or the lead wiring layer 4 The surface roughness is 0.1 μm or more, especially 0.1 μm.
It is desirable to roughen the surface to a thickness of 3 μm to 3 μm, optimally 0.3 to 1.5 μm.

【0031】このように、本発明の半導体装置によれ
ば、半導体素子のリード配線層への実装を自動化が可能
なTAB接続によって行うと同時に、そのTAB接続構
造を転写させることにより、TAB接続による量産性に
優れた実装方法を多層配線基板に適用して半導体装置を
作製できる。それと同時に、1つの基板上の任意の箇所
にTAB接続された半導体素子を搭載させることができ
るために、多数の半導体素子をを実装するマルチチップ
モジュール(MCM)の作製の容易に行うことができ
る。さらに、実装に対して鉛合金を必要としないために
環境への負荷も少ない等のメリットを有する。
As described above, according to the semiconductor device of the present invention, mounting of the semiconductor element on the lead wiring layer is performed by TAB connection which can be automated, and at the same time, the TAB connection structure is transferred so that the semiconductor device is mounted on the lead wiring layer. A semiconductor device can be manufactured by applying a mounting method excellent in mass productivity to a multilayer wiring board. At the same time, since a semiconductor element connected by TAB can be mounted at an arbitrary position on one substrate, a multi-chip module (MCM) on which many semiconductor elements are mounted can be easily manufactured. . Further, there is an advantage that a load on the environment is small because a lead alloy is not required for mounting.

【0032】[0032]

【発明の効果】以上詳述した通り、本発明の半導体装置
は、熱硬化性樹脂を含有する複数の絶縁層を積層してな
る多層配線基板の表面に形成されたリード配線層に対し
て、TAB接続した半導体素子を任意の箇所に搭載させ
ることができるために、マルチチップモジュールにTA
B接続構造を適用することができる結果、量産性に優れ
た半導体装置を提供することができる。
As described in detail above, the semiconductor device of the present invention can be used with respect to a lead wiring layer formed on the surface of a multilayer wiring board formed by laminating a plurality of insulating layers containing a thermosetting resin. Since a TAB-connected semiconductor element can be mounted at an arbitrary position, the multi-chip module has a TA chip.
As a result of applying the B connection structure, a semiconductor device with excellent mass productivity can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の製造方法を説明するため
の工程図である。
FIG. 1 is a process chart for explaining a method of manufacturing a semiconductor device according to the present invention.

【図2】本発明の図1における多層配線基板7を作製す
るための方法を説明するための図である。
FIG. 2 is a view for explaining a method for manufacturing the multilayer wiring board 7 in FIG. 1 of the present invention.

【符号の説明】[Explanation of symbols]

1 樹脂フィルム 2 穴 3 金属箔 4 リード配線層 5 TABテープ 6 半導体素子 7 多層配線基板 8 絶縁層 9 絶縁基板 10 配線回路層 11 ビアホール導体 DESCRIPTION OF SYMBOLS 1 Resin film 2 Hole 3 Metal foil 4 Lead wiring layer 5 TAB tape 6 Semiconductor element 7 Multilayer wiring board 8 Insulating layer 9 Insulating substrate 10 Wiring circuit layer 11 Via hole conductor

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】熱硬化性樹脂を含有する複数の絶縁層を積
層した絶縁基板と、該絶縁基板表面に形成されたリード
配線層と、前記絶縁基板表面および/または内部に形成
された配線回路層と、前記配線層間を電気的に接続する
ためのビアホール導体とを具備する多層配線基板と、前
記リード配線層にTAB接続された半導体素子とを具備
することを特徴とする半導体装置。
An insulating substrate having a plurality of insulating layers containing a thermosetting resin laminated thereon, a lead wiring layer formed on the surface of the insulating substrate, and a wiring circuit formed on the surface and / or inside the insulating substrate. A semiconductor device, comprising: a multi-layer wiring board including a layer and a via-hole conductor for electrically connecting the wiring layers; and a semiconductor element TAB-connected to the lead wiring layer.
【請求項2】前記絶縁基板表面のリード配線層と半導体
素子とが、転写フィルム表面にて前記半導体素子と前記
リード配線層をTAB接続した後、前記絶縁基板表面に
転写されたものである請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the lead wiring layer and the semiconductor element on the surface of the insulating substrate are transferred to the surface of the insulating substrate after the semiconductor element and the lead wiring layer are TAB-connected on the surface of the transfer film. Item 2. The semiconductor device according to item 1.
【請求項3】前記ビアホール導体を、金属粉末を含む導
体ペーストの充填によって形成し、且つ前記配線回路層
を金属箔により形成してなることを特徴とする請求項1
記載の半導体装置。
3. The method according to claim 1, wherein the via-hole conductor is formed by filling a conductor paste containing metal powder, and the wiring circuit layer is formed of metal foil.
13. The semiconductor device according to claim 1.
【請求項4】転写フィルム表面に、金属箔からなるリー
ド配線層を形成したTABテープを作製する工程と、該
TABテープの前記リード配線層に半導体素子をTAB
接続する工程と、熱硬化性樹脂を含有する複数の絶縁層
を積層した絶縁基板に、配線回路層と該配線回路層間を
電気的に接続するためのビアホール導体とが形成された
未硬化状態の多層配線基板を作製する工程と、前記半導
体素子をTAB接続したTABテープを前記多層配線基
板表面に積層した後、前記転写フィルムを剥がすことに
より、前記リード配線層とそれにTAB接続された半導
体素子とを前記多層配線基板表面に転写する工程と、該
多層配線基板を加熱して完全硬化する工程とを具備する
ことを特徴とする半導体装置の製造方法。
4. A step of producing a TAB tape in which a lead wiring layer made of a metal foil is formed on the surface of a transfer film;
Connecting, and an uncured state in which a wiring circuit layer and a via-hole conductor for electrically connecting the wiring circuit layer are formed on an insulating substrate on which a plurality of insulating layers containing a thermosetting resin are laminated. A step of manufacturing a multilayer wiring board, and after laminating a TAB tape in which the semiconductor element is TAB-connected to the surface of the multilayer wiring board, peeling off the transfer film, thereby forming the lead wiring layer and the semiconductor element TAB-connected thereto. A step of transferring the substrate to the surface of the multilayer wiring board, and a step of heating and completely curing the multilayer wiring board.
JP20165297A 1997-07-28 1997-07-28 Method for manufacturing semiconductor device Expired - Fee Related JP3441340B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20165297A JP3441340B2 (en) 1997-07-28 1997-07-28 Method for manufacturing semiconductor device

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Application Number Priority Date Filing Date Title
JP20165297A JP3441340B2 (en) 1997-07-28 1997-07-28 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH1145907A true JPH1145907A (en) 1999-02-16
JP3441340B2 JP3441340B2 (en) 2003-09-02

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ID=16444651

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Country Link
JP (1) JP3441340B2 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002089249A1 (en) * 2001-04-23 2002-11-07 Yokowo Co., Ltd. Broad-band antenna for mobile communication
JP2003332818A (en) * 2002-03-04 2003-11-21 Hitachi Metals Ltd Surface mount antenna and antenna device mounted with the same
JP2004104333A (en) * 2002-09-06 2004-04-02 Hitachi Cable Ltd Antenna and electrical apparatus provided with the same
JP2005072902A (en) * 2003-08-22 2005-03-17 Ngk Spark Plug Co Ltd Inverted-f antenna
JP2009100444A (en) * 2007-10-17 2009-05-07 Samsung Electronics Co Ltd Mimo antenna device
US20090315759A1 (en) * 2008-06-23 2009-12-24 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Direction Finding Antenna Systems and Methods for Use Thereof
WO2013012403A1 (en) * 2011-07-15 2013-01-24 Research In Motion Limited Diversity antenna module and associated method for a user equipment (ue) device

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002089249A1 (en) * 2001-04-23 2002-11-07 Yokowo Co., Ltd. Broad-band antenna for mobile communication
JP2003332818A (en) * 2002-03-04 2003-11-21 Hitachi Metals Ltd Surface mount antenna and antenna device mounted with the same
JP2004104333A (en) * 2002-09-06 2004-04-02 Hitachi Cable Ltd Antenna and electrical apparatus provided with the same
JP2005072902A (en) * 2003-08-22 2005-03-17 Ngk Spark Plug Co Ltd Inverted-f antenna
JP2009100444A (en) * 2007-10-17 2009-05-07 Samsung Electronics Co Ltd Mimo antenna device
US20090315759A1 (en) * 2008-06-23 2009-12-24 Hong Kong Applied Science And Technology Research Institute Co., Ltd. Direction Finding Antenna Systems and Methods for Use Thereof
WO2013012403A1 (en) * 2011-07-15 2013-01-24 Research In Motion Limited Diversity antenna module and associated method for a user equipment (ue) device

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