JPH1145596A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely execute a test with a simple circuit even in the case the memory capacities of respective semiconductor memory circuits respectively different from each other by resetting the address counter in a test circuit by using the respective max. word signals of the plural semiconductor memory circuits built in the circuit. SOLUTION: An address signal generating section 2 and data signal generating section 3 of a test circuit 15 write predetermined data patterns into the RAM (semiconductor memory circuit) 27. At this time, the counter consisting of toggle flip-flop in the address signal generating section 2 is reset with the word line selected in the last of a RAM 27 as a BIST signal to switch the writing of the data to the reading out of the data. An expected value collating section 5 compares the read out data with the expected value from an expected value data generating section 4 and outputs a collation result. When the last word line is selected again and the BIST signal is outputted, the test of the next RAM 28 is started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory circuit and a semiconductor integrated circuit including a test circuit for performing an operation test of the semiconductor memory circuit.

[0002]

2. Description of the Related Art Conventionally, semiconductor integrated circuits such as ASICs and microcomputers having a built-in semiconductor storage circuit such as a RAM include:
In some cases, a test circuit for performing an operation test of a semiconductor memory circuit is provided to reduce the number of external terminals for testing. FIG.
Reference numeral 0 is a block diagram showing an example of a conventional semiconductor integrated circuit incorporating a test circuit. In this figure, a test circuit 1 reads an address signal generator 2 for generating an address used for a test of a RAM 6, a data signal generator 3 for generating data to be written in the RAM 6, and data written in the RAM 6. An expected value matching unit 5 that determines whether the read data is the same as the data at the time of writing, and an expected value data generating unit 4 that generates expected value data to be input to the expected value matching unit 5 are provided. .

FIG. 11 is a time chart showing the operation of the test circuit 1. First, when a test signal is input from the outside, a counter (not shown) provided in the address signal generator 2 operates in synchronization with a clock, and an increment or decrement address signal is generated. The generated address signal is input to the decoder unit 7 (see FIG. 7) of the RAM 6, and a bit is selected. Then, the operation of writing the data signal generated by the data signal generation unit 3 to the selected bit is sequentially performed, and the RAM
Writing to all bits of the memory cell No. 6 is performed.

After writing to all the bits of the memory cell is performed, the write enable signal is switched from "0" to "1", and the read operation is switched. Then, the counter of the address signal generation unit 2 operates again, bits are sequentially selected, and data is read. Then, the comparison between the read data and the expected value data generated by the expected value data generation unit 4 is performed by the expected value comparison unit 5, and if they do not match, a pulse is output as a comparison result as a comparison result output terminal ( (Not shown). By mounting the test circuit 1 having such a function, one verification result output terminal can be used without using a plurality of external terminals for address signals and data input / output.

In recent years, the number of cases in which a plurality of RAMs are mounted has increased due to the improvement in the degree of integration of a semiconductor integrated circuit.
It is also conceivable to mount it for each of the. However, there is a strong demand for a reduction in chip area contrary to the improvement in the degree of integration. In particular, how to reduce the size of a self-test circuit used only during a test is an important issue.

As a method for solving this problem, it is possible to reduce the number of test circuits to one by switching using a selector. FIG. 12 is a block diagram showing a configuration of such an example. The semiconductor integrated circuit of this example includes three RAMs 10 to 12 having the same storage capacity, one test circuit 1, and selectors 13A to 13C. The selectors 13A to 13C are provided on the output side of the address signal generator 2 in the test circuit 1, the output side of the data signal generator 3, and the input side of the expected value matching section 5 receiving output signals from the RAMs 10 to 12. Is provided.

[0007] First, the selector 13A operates the RA
A signal path to M10 is selected, and an address signal and a data signal generated by the test circuit 1 are stored in the RAM 10. Subsequently, expected value comparison is performed at the time of reading. The details of this operation are the same as in the case described above. After that, the selector is switched by a test signal or a signal from a control circuit (not shown), and the remaining RAMs 11 and 12 are sequentially tested. In this example, since the address signal and the data signal can be used in common for all of the RAMs 10 to 12, the configuration is such that only the expected value comparison is performed individually.
One test circuit 1 can measure all RAMs 10 to 12 in parallel.

FIG. 13 is a block diagram showing another conventional example which does not use a selector. In this example, RAMs 10 to 12 having the same storage capacity and a test circuit 15 are mounted, and the expected value matching unit 5 in the test circuit 15
12 are provided in the same number. now,
The increment and decrement address signals generated by the address signal generator 2 of the test circuit 15 and the signals generated by the data signal generator 3 are stored in the RAMs 10-1.
2 are supplied in common, and data is written. Subsequently, each RAM 10
The expected values are compared by the expected value comparing sections 5 of the output signals from 12, and if they do not match, the test is performed in parallel by outputting from an external terminal provided separately.

[0009]

However, the above-mentioned conventional semiconductor integrated circuit has the following problems. A first problem is that when the storage capacities of a plurality of mounted semiconductor memory circuits are different, expected value comparison may not be performed normally. That is, a checker pattern may be written in order to see the influence of the interference of the data written in the memory cells of the semiconductor memory circuit, and the RAM having the largest storage capacity can be tested without any problem. The operation may not be performed normally for a small-capacity RAM.

The reason is that, for the address generated by the address signal generator 2 of the test circuit 1, the operation of alternately writing 0 and 1 signals to a series of bits and then reading the same is performed. When an address exceeding the address is selected, the data of the last accessed bit continues to be output as it is, whereas the expected value generating unit 5 of the test circuit 1 alternates the expected value signals of “0” and “1”. Is generated because of inconsistency.

The second problem is that the circuit becomes complicated and cost increases in order to prevent the inconsistency of the first problem from occurring. In other words, when testing each semiconductor memory circuit serially or in parallel, the test circuit 1 for each semiconductor memory circuit reaches a register for setting the maximum value of the address signal generated and the maximum address set in the register. Circuit for determining whether or not
Further, a control circuit for controlling the data signal, the write control signal, and the expected value signal when the maximum address set in the register is reached is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit that can reliably perform a test with a simple circuit even when a plurality of built-in semiconductor storage circuits have different storage capacities.

[0013]

In order to achieve this object, a semiconductor integrated circuit according to the present invention comprises a plurality of semiconductor memory circuits having different storage capacities and a test circuit for performing an operation test of the plurality of semiconductor memory circuits. A test circuit comprising: a data signal generating means for generating data for writing to the semiconductor memory circuit; an expected value data generating means for generating expected value data; and a semiconductor memory circuit to which the data is written. An expected value comparing unit that reads data, determines whether the read data is the same as the data output from the expected value data generating unit, and detects a selected state of a specific word line of each semiconductor memory circuit And an address signal generator for generating an address signal corresponding to each semiconductor memory circuit based on a detection signal of the detector. It is obtain things.

According to this structure, the address signal of the test circuit is controlled by the control signal output simultaneously with the operation of the maximum address word of the semiconductor memory circuit. The expected value collation mismatch does not occur.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. (I) First Embodiment FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention. In this figure, parts common to those in FIG. 10 described above are denoted by the same reference numerals, and description thereof is omitted. In the first embodiment,
The address signal generator 2 and the data signal generator 3 of the test circuit 15 operate respectively, and a RAM (semiconductor memory circuit)
A predetermined data pattern is written in
Buffer the last selected word line in the AM
(Or as it is) as a BIST control signal, and the BIST control signal resets the counter in the address signal generator 2 and switches from data writing to data reading.

Then, the operation of the counter is continuously started to read data, sequentially compare with the expected value, and output a pulse to the outside if a mismatch occurs.
Then, the last word line is selected again, and BIST is selected.
When the control signal is output, the process proceeds to the next RAM test. The above operation is performed for several times of RAM, and in this embodiment, 3
By repeating this process twice, each test of the RAMs 27 to 29 is completed. In this embodiment, the counter in the address signal generation unit 2 is reset at the last word line selected and data is switched from data write to data read. However, the operation of selecting a specific word line is delayed. Alternatively, the control signal can be used.

The address signal generator 2 has a configuration as shown in the block diagram of FIG. The above-described counter comprises a toggle flip-flop 30. When a BIST control signal from the RAM under measurement 27 to 29 is input during the counter operation, the counter value is reset to "0" and the counter operation starts again. At this time, after a test is performed on one RAM by the select circuits 22 and 24 shown in FIG. 1 as in the related art, the next RAM is selected and the test is performed. Since it is only necessary to sequentially generate address signals corresponding to the storage capacities of the respective RAMs 27 to 29 using the above circuits,
Expected value matching is performed without any problem.

The select circuits 22 and 24 are shown in FIGS.
As shown in (1), each of them is composed of three NOT circuits and NAND circuits. Also, as shown in FIG.
The BIST control signals obtained from 27 to 29 are input to the address signal generator 2 via the NOR circuit 23. As described above, not only the addition of the extremely simple circuits (the buffer 20, the selector circuits 22, 24, and the NOR circuit 23) can avoid the problem of expected value comparison, but also can avoid the generation of unnecessary addresses. It can contribute to shortening of test time. Note that the buffer 20 is not always necessary.

(II) Second Embodiment FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. In the second embodiment, the basic operation is the same as that of the above-described first embodiment, but the input signal of the expected value collating unit 5 is controlled by the BIST control signal so as not to be inconsistent. Are different. The counter of the address signal generation unit 2 continues to operate, but holds the input signal of the expected value comparison unit 5 so that the expected value comparison does not become inconsistent when the maximum address of the measured RAM is exceeded.

FIG. 6 is a block diagram showing a characteristic portion of the second embodiment. Upon receiving the BIST control signal,
The latch circuit 35 on the output side of the expected value data generator 4 holds the data used for the expected value comparison of the last bit. Since the measured RAM also keeps outputting the data of the bit accessed last, no mismatch occurs. The counter of the expected value collating unit 5 is reset to "0" by the output of the latch circuit 35, the latch is released simultaneously with the switching to the next RAM selection signal, and normal expected value collation starts. By repeating this operation, all the RAM 27
The tests of to 29 are completed.

(III) Application Example of Second Embodiment FIG. 7 is a block diagram showing a configuration of an application example of the second embodiment. This application example is basically the same as the second embodiment, but instead of holding expected value data, R
The difference is that both the output data of the AM and the output signal of the expected value data generator 4 are pulled down to the same potential. BIST
When a control signal is received, pull-down is performed, and expected value data and R
The output data of AM becomes the same potential, and no mismatch occurs in the expected value comparison. In this figure, the transistor element 36 is switched down to pull down. In addition, it is not limited to pre-down, but may be pull-up.

(IV) Third Embodiment FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention. In this embodiment, the address signal generation unit 2 and the data signal generation unit 3
The same signal is supplied to 7 to 29, and the expected value comparison unit 5 is provided for each of the RAMs 27 to 29 so that the test is performed in parallel. Each expected value matching unit 5 is controlled by a BIST control signal output from each of the RAMs 27 to 29.
Control the input signal of the controller so that no mismatch occurs. The basic operation is the same as that of the second embodiment.
No selector circuit for selecting input signals to 27 to 29 is used. Further, the detailed circuit in the third embodiment can be realized by the same one as in the second embodiment, and therefore its description is omitted.

(V) Fourth Embodiment FIG. 9 is a block diagram showing a configuration of a characteristic portion of a semiconductor integrated circuit according to a fourth embodiment of the present invention. In this embodiment, the basic operation is the same as in the second embodiment,
The difference is that, instead of controlling the input of the expected value matching unit 5, the output of the expected value matching unit 5 is forcibly brought into a matching state.

[0024]

According to the present invention, the maximum word signal of each of the plurality of semiconductor memory circuits is used as a control signal (BIST control signal), and the control signal resets the counter of the address signal generating means in the test circuit. By holding the expected value data from the expected value data generating means, a test can be performed on a plurality of semiconductor memory circuits having different storage capacities without causing a mismatch in expected value comparison.

Also, it corresponds to inputs of a NOR circuit for obtaining a logic of a BIST control signal of each semiconductor memory circuit, a latch circuit for holding expected value data generated from expected value data generating means, and expected value illuminating means. It is only necessary to add an element for pulling up or pulling down the output data of the semiconductor memory circuit and the expected value signal generated by the expected value data generating means to the same potential, and the conventional large-scale control circuit can be simplified. And a significant cost reduction becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of an address signal generation unit of the semiconductor integrated circuit according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a select circuit of the semiconductor integrated circuit according to the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of a select circuit of the semiconductor integrated circuit according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of a second embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 6 is a block diagram illustrating a configuration of a characteristic portion of a semiconductor integrated circuit according to a second embodiment;

FIG. 7 is a block diagram illustrating a configuration of a characteristic portion of an application example of the semiconductor integrated circuit according to the second embodiment;

FIG. 8 is a block diagram showing a configuration of a third embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 9 is a block diagram showing a configuration of a characteristic portion of a fourth embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 10 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 11 is a time chart showing an operation of a conventional semiconductor integrated circuit.

FIG. 12 is a block diagram showing a configuration of another conventional semiconductor integrated circuit.

FIG. 13 is a block diagram showing a configuration of another conventional semiconductor integrated circuit.

[Explanation of symbols]

 2 Address signal generator 3 Data signal generator 4 Expected value data generator 5 Expected value comparison unit 20 Buffer 22, 24 Selector 23 NOR circuit 27-29 RAM 30 Toggle flip-flop 35 Latch 36 Pull-down transistor element 37 NOT circuit 38 OR circuit

Claims (6)

[Claims] 1. A semiconductor integrated circuit comprising: a plurality of semiconductor storage circuits having different storage capacities; and a test circuit for performing an operation test of the plurality of semiconductor storage circuits. A data signal generating means for generating data of the expected value; an expected value data generating means for generating expected value data; and reading data from the semiconductor memory circuit in which the data is written, and outputting the read data from the expected value data generating means. Expected value comparing means for determining whether the data is the same as the selected data, detecting means for detecting a selected state of a specific word line of each semiconductor memory circuit, and each semiconductor memory based on a detection signal of the detecting means. A semiconductor integrated circuit, comprising: an address signal generator that generates an address signal corresponding to a circuit. 2. The semiconductor integrated circuit according to claim 1, wherein the operation of the address signal generating means is reset by a detection signal from the detecting means. 3. The semiconductor integrated circuit according to claim 1, wherein said address signal generating means includes a counter means for generating an address signal, and resets said counter means in response to a detection signal from said detection unit. circuit. 4. The semiconductor integrated circuit according to claim 1, further comprising: latch means for holding expected value data input to said expected value matching means in response to a detection signal from said detecting means. 5. A semiconductor device according to claim 1, further comprising a pull-down or pull-up means for setting the expected value data inputted to said expected value comparison means and an output signal of said semiconductor memory circuit to the same potential in response to a detection signal from said detection means. A semiconductor integrated circuit according to claim 1, wherein: 6. The semiconductor integrated circuit according to claim 1, further comprising: holding means for holding a matching result of said expected value matching means in a matching state based on a detection signal from said detecting means.