JPH1139180A - Semiconductor device test system and its server device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device test system which reduces testing time. SOLUTION: A semiconductor test system 204 includes a storing part 205 which stores a test program that separately identifies a test item and tests a semiconductor device, a test number correspondence table storing part 211 which classifies test items of the test program, a test executing part 109 which carries out a program stored in the part 205 and accumulates test results in each test item, a test result accumulating part 208 and a relocation executing part 209 which relocates the test items of the test program in a prescribed order based on a classification result and an accumulation result. A server that performs centralized management of plural tests with similar configuration is also disclosed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for testing a semiconductor device, and more particularly, to a system capable of shortening a test time and a server apparatus therefor.

[0002]

2. Description of the Related Art Tests are indispensable for manufacturing semiconductor devices. However, with the recent increase in the degree of integration of semiconductor devices, there is a problem that the test time increases.
Is important.

Referring to FIG. 25, a conventional semiconductor device test system compiles a semiconductor device test source program 101 and executes an execution program 10
3 and a tester 104 for executing a program for a product type to be tested out of the execution program 103 to output a test result (pass / fail) and storing the test result.
And

A tester 104 includes an execution program storage unit 105 for storing an execution program, a program memory 108, and a program selection and load instruction 106.
Reads the specified execution program from the execution program storage unit 105 according to
And a test execution unit 109 for executing a device test based on the execution program loaded in the program memory 108.
And a pass / fail notification unit 110 for notifying a test result (pass / fail) to the outside, and a test result storage unit 111 for storing the test result.

A conventional semiconductor device test system operates in the following procedure. First, a source program 101 for device test is created. This source program is compiled by the test program compiler 102 to create an execution program 103. The execution programs 120A, 120B,.
0Z and the like are registered in the execution program storage unit 105.

In accordance with a program selection and load instruction 106, a program of a type to be tested is selected from among the execution programs 120A, 120B,.
To the program memory 108 via The test execution unit 109 executes the loaded program, and notifies a test result to the outside from the pass / fail notification unit 110. The test results are also stored in the test result storage unit 111.

[0007]

When a defect occurs in a test of a semiconductor device, the defect item often depends on a test item in lot units or wafer units. There are many types of test items in a device test, but if a defect occurs due to a certain test item, it is possible to determine the defect immediately by executing the test item first, and perform the subsequent tests. Since it is not necessary, the test time as a whole is short.

For example, when the test item to be defective is the last one in the test order, it is necessary to execute all the test items for determining the path up to the test item. If you run the bad test item first,
The defect determination is performed early. If the test is to find defective products, it is not necessary to execute the subsequent test items. Therefore, the test time is shortened.

However, if such processing is to be performed by the above-described conventional test system, the following processing is required. First, the failure rate is tabulated based on the test results inside the tester (112). By examining the result of the aggregation, a test flow to be changed is determined (113). Edit the source program 101 based on the test flow (11
4). Source program 1 edited in this way
01 is recompiled, loaded into the program memory 108, and executed.

In the conventional system, the above-described procedure is required to change the test program to a flow according to the defect occurrence rate and execute the test. Therefore, even if a test item having a defect in a lot unit or a wafer unit is followed, the operator must recognize the change in the test flow and perform the manual test flow change as described above. . Therefore, in the conventional test system, it is difficult to change the test flow in a timely manner, and it is difficult to reduce the test time.

The conventional system also has the following problems. When performing device failure analysis, if a certain test item fails to investigate the cause of failure,
It is necessary to check whether the test item alone is defective or a later test item is also defective. for that purpose,
The test program is changed so that test items subsequent to the defective test item can be tested before the defective test item.

However, in the conventional system, as described above, in order to change the test flow, the contents of the failure are investigated based on the test results inside the tester (112), and the test flow to be changed is determined (113). ), After editing the source program based on the test flow (114),
The work of compiling again and loading the execution program was necessary. When the source program is changed in this way, it is difficult to make an appropriate change unless the contents of the source program are detailed. Therefore, there is a problem that it takes time to perform the failure analysis.
Therefore, there is a need for a semiconductor device test system capable of automatically rearranging a test program according to a specific purpose of shortening a test time and a failure rate of a test result.

In addition to the fact that such processing can be executed by a single tester, a server device of a semiconductor device test system is also required so that a plurality of testers can execute the processing in parallel.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a first object of the present invention is to provide a semiconductor device test system capable of shortening a test time.

Further, a second object is to provide a semiconductor device test system in which a test flow can be easily changed in addition to the first object.

A third object is to provide a server device of a semiconductor device test system capable of shortening a test time.

[0017]

According to a first aspect of the present invention, there is provided a semiconductor device test system for storing a test program for testing a semiconductor device which can be identified for each test item. Means, means for classifying test items of the test program,
Means for executing the program stored in the storage means and summing up the test results for each test item, and classifying the test items of the test program based on the result of the classification by the classifying means and the totaling result by the summing means. Means for rearranging in a predetermined order.

According to the first aspect of the present invention, test results obtained by executing the program are totalized, classified,
The test items of the test program are automatically rearranged in a predetermined order based on the aggregation result and the test result. Since the test items are automatically rearranged in the order according to the purpose, it is easy to execute the tests in the optimum order according to the test purpose, and the test time can be reduced.

According to a second aspect of the present invention, in the semiconductor device test system according to the first aspect, the rearrangement means re-arranges the test items of the test program in the descending order from the test item having a high defect rate. Including means for positioning.

By rearranging the test items in descending order of the defect rate, a test item with a high defect rate is executed before other test items, and a defective product is found at an early stage. It is not necessary to execute the test items subsequent to the test item on the defective product, and the test time can be reduced.

According to a third aspect of the present invention, there is provided a semiconductor device test apparatus according to a test flow editing means for editing a test flow by a test program in test item units, and a test flow edited by the test flow editing means. Instruction means for instructing rearrangement of the test program. The rearrangement unit executes the rearrangement in response to an instruction from the instruction unit.

According to the third aspect of the present invention, the operator can edit the test flow for each test item. The operator does not need to know the detailed contents of each test item. Then, the test program is automatically rearranged according to the edited result, so that the test flow can be easily changed and the test time can be reduced.

According to a fourth aspect of the present invention, there is provided a server device of the semiconductor device test system, wherein each of the plurality of servers can execute a test program for testing a semiconductor device and capable of identifying each test item. A communication device for communicating with the plurality of test devices, a storage unit for storing the test program, a unit for classifying test items of the test program based on the identifier, and a test program stored in the storage unit. Means for downloading and executing the test results to a plurality of test devices connected via the same, collecting test results and totaling them for each test item, the results of classification by the classifying means, and the totaling results by the totaling means. Means for rearranging the test items of the test program based on the predetermined order.

According to the fourth aspect of the present invention, the test results obtained by executing the programs in the respective testers are totaled and classified by the server device, and the test program is classified based on the totalized results and the test results. Are automatically rearranged in a predetermined order. Since the test items are automatically rearranged in the order according to the purpose, it is easy to execute the test in each tester in the optimal order according to the test purpose, and the test time can be reduced.

According to the invention set forth in claim 5, according to claim 4,
In addition to the above configuration, the arranging means includes means for rearranging the test items of the test program in descending order of the test items having a high defect rate.

By rearranging the test items in descending order of the defect rate, the test items having a high defect rate are executed before the other test items, and defective products are found at an early stage. It is not necessary to execute the test items subsequent to the test item on the defective product, and the test time can be reduced.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] Referring to FIG. 1, tester 2 according to a first embodiment of a semiconductor device test system of the present invention.
04 is the source program 2 created for the test
01, as source programs 203A, 203B,..., A compiler 202 for compiling the source programs 203A, 203B,.
The execution program 22 created by the compiler 202
0A, 220B,..., A program memory 108, and a program type to be tested among execution programs registered in the execution program storage unit 205 in response to the program selection and loading instruction 106. It includes a loading unit 107 for selecting a program and loading it into the program memory 108, and a relocation information storage unit 207 for storing relocation information in response to the program relocation information instruction 210. Here, the relocation information is information indicating at what timing the relocation of the test program is executed. Examples of the relocation information include "execute every lot, every 10 wafers, every 10 hours", "execute immediately after instructing relocation",
Or there is information such as "Do not execute relocation".

The tester 204 further includes a test execution unit 109 for executing a test by executing the test program loaded in the program memory 108 and a pas for notifying the test result by the test execution unit 109 to the outside.
an s / fail notification unit 110 and a test result storage unit 111 for storing a test result by the test execution unit 109
And monitors the test status of the device at all times, and issues a program relocation instruction when the conditions for relocating the program are satisfied based on the relocation information stored in the relocation information storage unit 207. Instruction unit 206 for
In response to the instruction 230 from the rearrangement instruction unit 206,
Of the test results stored in the test result storage unit 111, the test result totaling unit 208 for totaling the failure rate of all test items for the amount specified by the relocation information.
In response to the relocation instruction from the relocation instruction unit 206,
To extract the relocation target test items from the source programs 203A, 203B,... Stored in the source program storage unit 203, and to rearrange the test items based on the test results totalized by the test result aggregation unit 208. And a test number correspondence table storage unit 211 for storing the relocation target number target table 401 created by the relocation execution unit 209.

Referring to FIG. 2, the structure of the source programs 201, 203A, 203B and the like in FIG. 1 will be described. The following description uses the source program 201 as an example. Referring to FIG. 2, test items to be rearranged in source program 201 are separated from each other by identifiers indicating their start position and end position. For example, in FIG. 2, the start is indicated by an identifier "START" and the end is indicated by an identifier "END". Each test within the range enclosed by the identifiers “START” and “END” forms one test item.

Here, the test number is a serial number assigned to each test item in the test program, and is assumed to correspond to all test items on a one-to-one basis.

Referring to FIG. 3, relocation executing section 209 includes:
Source program, for example, source program 203A
Test item extraction unit 20 for extracting test items from
9A and a failure rate totaling unit 209B for creating a failure rate totaling table for each relocation test item based on the failure percentage totaling result 208A created by the test result totaling unit 208.
The contents including the tables described below, such as the relocation test item-specific defect rate total table and the defect rate total result, will be described later.

The relocation execution unit 209 further includes a test flow determination unit 209C for determining test flows in descending order of the failure rate based on the failure rate aggregation table for each relocation test item created by the failure rate aggregation unit 209B. And a program rearrangement unit 209D for analyzing the source program and rearranging the test items based on the test flow determined by the test flow determination unit 209C to create the rearrangement completion source program 301.

FIG. 4 shows the flow of a table or the like created by each unit in FIG. Referring to FIG.
From 3A, a test item extraction unit 209A creates a relocation test number correspondence table 401. This relocation correspondence table 401
And the failure rate totaling unit 209B based on the failure rate totaling result 208A.
Creates the relocation test item-specific defect rate totalization table 402.
The test flow determining unit 209C determines the test flow 403 based on the relocation test item-specific failure rate totalization table 402. Based on the test flow 403 and the analysis result of the source program 203A, the program relocation unit 2
09D rearranges the program to create a rearrangement completion source program 301.

The contents of each table shown in FIG.
This will be described below with examples. Referring to FIG. 5, a plurality of test items whose source program 203A is to be rearranged as shown in the drawing (test item numbers of these test items are A1, A2,... An, respectively. Each test item is represented by this test item number.) And other tests that are not to be rearranged. For example, test items A1, A2,.
Each of n includes an arbitrary number of tests, and has an identifier "START" indicating its start position and an identifier "END" indicating its end position. By dividing the program by the identifier in this way, in the compilation at the time of rearrangement, only the program portion in which the identifiers START and END are described need be recompiled. In this case, there is an effect that the compile time is short. Of course, if there is no problem in compilation time, all parts may be compiled.

FIG. 6 shows an example of the relocation test number correspondence table 401. In this example, the source program 20 shown in FIG.
The result of analyzing 3a is shown. Referring to FIG.
The rearrangement test number correspondence table 401 includes a test item number (A
Test numbers (a11, a12, etc.) included in the test item indicated by each test item number
Is made to correspond. The creation of the rearrangement test number correspondence table 401 as described above has the following effects.

Before analyzing the source program 203A, the test item extracting unit 209A first checks the relocation test number correspondence table 401. If test items have been extracted by the same program before, the relocation test number correspondence table 401 should have already been created and stored. Therefore, in this case, the relocation test number correspondence table 4 already created in place of the test item extraction
If 01 is used, the time required for extracting test items can be eliminated, and the test time can be reduced.

Referring to FIG. 7, defect rate totaling result 208A
Is a pair of each test number (a1, a2,...) And the failure rate in the test.

Referring to FIG. 8, relocation test item failure rate totaling table 402 manages, for each test item number, the test number included in the test item and the failure rate of the entire test number of the test item. It is a table for doing. This table is created from the relocation test number correspondence table 401 and the failure rate total result 208A. The test flow is determined based on the column of “defective rate” in this table.

Referring to FIG. 9, the test flow 403 is as follows.
The test order is assigned to each test item number of the relocation test item-specific failure rate totalization table 402 shown in FIG. 8 in the order of a higher failure rate (in descending order of the failure rate). In the example shown in FIG. 8, the failure rate of the test item A1 is 2%, and the failure rates of other test items are higher. Then
As shown in FIG. 9, the test order of the test item A1 is n.
(N is the number of test items) and rearranged at the latest position.

This relocation test item failure rate totalization table 40
2 and the relocation completed source program 30 that has been relocated based on the analysis result of the source program 203A.
1 is shown in FIG. As shown in FIG. 10, each test item is shown in FIG.
02 according to the corresponding test order.

The tester 104 operates as follows. Referring to FIG. 1, first, a source program 201 is created and stored in the source program storage unit 203.
The format of the source program 201 at this time is as shown in FIG. 2 or FIG. This is compiled by the compiler 202 and registered in the execution program storage unit 205.

Next, program selection and load instruction 10
6, the program of the type to be tested is selected from the execution programs registered in the execution program storage unit 205, and the program memory 10
Load 8 At the same time as this program loading instruction,
The program relocation information instruction 210 is also performed, and the relocation information is registered in the relocation information storage unit 207.

The test execution unit 109 stores the program memory 1
A test is executed based on the program loaded in step 08, and the result of the test is notified from the pass / fail notifying unit 110 to the outside. The test result is also stored in the test result storage unit 111.

On the other hand, the relocation instructing unit 206 constantly monitors the test status of the device, and determines whether or not the conditions for relocating the program are satisfied based on the relocation information registered in the relocation information storage unit 207. to decide. Then, when it is determined that the conditions for relocating the program are satisfied, the relocation instruction unit 206 first outputs an instruction 234 for temporarily suspending the test in the test execution unit 109. Next, the rearrangement instructing unit 206 instructs the test result totaling unit 208 on the basis of the test results stored in the test result storage unit 111, the failure rate of all the test items specified by the rearrangement information. An instruction 230 to start counting is given. The reallocation instruction unit 206 further provides a reallocation instruction 232 to the reallocation execution unit 209.

The relocation execution unit 209 is provided with the relocation instruction unit 20.
6 in response to the relocation instruction 232 from the source program storage unit 203, the relocation target test items are extracted from the source program in the source program storage unit 203. Once the test results have been compiled,
The relocation execution unit 209 relocates test items based on the totaled test results and the source program from which the relocation target test items have been extracted.

Referring to FIG. 3, a test item to be rearranged is extracted by test item extracting section 209A. That is, the test item extracting unit 209A analyzes the source program, extracts the test numbers in the test items to be rearranged surrounded by the identifiers START and END, and creates the relocation test number correspondence table 401. This relocation test number correspondence table 40
1 is stored in the test number correspondence table storage unit 211. At this time, the test item extraction unit 209A checks whether or not test items have been extracted by the same program before, and if so, reads out the corresponding correspondence table from the test number correspondence table storage unit 211, No test items are extracted.

Next, based on the relocation test number correspondence table 401 and the failure rate aggregation result 208A from the test result aggregation section 208, the failure rate aggregation section 290B creates a failure rate aggregation table 402 for each relocation test item. The test flow determination unit 209C performs the relocation test item-specific defect rate totaling table 40.
2, the test flow 403 is determined. This determination method is as described above.

Next, the program rearrangement section 209D analyzes the source program again, rearranges the test items based on the test flow 403, and creates a rearrangement completion source program 301. In this case, the test items may be rearranged in the source program in the test order.

The relocation complete source program 301 is given to the compiler 202, automatically compiled to create an execution program, and registered in the execution program storage unit 205. This execution program is loaded again into the loading unit 107
To the program memory 108 via In the program memory 108 where this program is loaded,
As shown in FIG. 11, the order of each test item in the program is changed before and after the rearrangement, and the order is as determined by the test flow determination unit 209C. When a test restart instruction 236 is given from the rearrangement instruction unit 206 to the test execution unit 109, the test execution unit 109 performs a test based on the program after the rearrangement is completed.

By performing the above-described operation in the tester having the above-described configuration, a test can be performed by automatically rearranging test items in descending order of the defect rate according to the test result. For this reason, many defect determinations can be made in a shorter test time than in a conventional test system, and the entire test time can be reduced.

In the first embodiment, it is assumed that the test program is composed of one source program. However, the present invention is not limited to this, and it is also possible to adopt split compilation in which a source program is divided and created, and they are combined at the time of compilation to generate one execution program. In the first embodiment, the execution program storage unit 205, the test result storage unit 111, and the relocation information storage unit 207 have been described as separate storage devices. However, they may be provided in separate areas of a common storage device. The good thing is, of course.

In the first embodiment, the rearrangement instruction unit 20
6 to the test execution unit 109 by a test interruption instruction 234
Is performed when it is detected that the rearrangement conditions are satisfied. However, the present invention is not limited to this. For example, considering that it takes a long time to execute the relocation, the test suspension instruction 234 is performed when the compilation of the relocation completion source program 301 is completed, and when the loading of the execution program into the program memory 108 is completed. A test restart instruction 236 may be issued.

[Embodiment 2] The apparatus of Embodiment 1
Program relocation was possible with a single tester. On the other hand, a test can be performed by a plurality of testers, and the rearrangement of test programs can be managed collectively by a test server. The system according to the second embodiment is such a system.

Referring to FIG. 12, the system includes a server 501 having a test program relocation function, and a server 501 connected to the server 501 via a network to execute a test under the management of server 501. And a plurality of testers 520. The server 501 is connected to each tester 52
It is possible to total the test results executed in step 0, relocate the test program, and download the relocated test program to each tester.

FIG. 13 shows the configuration of the server 501, and FIG. 14 shows the configuration of the tester 520. 13 and 14, the same or similar portions as those of the device of the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be repeated.

Referring to FIG. 13, this server 501 includes:
A source program storage unit 203 and a compiler 202
Execution program storage unit 205, relocation information storage unit 207, relocation instruction unit 206, test number correspondence table storage unit 211, test result storage unit 111, test result totalization unit 208, relocation execution And a communication unit 250 connected to the execution program storage unit 205, the test result storage unit 111, and the rearrangement instruction unit 206, and connecting these to the respective testers 520 via a network.

Referring to FIG. 14, each tester 520 connects load section 107, program memory 108, test execution section 109, pass / fail notification section 110, load section 107 and test execution section 109 via a network. And a communication unit 252 for connecting to the server 501.

When a program selection and load instruction 106 is generated in each tester 520, a download request for the specified program is issued from the load unit 107 to the server 501 via the communication unit 252. In response to the download request, the execution program storage unit 205 of the server 501 downloads the selected execution program to the program memory 108 via the load unit 107 of each tester 520 via the communication unit 250. The test result storage unit 111 collects test results from the test execution unit 109 of each tester 520 via a network. The relocation instructing unit 106 communicates with the test execution unit 10 via a network.
9, a test interruption instruction 234 and a test restart instruction 236 are given.

Also in this system, relocation information is stored in the relocation information storage unit 207 in advance. Each tester 520
Thereafter, the completion report of the test and the test result for each wafer and each lot are recorded in the server 501. Therefore, in the server 501, it is possible to confirm the relocation conditions in units of wafers and lots and to collect data for relocation. In addition, information of test start and test end is also recorded from each tester 520 to the server 501. for that reason,
It is possible to check the relocation conditions in units of time and collect data for relocation.

The system according to the second embodiment can obtain the same effects as those of the device according to the first embodiment. Also,
By connecting a server and a plurality of testers via a network, a test can be executed by the plurality of testers and test results can be centrally managed by the server. More test results can be collected in a shorter period of time as compared with the program relocation by each tester alone, and a more timely relocation program can be created.

Third Embodiment FIG. 15 shows a configuration of a tester 610 according to a third embodiment of the present invention. FIG.
Shows the configuration of the relocation execution unit 612 included in the tester 610. The tester 610 according to the third embodiment is different from the tester 610 according to the first embodiment.
Compared to the tester 204, the test flow can be easily changed without knowing the details of the test program. Therefore, in this tester 610, a test flow required for failure analysis can be easily changed, for example, a test item placed after a certain test item is moved to the front of the test item, and efficient failure analysis can be performed. Embodiment 3
In the drawings, the same or similar parts as those of the tester according to the first embodiment are denoted by the same reference numerals, and detailed description thereof will not be repeated.

The tester 610 shown in FIG. 15 is different from the tester 204 shown in FIG. 1 in that a test flow edit 601 and a test flow change which are connected to a test number correspondence table storage unit and a relocation instruction unit, respectively. That is, a function of an instruction 602 is added. In addition, this tester 61
0 is the relocation instruction unit 20 of the tester 204 of the first embodiment.
6. Relocation execution unit 209 and test number correspondence table 211
And a rearrangement instruction unit 61 having a slightly different function.
4, a relocation execution unit 612, and a test number correspondence table storage unit 616.

In the test flow editing 601, a test flow can be created by assigning a test order for each test item based on the rearranged test number correspondence table stored in the test number correspondence table storage unit 616 in the tester. it can. In this case, the test order may be assigned to each test item, and since each test item has an identifier indicating its start and end, the test order can be easily changed in test item units without knowing the details of the test program. It is possible to

The test flow change instruction 602 is for instructing the relocation instruction unit 614 to relocate the test program based on the test flow edited by the function of the test flow editing 601. The relocation instructing unit 614 notifies the relocation executing unit 612 not only when the relocation condition stored in the relocation information storage unit 207 is satisfied but also when the test flow change instruction 602 issues an instruction. A rearrangement execution instruction 232 is issued.

FIG. 16 shows the configuration of the relocation execution unit 612.
This will be described with reference to FIG. The reallocation execution unit 612 is different from the reallocation execution unit 209 of the first embodiment shown in FIG.
Test flow 701 newly edited by the test flow editing 601 in place of the program relocation unit 209D of FIG.
Accordingly, a different point is that a program rearrangement unit 612D that rearranges the source program in a different manner depending on the cause of the instruction to execute the rearrangement and outputs the rearrangement completed source program 404 is provided. The program rearrangement unit 612D also
It is also different from the program rearrangement unit 209D of FIG. 3 in that the test item extraction result is directly received from the test item extraction unit 209A.

FIG. 17 shows the flow of the process of rearranging the source program in the tester 610 according to the third embodiment. 17, the same or similar portions as those shown in FIG. 3 are denoted by the same reference characters, and detailed description thereof will not be repeated. 17 differs from FIG. 3 in that a test flow 701 that can be newly edited is included, and that the rearrangement completion source program 404
Or 701.

The tester 610 according to the third embodiment operates as follows. First, the tester 610 can operate in exactly the same way as the tester of the first embodiment. In this case, the program rearrangement unit 612D shown in FIG.
Operates in exactly the same way as the program rearrangement unit 209D shown in FIG. 7, and rearranges the program according to the test flow determined by the test flow determination unit 209C. FIG. 18 shows an example of the source program at this time, and FIG. 19 shows an example of the relocation test number correspondence table 401.
FIG. 20 shows an example of A, and FIG.
02 is shown in FIG. 21 and an example of the test flow 403 is shown in FIG.
Are shown below. FIGS. 19 to 22 correspond to FIGS. 6 to 9 of the first embodiment, respectively. Since the original source program is different, the content of each drawing is also different, but the essence is exactly the same as in the first embodiment.

On the other hand, the operation of the tester 610 when the test flow 701 is created by using the test flow editing 601 is as follows. First, the test flow editing 601 creates a test flow 701 in the test number correspondence table storage unit 616. When the test flow change instruction 602 is issued, the relocation instruction unit 614 suspends the test in the test execution unit 109. Next, the rearrangement instruction unit 614
, An instruction 232 for relocating the program is issued to the relocation executing unit 612. The instruction at this time is distinguished from when the rearrangement condition is satisfied.

In relocation executing section 612, with reference to FIG. 16, test item extracting section 209A extracts a test item and provides it to program relocating section 612D. Defect rate totaling unit 2
09B and the test flow determination unit 209C do not operate. The program rearrangement unit 612D analyzes the source program, rearranges the test items based on the test flow 701, and outputs the rearranged source program 404.

The relocation complete source program 4
Since the test method using No. 04 is the same as that in the first embodiment, it will not be repeated here.

FIG. 23 shows an example of the test flow 701.
The test flow 701 is the same as the test flow 403 except that the items in the test order are edited by the test flow edit 601. By making it editable in this way, it is possible to easily realize a rearrangement different from the rearrangement based only on the defect rate as shown in FIG.

FIG. 24 shows an example of the relocation completion source program 404. The example shown in FIG. 24 is the result of relocating the program according to the test flow 701.

As described above, the tester 61 of this embodiment
At 0, the test can be automatically performed by a program in which test items are rearranged in descending order of the defect rate, just like the tester of the first embodiment. Further, in this tester 610, as long as the correspondence between the test item and the test number is grasped, the test flow can be easily and appropriately changed without knowing the contents of the source program in detail. Therefore, there is an effect that a failure analysis that requires such processing can be performed more efficiently than before.

Further, the tester according to the third embodiment can be modified as described in the first embodiment. The tester of the third embodiment can also be networked like the system of the second embodiment.

[0075]

As described above, according to the first aspect of the present invention, the test items are automatically rearranged in the order according to the purpose, so that the tests are executed in the optimum order according to the test purpose. And the test time can be shortened.

According to the second aspect of the present invention, by rearranging the test items in descending order of the defect rate, the test items having a higher defect rate are executed before the other test items, and the defective products are earlier. Found at the stage. It is not necessary to execute the test items subsequent to the test item on the defective product, and the test time can be reduced.

According to the third aspect of the present invention, the operator can edit the test flow for each test item. Since the test program is automatically rearranged according to the editing result, the test flow can be easily changed, and the test time can be reduced.

According to the fourth aspect of the present invention, the test results obtained by executing the program in the plurality of testers are totaled and classified by the server device, and the test results are classified based on the totaled results and the test results. The test items of the program are automatically rearranged in a predetermined order. In addition, since the test items are automatically rearranged in the order according to the purpose, it is easy to execute the tests by the respective testers in the optimum order according to the test purpose, and the test time can be reduced.

According to the fifth aspect of the invention, a test item having a high defect rate is executed before other test items,
Defective products are found early. For the defective product,
It is not necessary to execute the test items after the test item, and the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an overall function of a semiconductor device tester according to a first embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a format of a source program used in the tester according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a reallocation execution unit of the tester according to the first embodiment of the present invention.

FIG. 4 is a schematic diagram showing a process of rearranging a source program in the tester according to the first embodiment.

FIG. 5 is a diagram schematically illustrating an example of a source program input to the tester according to the first embodiment of the present invention.

FIG. 6 is a diagram schematically showing a relocation test number correspondence table.

FIG. 7 is a diagram schematically showing the result of the failure rate aggregation.

FIG. 8 is a diagram schematically illustrating a failure rate totalization table for each rearrangement test item.

FIG. 9 is a diagram schematically showing a test flow.

FIG. 10 is a diagram schematically showing a relocation completion source program.

FIG. 11 is a diagram schematically showing the contents of a program memory.

FIG. 12 is a diagram illustrating an overall configuration of a semiconductor device test system according to a second embodiment;

FIG. 13 is a block diagram of a server of the semiconductor device test system according to the second embodiment.

FIG. 14 is a block diagram of a tester of the semiconductor device test system according to the second embodiment.

FIG. 15 is a block diagram for explaining an overall function of a semiconductor device tester according to a third embodiment of the present invention.

FIG. 16 is a block diagram of a reallocation execution unit of the tester according to the third embodiment of the present invention.

FIG. 17 is a diagram schematically showing a flow of rearrangement of a source program according to the third embodiment of the present invention.

FIG. 18 is a diagram schematically illustrating an example of a source program input to the tester according to the first embodiment of the present invention.

FIG. 19 is a diagram schematically showing a relocation test number correspondence table.

FIG. 20 is a diagram schematically showing the result of the defect rate totalization.

FIG. 21 is a diagram schematically illustrating a relocation test item-specific failure rate totalization table.

FIG. 22 is a diagram schematically showing a test flow.

FIG. 23 is a diagram schematically showing an edited test flow;

FIG. 24 is a diagram schematically showing a relocation completion source program.

FIG. 25 is a block diagram showing a configuration of a conventional semiconductor device tester.

[Explanation of symbols]

111 test result storage unit, 203 source program storage unit, 202 compiler, 204, 520, 61
0 tester, 205 execution program storage, 206,
614 relocation instruction unit, 207 relocation information storage unit, 2
08, test result totaling unit, 209, 612 reallocation execution unit, 209A test item extracting unit, 209B defect rate totaling unit, 209C test flow determining unit, 209D program rearranging unit, 211, 616 test number correspondence table storage unit, 250 , 252 communication unit, 401 relocation test number correspondence table, 402 relocation test item failure rate total table, 403 test flow, 501 server, 612D
Program relocation unit, 701 test flow.

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[Procedure amendment]

[Submission date] July 17, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claim 1

[Correction method] Change

[Correction contents]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claim 4

[Correction method] Change

[Correction contents]

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

In the conventional system, the above-described procedure is required to change the test program to a flow according to the defect occurrence rate and execute the test. Therefore, even if a test item having a defect in a lot unit or a wafer unit is followed, the operator must recognize the change in the test flow and perform the manual test flow change as described above. . Therefore, in the conventional test system, it is difficult to change the test flow in a timely manner, and it is difficult to reduce the test time. Therefore, for example, for a specific purpose of shortening the test time, a test system of a semiconductor device capable of automatically rearranging a test program according to a failure rate of a test result is required.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

However, in the conventional system, as described above, in order to change the test flow, the contents of the failure are investigated based on the test results inside the tester (112), and the test flow to be changed is determined (113). ), After editing the source program based on the test flow (114),
The work of compiling again and loading the execution program was necessary. When the source program is changed in this way, it is difficult to make an appropriate change unless the contents of the source program are detailed. Therefore, there is a problem that it takes time to perform the failure analysis.
Therefore, for example, for a specific purpose of facilitating the change of the test flow, there is a demand for a semiconductor device test system capable of automatically rearranging a test program in response to a test flow change instruction.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

In addition to the fact that such a process can be executed by a single tester, a server device of a semiconductor device test system for enabling a plurality of testers to execute the processes in parallel is also required.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

[0017]

According to a first aspect of the present invention, there is provided a semiconductor device test system for storing a test program for testing a semiconductor device which can be identified for each test item. Means, means for classifying test items of the test program,
Totalizing means for executing the program stored by the storing means and totalizing test results for each test item;
And means for rearranging the test items of the test program in a predetermined order based on the result of the classification by the classifying means and the result of the counting by the counting means.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

According to a fourth aspect of the present invention, there is provided a server device of the semiconductor device test system, wherein each of the plurality of servers can execute a test program for testing a semiconductor device and capable of identifying each test item. A communication device for communicating with the plurality of test devices, storage means for storing the test program, means for classifying test items of the test program based on the identifier, and the test program stored by the storage means. Means for downloading and executing the test results to a plurality of test devices connected via the same, collecting test results and totaling them for each test item, the results of classification by the classifying means, and the totaling results by the totaling means. Means for rearranging the test items of the test program based on the predetermined order.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Change

[Correction contents]

[0027]

First Embodiment Referring to FIG. 1, a tester 2 according to a first embodiment of a semiconductor device test system of the present invention will be described.
04 is the source program 2 created for the test
01, as source programs 203A, 203B,..., A compiler 202 for compiling the source programs 203A, 203B,.
The execution program 22 created by the compiler 202
0A, 220B,..., A program memory 108, and a program type to be tested among execution programs registered in the execution program storage unit 205 in response to the program selection and loading instruction 106. It includes a loading unit 107 for selecting a program and loading it into the program memory 108, and a relocation information storage unit 207 for storing relocation information in response to the program relocation information instruction 210. Here, the relocation information is information indicating at what timing the relocation of the test program is executed. Examples of the relocation information are “each lot, every 10 wafers,
There is information such as "execute every 10 hours", "execute immediately after rearrangement instruction", or "do not execute rearrangement".

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0028

[Correction method] Change

[Correction contents]

The tester 204 further includes a test execution unit 109 for executing a test by executing the test program loaded in the program memory 108 and a pas for notifying the test result by the test execution unit 109 to the outside.
an s / fail notification unit 110 and a test result storage unit 111 for storing a test result by the test execution unit 109
And monitors the test status of the device at all times, and issues a program relocation instruction when the conditions for relocating the program are satisfied based on the relocation information stored in the relocation information storage unit 207. Instruction unit 206 for
In response to the instruction 230 from the rearrangement instruction unit 206,
Of the test results stored in the test result storage unit 111, the test result totaling unit 208 for totaling the failure rate of all test items for the amount specified by the relocation information.
In response to the relocation instruction from the relocation instruction unit 206,
To extract the relocation target test items from the source programs 203A, 203B,... Stored in the source program storage unit 203, and to rearrange the test items based on the test results totalized by the test result aggregation unit 208. And a test number correspondence table storage unit 211 for storing the rearrangement test number correspondence table 401 created by the rearrangement execution unit 209.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction contents]

FIG. 4 shows the flow of a table or the like created by each unit in FIG. Referring to FIG.
From 3A, a test item extraction unit 209A creates a relocation test number correspondence table 401. From the rearrangement test number correspondence table 401 and the failure rate aggregation result 208A, the failure rate aggregation section 209B creates a failure rate aggregation table 402 for each rearrangement test item. This relocation test item-specific defect rate summary table 402
The test flow determination unit 209C determines the test flow 403 based on the Based on the test flow 403 and the analysis result of the source program 203A, the program rearrangement unit 209D rearranges the program to create the rearrangement completion source program 301.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction contents]

The contents of each table shown in FIG.
This will be described below with examples. Referring to FIG. 5, a plurality of test items whose source program 203A is to be rearranged as shown in the drawing (test item numbers of these test items are A1, A2,... An, respectively. Each test item is represented by this test item number.) And other tests that are not to be rearranged. Each of the test items A1, A2,... An includes an arbitrary number of tests, and includes an identifier “START” indicating a start position and an identifier “E” indicating an end position.
ND ".

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0062

[Correction method] Change

[Correction contents]

The tester 610 shown in FIG. 15 is different from the tester 204 shown in FIG. 1 in that a test flow edit 601 and a test flow change which are connected to a test number correspondence table storage unit and a relocation instruction unit, respectively. That is, a function of an instruction 602 is added. In addition, this tester 61
0 is the relocation instruction unit 20 of the tester 204 of the first embodiment.
6. Instead of the relocation execution unit 209 and the test number correspondence table storage unit 211, a relocation instruction unit 614 having slightly different functions, a relocation execution unit 612, and a test number correspondence table storage unit 616 are included. .

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0065

[Correction method] Change

[Correction contents]

FIG. 16 shows the configuration of the relocation execution unit 612.
This will be described with reference to FIG. The reallocation execution unit 612 is different from the reallocation execution unit 209 of the first embodiment shown in FIG.
Test flow 701 newly edited by the test flow editing 601 in place of the program relocation unit 209D of FIG.
Accordingly, a different point is that a program rearrangement unit 612D that rearranges a source program in a different manner depending on the cause of a rearrangement execution instruction and outputs a rearrangement completed source program 702 is provided. The program rearrangement unit 612D also
It is also different from the program rearrangement unit 209D of FIG. 3 in that the test item extraction result is directly received from the test item extraction unit 209A.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0066

[Correction method] Change

[Correction contents]

FIG. 17 shows the flow of the process of rearranging the source program in the tester 610 according to the third embodiment. 17, the same or similar portions as those shown in FIG. 3 are denoted by the same reference characters, and detailed description thereof will not be repeated. 17 differs from FIG. 3 in that a test flow 701 that can be newly edited is included, and the rearrangement completion source program 702 is different from the test flow 403 in FIG.
Or 701.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0069

[Correction method] Change

[Correction contents]

In relocation executing section 612, with reference to FIG. 16, test item extracting section 209A extracts a test item and provides it to program relocating section 612D. Defect rate totaling unit 2
09B and the test flow determination unit 209C do not operate. The program rearrangement unit 612D analyzes the source program, rearranges the test items based on the test flow 701, and outputs the rearranged source item 702 as a rearrangement completed source program 702.

[Procedure amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0070

[Correction method] Change

[Correction contents]

Hereinafter, the rearrangement completion source program 7
02 is the same as that in the first embodiment, and will not be repeated here.

[Procedure amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0072

[Correction method] Change

[Correction contents]

FIG. 24 shows an example of the relocation completion source program 702. The example shown in FIG. 24 is the result of relocating the program according to the test flow 701.

[Procedure amendment 18]

[Document name to be amended] Statement

[Correction target item name]

[Correction method] Change

[Correction contents]

Further, also in the tester of the third embodiment, a network can be formed as in the system of the second embodiment.

[Procedure amendment 19]

[Document name to be amended] Statement

[Correction target item name] Explanation of sign

[Correction method] Change

[Correction contents]

[Description of Signs] 111 Test Result Storage Unit, 203 Source Program Storage Unit, 202 Compiler, 204, 520, 61
0 tester, 205 execution program storage, 206,
614 relocation instruction unit, 207 relocation information storage unit, 2
08 test result totaling unit, 209, 612 reallocation execution unit, 209A test item extracting unit, 209B defect rate totaling unit, 209C test flow determining unit, 209D program rearranging unit, 211, 616 test number correspondence table storage unit, 250, 252 communication unit, 401 relocation test number correspondence table, 402 relocation test item failure rate total table, 403 test flow, 501 server, 612D
Program relocation unit, 701 test flow.

[Procedure amendment 20]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

[Procedure amendment 21]

[Document name to be amended] Drawing

[Correction target item name] Fig. 5

[Correction method] Change

[Correction contents]

FIG. 5

[Procedure amendment 22]

[Document name to be amended] Drawing

[Correction target item name] Fig. 6

[Correction method] Change

[Correction contents]

FIG. 6

[Procedure amendment 23]

[Document name to be amended] Drawing

[Correction target item name] Fig. 7

[Correction method] Change

[Correction contents]

FIG. 7

[Procedure amendment 24]

[Document name to be amended] Drawing

[Correction target item name] Fig. 8

[Correction method] Change

[Correction contents]

FIG. 8

[Procedure amendment 25]

[Document name to be amended] Drawing

[Correction target item name] Fig. 9

[Correction method] Change

[Correction contents]

FIG. 9

[Procedure amendment 26]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 16

[Procedure amendment 27]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 28]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 24

Claims (5)

[Claims] 1. A storage means for storing a test program for testing a semiconductor device, which can be identified for each test item, a classification means for classifying test items of the test program, and a storage means for storing in the storage means By executing the said program,
Tabulating means for tabulating test results for each of the test items; and rearranging the test items of the test program in a predetermined order based on the result of classification by the classifying unit and the tabulated result by the tabulating means. Semiconductor device test system comprising: 2. The semiconductor device test system according to claim 1, wherein said rearrangement means includes means for rearranging test items of said test program in descending order of test items having a high defect rate. 3. A test flow editing means for editing a test flow by a test program in test item units, and instructing rearrangement of the test program according to the test flow edited by the test flow editing means. 3. The semiconductor device test system according to claim 1, further comprising: an instruction unit for executing the rearrangement in response to the instruction from the instruction unit. 4. A communication apparatus for communicating with a plurality of test apparatuses each of which is capable of executing a test program for testing a semiconductor device and capable of identifying a test item for each test item; Storage means for storing test items based on the identifier; and the plurality of tests connected to the test program stored in the storage means via the communication device. Means for downloading and executing each of the devices, collecting test results and totaling the test items for each of the test items; a classification result by the classification means; Means for rearranging test items in a predetermined order. 5. The server device of the semiconductor device test system according to claim 4, wherein said rearrangement unit includes a unit for rearranging test items of said test program in descending order of test items having a high defect rate.