JPH11331840A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a video signal processor high in the operating rate of a decoder and capable of displaying plural videos simultaneously. SOLUTION: A demultiplexer 4 demultiplexes respective compressed video data from a transport stream. In this case, from which output port among plural output ports and which compressed video data are to be outputted is preset depending on a profile and a level. Which part of received compressed video data decoders 51, 52 decode is preset depending on a video format of the video data. Thus, same compressed high definition video data such as 1080i data are given to the decoders 51, 52, which take partial charge of decoding the data. Different compressed standard video data such as 480i data are given to the decoders and the decoders decode separate video data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a video signal processing apparatus, and more particularly to decoding of MPEG2 compressed video data and the like.

[0002]

2. Description of the Related Art FIG. 9 is a diagram showing a conventional video signal processing apparatus described in Nikkei Micro Devices, May 1997, page 66. In FIG. 9, 1 is an antenna, 2
Is a tuner, 3 is a demodulator, 4 is a demultiplexer, 51
And 52 are decoders, 6 is a display processor,
7 is a video output.

FIG. 10 is a diagram showing a conventional demultiplexer 4. As shown in FIG. In FIG. 10, reference numeral 400 denotes a distributor for separating packets of a transport stream, 402 denotes a transport stream input, 403 denotes a compressed audio data output, 404 denotes other data outputs, and 405 denotes a compressed video data output.

FIG. 11 shows a conventional display processor 6.
FIG. In FIG. 11, 7 is a video output,
620 is a switch, 621 is a judging unit for judging a decoding area, 631 and 632 are inputs of decoding results of the decoders 51 and 52, and 641 and 642 are memories for storing decoded data.

[0005] The antenna 1 outputs the received RF signal to the tuner 2. However, when the antenna 1 is a satellite broadcasting antenna, an IF signal is output from a converter attached to the satellite broadcasting antenna. In Tuner 2, this RF
Channel selection is performed by performing frequency selection processing on the signal or the IF signal. Then, the extracted signal is restored to a transport stream by the demodulator 3. Further, in the restored transport stream, the distributor 400 of the demultiplexer 4 separates data constituting the transport stream, for example, compressed video and compressed audio data. Then, the separated video data is output to the decoders 51 and 52. The reason why two decoders are provided is that a high-definition video requires a large amount of processing to decode the high-definition video, and cannot be decoded by only one decoder currently in practical use.

If the received video data is high-definition video (here, 1080i), the decoders 51, 5
2 decodes the video data. For example, the screen is divided into upper and lower parts, and the upper half is decoded on the one side and the lower half is decoded on the other side. If the received video data is a standard video (480i in this case), decoding is performed by only one decoder. The decryption result is then passed to the display processor 6. In this case, the decoder 51
Information indicating the video format is passed to the display processor 6 as a decoded result together with the decoded video data.

The display processor 6 includes a decoder 5
The decryption results passed from
1,642. And the memories 641 and 642
One screen is constructed by reading out the decryption results stored in the. The reading method in this case differs depending on the type of the video at that time and the display mode.

The image at this time is a high definition image (1080i)
In the case of, one screen is configured by combining the decoding results stored in the memories 641 and 642.
This combination is realized by switching the memory from which the video data is read at a predetermined timing by the switch 620. For example, the switch 62 is configured to read data from the memory 641 when outputting data in the upper half of the screen, and to read data from the memory 642 when outputting data in the lower half of the screen.
Switch 0.

On the other hand, the image at this time is a standard image (48
In the case of 0i), the decoding result is output only from the decoder 51. The display processor 6 stores this in the memory 64
1 and read it out as it is to constitute one screen. In this case, the switch 620 is always in a state where the memory 641 is selected.

The selection state of the switch 620, that is, the type of video at this time is determined as follows. That is, the decoding result output from the decoder 51 and stored in the memory 641 includes information indicating the video format of the video. The determination unit 621 in the display processor 6 reads out this information and determines its contents, thereby determining the type of video at that time. Then, the switch 620 is switched according to the determination result.

[0011]

In the conventional video signal processing apparatus, when high-definition video is not decoded, one of the decoders, in the above-described example, the decoder 52 is not used at all and is wasted. . When high-definition video is not transmitted, a plurality of 480i or 480p
Although there is a high possibility that the video signal is transmitted, there is a problem that only one of the video signals can be viewed. In order to view two images simultaneously, it is necessary to provide two systems of the entire circuit shown in FIG. 9, which has been difficult to realize in terms of cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a video signal processing apparatus having a high operation rate of a decoder and capable of enjoying a large number of digital images on one screen.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to achieve the above-mentioned object, and provides a desired compressed video signal from a multiplexed compressed video signal obtained by multiplexing compressed video data which is compressed video data. In a video signal processing device for extracting only data and decoding the same, a plurality of output ports are provided, and individual compressed video data is separated from the multiplexed compressed video signal. A separation unit configured to output data from one or more desired output ports, and the output port configured to decode the compressed video data separated by the separation unit and output the decoding result as decoded video data A decoding unit provided for each, and the decoded video data,
And a display processing unit that converts the signal into a signal that can be displayed on the display device.

In the case where the video data is based on the MPEG2 standard and the multiplexed compressed video data is a transport stream, the separation unit may generate the compressed video data based on a profile and a level of the video data. Is preferably set.

It is preferable that the decoding units to which the same compressed video data is input from the separation unit share the same and decode the compressed video data.

The decoding section has a capability of decoding at least a half of an interlaced image having 1080 scanning lines, and the separation section has at least two output ports. Among the compressed video data separated from the multiplexed compressed video signal, the number of scanning lines is 480.
1 for each compressed video data of interlaced video of a book
One decoding unit is assigned, and one decoding unit is assigned to one piece of compressed video data of line-sequential scanning video having 480 scanning lines, and one piece of compressed video data of line-sequential scanning video having 720 scanning lines is assigned. Video signals may be output from each output port such that two decoding units are allocated to each of the compressed video data of the interlaced video having 1080 scanning lines.

The decoding unit has a capability of decoding at least a quarter of an interlaced video having 1080 scanning lines, and the separation unit has at least four output ports. Among the compressed video data separated from the multiplexed compressed video signal, the number of scanning lines is 480.
1 for each compressed video data of interlaced video of a book
One decoding section is allocated, and two decoding sections are allocated to one piece of compressed video data of line-sequential scanning video having 480 scanning lines, and one piece of compressed video data of line-sequential scanning video having 720 scanning lines is provided. Video signals may be output from each output port such that four decoding units are allocated to each of the compressed video data of the interlaced video having 1080 scanning lines.

According to a second aspect of the present invention, there is provided a video signal processing for extracting only desired compressed video data from a multiplexed compressed video signal obtained by multiplexing compressed video data which is compressed video data and decoding the same. In the apparatus, each of which separates desired compressed video data from the multiplexed compressed video signal, a plurality of separating units, and decodes the compressed video data separated by the separating unit, and decodes the decoded result into decoded video data. A decoding unit, which is provided in the same number as the separation units, and a switching unit that switches an input / output relationship between the separation unit and the decoding unit according to a video format of the decoded video data; A display processing unit for converting the video data into a signal that can be displayed on the display device, wherein the video format of the decoded video data is predetermined. In this case, the switching means causes the decoded video data to be input to a plurality of decoding units, and the decoding units to which the same compressed video data is input share each other and decode the compressed video data in parallel. A video signal processing device characterized by the following.

In the first and second aspects described above, the decoding unit determines an area to be decoded in the input compressed video data according to its video format, Decoding sections to which the same compressed video data is input may have different areas set as decoding areas.

The display processing section combines a plurality of decoded video signals constituting a part of one video into one video and outputs the synthesized video signal, while decoding a plurality of different videos. As for the video signal, it is preferable to divide the screen into a plurality of regions and display each video in each region.

[0021]

Embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 In the first embodiment, the MPE
G2 (Moving Picture Experts
This is a video signal processing device that processes video data compliant with Group Phase 2). Particularly, in the present embodiment, a video signal requiring a large amount of processing per unit time required for decoding is shared and decoded by a plurality of decoders, while a video signal requiring a small amount of processing per unit time required for decoding is provided by a plurality of decoders. The main feature is that different video signals are decoded by each decoder when they are included. The amount of processing per unit time required for decoding is basically larger as the resolution of an image is higher. However, this processing amount is not determined only by the resolution, but also depends on the transmission rate at the time of transmission, the compression method, and the like. Therefore, in the present embodiment, before decoding, the profile and level specified in MPEG2 are used. Based on the video format after decoding, the sharing method is set in advance.

Hereinafter, Embodiment 1 will be described in detail with reference to FIG. 1, FIG. 2 and FIG.

As shown in FIG. 1, the video signal processing apparatus according to the first embodiment has a demultiplexer 4, a decoder 51,
52, and a display processor 6. The same components as those in the conventional example are denoted by the same reference numerals, and description thereof is omitted. The antenna 1, the tuner 2, and the demodulator 3 are the same as in the related art.

The demultiplexer 4 determines, based on information contained in the packet of the transport stream input from the demodulator 3, whether the transmitted data is, for example, a video or not. Are determined, and each of them is separated and output. MPEG
In No. 2, an ID number for identifying a packet is added to a header portion of the packet. As information for identifying whether the content of each packet is video or audio, a program association table is provided for a packet with ID = 0, and a program map table is provided for a packet with ID = 1. Is provided. The demultiplexer 4 performs the above-described determination based on information described in the program association table and the program map table. Further, the structure of the video data separated by the demultiplexer 4 has a hierarchical structure defined by MPEG2. That is, the sequence header and the sequence extension provided at the head describe the profile and level that define the capability required of the decoder, information indicating the video format, for example, the number of pixels in the horizontal direction and the number of scanning lines. .

Demultiplexer 4 in the present embodiment
Specifically, as shown in FIG. 2, the device includes a distributor 400 and a switch 401. Outputs include a compressed audio data output 403 and other data output 4
04, compressed video data outputs 405 and 406.

The switch 401 in FIG.
This is for switching the compressed video data output from the 5,406. In particular, in the first embodiment, what kind of compressed video data is output from the outputs 405 and 406 is actually set in advance in the demultiplexer 4 in accordance with the profile and level specified in MPEG2. Have been. In the present embodiment, in the case of a high definition video, the output 405 and the output 406
And the same compressed video data is output from both. When a plurality of standard images (480i) and 480p images are included, the demultiplexer 4 selects two of them and outputs them separately from the outputs 405 and 406. The output 405 is connected to the decoder 51.
Meanwhile, the output 406 is input to the decoder 52.

The decoders 51 and 52 are for decoding the compressed video data input from the demultiplexer 4. The decoders 51 and 52 have a function of determining a data area to be decoded by itself according to a video format described in a sequence header or the like of the input compressed video data. Which region is to be decoded is preset in the decoders 51 and 52 according to the video format of the video.
More specifically, when a high-definition video (1080i or 720p in the present embodiment) is input, the decoder 51 decodes only the upper half of the video and when a normal standard image is input. Is set to decode the whole. On the other hand, the decoder 52 is set to decode only the lower half when a high-definition video is input, and to decode the whole when a normal standard image is input. . In other words, decoders to which the same compressed video data is input have their decoding areas set so that they share the same and decode the compressed video data. The decoders 51, 52 each have the necessary and sufficient capacity to decode at least half of the high definition video.

The correspondence between the decoder capabilities (profile and level) and the video data compliant with MPEG2 is as follows. That is, main profile @ main level corresponds to an image of 480i. The main profile @ high level (1440) corresponds to an image of 480p. The main profile @ high level corresponds to a high definition video (1080i, 720p).

The decoders 51 and 52 output the decoding result to the display processor 6. The decoding result includes, in addition to the decoded video data, the video format included in the above-described sequence header and the like. ing.

The display processor 6 includes a decoder 5
Decoding results are received from the decoding devices 1 and 52, and one screen is constituted by the video data included in the decoding results. The display processor 6 is shown in FIG.
, The memories 641 and 642, the determination unit 621,
A switch 620 and filters 650 and 651 are provided.

The memory 641 stores the decoding result sent from the decoder 51. Memory 64
Numeral 2 stores the decoding result sent from the decoder 52.

The judging section 621 and the switch 620 switch the source (memory 641 and memory 642) of the data to be read at that time according to the video format included in the decoding results stored in the memories 641 and 642. Depending on the manner of operation of the determination unit 621 and the like, one screen is constituted, for example, one image is displayed on the entire screen, or one screen is divided into two right and left, and different images are displayed in respective areas. Is determined. The manner of these operations, that is, the switching of the switch 620, is set in the display processor 6 in advance according to the video format.

The filters 650 and 651 perform pixel interpolation of video data. These filters 650, 6
By performing pixel interpolation by 51, an image can be displayed on the entire screen of the display device even when the resolution of the video data is different from the resolution of the display device.

The term “separator” in the claims corresponds to the demultiplexer 4 in the present embodiment. The “decoding unit” corresponds to the decoders 51 and 52. The “display processing unit” corresponds to the display processor 6. The “multiplexed compressed video signal” corresponds to a transport stream. “Output ports” correspond to the outputs 405 and 406 of the demultiplexer 4. “Decoded video data” corresponds to the decoding result output from the decoders 51 and 52.

Next, the operation will be described.

The RF signal received by the antenna 1 is output to the tuner 2. However, when the antenna 1 is a satellite broadcast antenna, an IF signal from a converter attached to the satellite broadcast antenna is output to the tuner 2.
In the tuner 2, frequency selection processing, that is, channel selection is performed on the RF signal or the IF signal. Then, the extracted signal is restored to a transport stream by the demodulator 3. Then, this transport stream is output to the input 402 of the demultiplexer 4.

The demultiplexer 4 separates video data, audio data and the like from packets of the transport stream input from the demodulator 3. The separated data are distributed by the distributor 400 and output from the corresponding outputs 403, 404, and the like. In this case, for the compressed video data, a switch 4 is further provided according to the profile and level of the compressed video data.
By switching 01, the compressed video data output from the outputs 405 and 406 is switched. Specifically, when the data is a high definition video, the output 405 and the output 406
Output the same compressed video data from both. On the other hand, when a plurality of standard images (480i) and 480p images are included, the demultiplexer 4 selects two of them and outputs them separately from the outputs 405 and 406. In this case, the structure of the video data separated by the demultiplexer 4 is a hierarchical structure defined by MPEG2, and the sequence header and the sequence extension include information indicating a profile, a level, and a video format (for example, a horizontal direction). Number of pixels, number of scanning lines, aspect ratio,
Frame rate, interlace / progressive) and the like.

The decoders 51 and 52 confirm the video format of the video by confirming the sequence header and the like of the video data input from the demultiplexer 4 at that time. Then, only the area set in advance according to the video format is decoded. When a high-definition video is input, the areas to be decoded are different between the decoder 51 and the decoder 52. Therefore, as a result, the decoder 51 and the decoder 52 share each other and decode the entire high definition video. The decoders 51 and 52 output a decoded result including the decoded video data and the video format to the display processor 6.

The display processor 6 includes a decoder 5
The decoding results input from the memory devices 1 and 52 are stored in the memory 641 and the memory 642, respectively. The determination unit 621 of the display processor 6 determines the video format included in the decoding result, and forms one video by switching the switch 620 at a predetermined timing according to the determination result. That is, when the original video is one high-definition video, the switch 62
0 is switched at half the position of one field to compose one screen. On the other hand, when the decoder 51 and the decoder 52 are decoding different images, the switch 620 is switched at a half position of one line. Thus, one screen can be divided into a right half area and a left half area, and different images can be displayed for each area. When a user's selection instruction is received at an operation unit (not shown), only an image selected from any of a plurality of images is displayed.

When two video signals are displayed on the left and right of one screen, the video data may not match the resolution of the display. For example, 1920 horizontal pixels and 10 vertical pixels
80 lines of high-definition display with 720 horizontal pixels
When displaying two standard images composed of 480 vertical lines, they are not displayed on the entire screen. However, if the pixels are interpolated by the filters 650 and 651, they can be displayed on the entire screen. When the decoder is decoding a high definition video, the filters 650 and 651 are in an invalid state. However, when one standard image is displayed on the entire screen, or when two standard images are displayed side by side on one screen, the filter 650 or the like performs pixel interpolation to thereby input the standard image. The video is converted to a 1920 × 1080 image.

When displaying two or more videos at a time, the user accepts the selection of audio, and the distributor 400 separates only the compressed audio data of the selected video and outputs it from the audio data output 403.

According to the video signal processing apparatus of the first embodiment described above, a video signal requiring a large amount of processing per unit time for decoding is decoded using a plurality of decoders, and the unit time required for decoding is When a plurality of video signals with a small processing amount per unit are included, each video signal is decoded by each decoder. In addition, the display processor can display one or a plurality of decoded video signals on one screen by dividing one or a plurality of screens. Therefore, the decoder and the like can be used more effectively.

In the present embodiment, the decoding area is set in advance for each decoder, so that the decoders share the decoding without communicating with each other. However, the way of sharing is not limited to the present embodiment. For example, an independent control unit may be provided, and after the control unit determines a video format, each decoder may specify an area to be in charge of decoding.

Embodiment 2 The second embodiment is mainly characterized in that four decoders are provided, and these are selectively used according to the profile and level of video data, the video format, and the like. The configuration of the second embodiment corresponds to the provision of four decoders, except that the output of the demultiplexer 4, the memory in the display processor 6, and the like are divided into four systems. Is the same as Therefore, the following description focuses on the differences from the first embodiment.

FIG. 4 is a block diagram showing an outline of a video signal processing device according to the second embodiment. FIG. 5 is a block diagram showing a configuration of the demultiplexer 4 according to the second embodiment. FIG. 6 is a block diagram illustrating a configuration of the display processor 6 according to the second embodiment. In FIG. 4, reference numerals 51, 52, 53 and 54 are decoders. In FIG. 5, reference numeral 400 denotes a distributor having outputs of four systems a, b, c, and d. Reference numeral 401 denotes outputs 405, 406, 407, and 4 of the data output from the systems a, b, c, and d.
08 is a switch for switching the compressed video data to be output. The setting state of the switch 401 is determined in advance according to the profile and the level, and is specifically as shown in Table 1. In FIG. 6, reference numerals 631, 632, 633, and 634 denote decoding result input from the decoder, and 641, 642, 643, and 644.
Is a memory, 661 and 662 are switches, 671 and 672
Is a memory.

[0047]

[Table 1]

The demultiplexer 4 has four outputs (a, b, c, d) of compressed video data, except that
Basically, it is similar to the first embodiment.

In the demultiplexer 4, the internal distributor 4
00 and the switch 401 operate in cooperation,
The predetermined compressed video data is output from a predetermined predetermined system.

If the separated compressed video data is for one high-definition video, the distributor 400 outputs this to the system a. As shown in Table 1, the state of the switch 401 changes according to the format of the input video. As shown in Table 1, in this case, output 4
05, 406, 407 and 408 all output the compressed video data of system a.

The separated compressed video data is divided into two 480
For a line-sequential image of p, the distributor 400
Outputs one compressed video data to the system a and the other compressed video data to the system c. In this case, as shown in Table 1, the switch 401 outputs the compressed video data input to the system a to the outputs 405 and 406 and the compressed video data input to the system c to the outputs 407 and 408. .

When the separated compressed video data is one 480
If it is for a line-sequential image of p and for two standard images, distributor 400 will add 480 to system a.
The compressed video data of the p-line sequential video, the compressed video data of one standard video is output to the system c, and the compressed video data of the other standard video is output to the system d. In this case, as shown in Table 1, the switch 401 outputs the compressed video data of the 480p line-sequential video input to the system a to the output 40.
5,406. In addition, 4 input to system c
The 80i standard video signal is output to the output 407, and the compressed video data of the 480i standard video input to the system d is output to the output 408.

If the separated compressed video data is for four standard videos, the distributor 400 controls the system a,
The compressed video data of the standard video is 1 for each of b, c, and d.
Assign and output one by one. In this case, as shown in Table 1, the switch 401 causes the output 405 to output the compressed video data of the standard video input to the system a. Similarly, the compressed video data of the standard video input to the system b is output to the output 406, the compressed video data of the standard video input to the system c is output 407, and the compressed video data of the standard video input to the system d is output. The data is output to the output 408.

The compressed video data output from the outputs 405, 406, 407 and 408 is
2, 53, and 54, where they are decoded. In this case, the compressed video data output to the output 405 is output to the decoder 51, the compressed video data output to the output 406 is output to the decoder 52, the compressed video data output to the output 407 is output to the decoder 53, and the output 408 is output. The compressed video data is input to the decoder 54.

In this case, the sharing of the area to be decoded between the respective decoders is as follows. When the compressed video data is for a high-definition video, the video is divided into four in the vertical direction, and each section is divided into decoders 51, 52,
53 and 54 share one by one. In the case of the 480p line sequential video, the video is divided into two in the vertical direction, and one decoder is assigned to the upper half and the other decoder is assigned to the lower half. Which section each decoder decodes is preset in each decoder according to the video format. If each decoder has a capability of decoding a quarter of a 1080i video, it can also decode the standard video signal (480i) with a margin. The video data decoded in this way is output to the display processor 6.

The display processor 6 composes a screen in accordance with the original video format from the decoding results input from the four decoders 51, 52, 53, 54.
Hereinafter, the operation inside the display processor 6 will be described in detail with reference to FIG.

The decoding result output from the decoder 51 is input to the input 631 of the display processor 6, and the input data is stored in the memory 641. Similarly, the decoding result of the decoder 52 is stored in the memory 642 through the input 632. The decoding result of the decoder 53 is stored in the memory 643 through the input 633. The decoding result of the decoder 54 is stored in the memory 644 through the input 634.

The display processor 6 switches the switch 6 according to the image format of the image input at this time.
One screen is configured by switching among 61, 662, and 620. Table 2 shows the settings of the switches 661, 662, and 620.

[0059]

[Table 2]

For example, if the video data at this time is for a high-definition video, the memory 641 stores the upper quarter of one image. Similarly, the memory 6
42, 643, and 644 also store quarters of one image in order. Therefore, the upper half of the screen is formed by switching the switch 661 so that data is continuously transferred from the memory 641 to the memory 642. Then, the composed upper half image is stored in the memory 671. Similarly, the lower half of the screen is configured by switching the switch 662 so that data is continuously transferred from the memory 643 to the memory 644. Then, the composed lower half image is stored in the memory 672. Further, one screen is configured by switching the switch 620 at a half position of the field as in the first embodiment. Switches 661, 662, 62
Is performed based on the result of the determination unit 621 determining the video format included in the decoding result.

The video data at this time is two different 480
In the case of a p-line sequential image, the screen is divided into two right and left, and each image is displayed side by side. in this case,
The upper half of one image is stored in the memory 641, and the lower half is stored in the memory 642. Therefore, switch 66
One screen is configured by switching 1 at half the position of the field, and the configured screen is stored in the memory 671. As for the other video, the upper half is in the memory 643,
The lower half is stored in the memory 644. Therefore, similarly, one screen is formed by switching the switch 662 at a half position of the field, and the formed video is stored in the memory 672. Further, by switching the switch 620 at a half position of one line, the memory 671 is switched.
And the video stored in the memory 672 are displayed separately on the left and right sides of the screen.

The video data at this time is a total of 3 of one 480p line sequential image and two different 480i line sequential images.
One or two of these
Select one to display. When displaying two images, the screen is divided into two right and left, and the two images are displayed side by side. In this case, the upper half of the 480p video is stored in the memory 641, and the lower half is stored in the memory 642. Therefore, one image is formed by switching the switch 661 at a half position of the field, and the formed image is stored in the memory 671. Regarding the two 480i videos, one is stored in the memory 643 and the other is stored in the memory 644. Therefore, by setting one of the memory 643 and the memory 644 to be selected by the switch 662, only one of the images is read and stored in the memory 672. Further, by switching the switch 620 at half the position of one line, the memory 6
The video stored in the memory 71 and the video stored in the memory 672 are displayed separately on the left and right sides of the screen. In this case, the video stored in the memory 672 is converted into 480p by being processed by the filter 651, and is output.

If the image data at this time is for four 480i standard images, the memories 641, 6
42, 643, and 644 each store one standard image. Therefore, in this case, the screen is divided into four parts, upper, lower, left, and right, and an image is displayed one by one in each area. Such a display can be made by switching the switches 661 and 662 at half field positions and switching the switch 620 at half a line. Alternatively, the switches 661 and 662 can be switched by half of one line, and the switch 620 can be switched by half of the field.

However, in any of the above cases, it is needless to say that only one image can be displayed according to the user's selection.

Embodiment 3 The third embodiment is different from the above-described embodiment in that not only the decoder but also a plurality of demultiplexers are provided, so that video data is separately taken out from a plurality of transport streams and separately decoded by the decoder. different. Also, the correspondence between the demultiplexer and the decoder can be changed by a switch 8 described later. The details will be described below.

FIG. 7 is a block diagram showing the third embodiment. In FIG. 7, 41 and 42 are demultiplexers, and 8 is a switch. Further, the demodulator 3 according to the third embodiment has a capability of outputting two transport streams from one physical channel.

When two or more transport streams are included in one physical channel, the demodulator 3 separates a predetermined number (two in this embodiment) of transport streams and separates each transport stream. Output to separate demultiplexers 41 and 42. At this time, a high-definition video having a large processing amount per unit time required for decoding is output to the demultiplexer 41 side. Actually, the output destination is set in advance in the demodulator 3 in accordance with the profile and level specified in MPEG2, and the output destination is selected according to the setting.

The demultiplexers 41 and 42 are similar to the conventional demultiplexer shown in FIG. 10, and separate and output the compressed video data.

Normally, the switch 8 connects the decoder 52 to the demultiplexer 41. However, the decoder 51
Only when the control signal 501 is output from the controller, the state is switched so that the decoder 52 is connected to the side of the demultiplexer. When the output of the demultiplexer 41 is the compressed video data of the high definition video, the decoder 51 does not output the control signal 501. Therefore, both the decoder 51 and the decoder 52 receive the compressed video data of the high-definition video output from the demultiplexer 41. On the other hand, the demultiplexer 4
If the output of No. 1 is compressed video data for the standard video (480i), the decoder 51 outputs a control signal 501 to the switch 8. The switch 8 is accordingly switched to the demultiplexer 41 side. As a result, the output of the demultiplexer 41 is supplied to the decoder 51.
On the other hand, the output of the demultiplexer 42 is input to the decoder 52. The outputs of the decoders 51 and 52 are thereafter processed in the same manner as in the first embodiment, and output from the video output 7.

The "switching means" in the claims is realized by the decoder 51 and the switch 8 in the present embodiment.

Embodiment 4 The video signal processing apparatus according to the fourth embodiment is an example in which a plurality of tuners, demodulators, and demultiplexers are provided.

FIG. 8 is a block diagram showing the fourth embodiment. In FIG. 8, 21 and 22 are tuners, and 31 and 3
Reference numeral 2 denotes a demodulator, and the other parts have the same configuration as that of the third embodiment.

When receiving a plurality of transport streams from a plurality of physical channels (including a case where networks such as BS and CS are different), a plurality of transport streams are received via separate tuners, demodulators, and demultiplexers (2 in FIG. 1). ) Of compressed video data. Subsequent steps are the same as in the third embodiment.

In the embodiment described above, two or four demultiplexers and decoders are provided. However, these numbers are not limited to this.

In the above-described embodiment, an apparatus for processing video data conforming to MPEG2 has been described. However, the application of the present invention is not limited to a device that processes video data conforming to MPEG2. Further, the number of decoders assigned to one piece of compressed video data is not limited to the above-described example.
What is necessary is just to set according to the processing amount per unit time required for decoding the compressed video data and the processing capability of the decoder.

[0076]

According to the video signal processing apparatus of the present invention, the following effects can be obtained.

Since the separating section has a plurality of output ports for compressed video data and a decoding section for each output port, a plurality of videos can be decoded at one time, so that the operating rate of the decoding section is extremely high. There is no waste.

In addition to determining the amount of processing per unit time required for decoding or the data (for example, profile and level) having different settings according to this, the compressed video data to be output from each output port is determined. In a configuration in which each decoding unit shares one video as necessary or separately decodes different videos, it is possible to cope with videos of various video formats. Moreover, the operation rate of the decoding unit is extremely high, and there is no waste in the system.

Even in a configuration in which a plurality of separation units and decoding units are provided and their connection relations can be switched by switching means, it is possible to cope with videos of various video formats. Moreover, the operation rate of the decoding unit is extremely high, and there is no waste in the system. Furthermore, compressed video data can be arbitrarily selected and decoded from a plurality of transport streams. Therefore, a plurality of videos transmitted through different physical channels or broadcast networks can be processed at a time.

In the case where the display processing unit is further provided with a structure for displaying a plurality of images on one screen at the same time, a plurality of images decoded in parallel can be displayed on the one screen at a time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal processing device according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a demultiplexer according to the first embodiment.

FIG. 3 is a block diagram illustrating a configuration of a display processor according to the first embodiment.

FIG. 4 is a block diagram illustrating a configuration of a video signal processing device according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a demultiplexer according to a second embodiment.

FIG. 6 is a block diagram showing a configuration of a display processor according to a second embodiment.

FIG. 7 is a block diagram illustrating a configuration of a video signal processing device according to a third embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a video signal processing device according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional video signal processing device.

FIG. 10 is a block diagram showing a configuration of a conventional demultiplexer.

FIG. 11 is a block diagram illustrating a configuration of a conventional display processor.

[Explanation of symbols]

1 antenna, 2 tuner, 3 demodulator, 4
Demultiplexer, 6 display processor, 8
Switch, 21, 22 Tuner, 31, 32
Demodulator, 41, 42 demultiplexer, 51, 5
2,53,54 decoder, 400 distributor, 40
1 switch, 620 switch, 621 judgment unit,
641,642,643,644,671,672
Memory, 661,662 switch, 650,65
1 Filter.

Claims (8)

[Claims] 1. A video signal processing apparatus for extracting only desired compressed video data from a multiplexed compressed video signal obtained by multiplexing compressed video data, which is compressed video data, and decoding the same, includes a plurality of output ports. Separating the individual compressed video data from the multiplexed compressed video signal, and converting desired compressed video data among the separated compressed video data to 1 or 2
A separating unit configured to be able to output from the above desired output port, and provided for each of the output ports for decoding the compressed video data separated by the separating unit and outputting the decoding result as decoded video data. A video signal processing device, comprising: a decoding unit; and a display processing unit that converts the decoded video data into a signal that can be displayed on a display device. 2. When the video data is based on the MPEG2 standard and the multiplexed compressed video data is a transport stream, the separating unit performs the compression based on a profile and a level of the video data. 2. The video signal processing device according to claim 1, wherein an output port for outputting video data is set. 3. The video signal processing apparatus according to claim 1, wherein the decoding units to which the same compressed video data is input from the separation unit share the same and decode the compressed video data. 4. The decoding unit has a capability of decoding at least a half of an interlaced video having 1080 scanning lines, and the separation unit has at least two output ports. And one decoding unit is assigned to each of the compressed video data of the interlaced scan video having 480 scanning lines out of the compressed video data separated from the multiplexed compressed video signal, and the number of scanning lines is 480. One decoding unit is assigned to one piece of compressed video data of a video of line sequential scanning, and the number of scanning lines is seven.
Two decoding units are assigned to one piece of compressed video data of 20 line-sequentially scanned images, and two decoding units are assigned to one piece of compressed video data of an interlaced image having 1080 scanning lines. The video signal processing device according to claim 3, wherein the video signal is output from an output port. 5. The decoding unit has a capability of decoding at least a quarter of an interlaced image having 1080 scanning lines, and the separation unit has at least four output ports. And one decoding unit is assigned to each of the compressed video data of the interlaced scan video having 480 scanning lines among the compressed video data separated from the multiplexed compressed video signal, and the number of scanning lines is 480. Two decoding units are assigned to one piece of compressed video data of the video of the line sequential scanning, and the number of scanning lines is 7
Four decoding units are assigned to one piece of compressed video data of 20 line-sequentially scanned images, and four decoding units are assigned to one piece of compressed video data of an interlaced image having 1080 scanning lines. The video signal processing device according to claim 3, wherein the video signal is output from an output port. 6. A video signal processing apparatus for extracting only desired compressed video data from a multiplexed compressed video signal obtained by multiplexing compressed video data, which is compressed video data, and decoding the extracted compressed video data, A plurality of separating units for separating desired compressed video data from the multiplexed compressed video signal, and the separating unit for decoding the compressed video data separated by the separating unit and outputting a decoding result as decoded video data; The same number of decoding units, switching means for switching the input / output relationship between the separation unit and the decoding unit according to the video format of the decoded video data, and a signal capable of displaying the decoded video data on a display device And a display processing unit for converting the video data into a video data. A video signal processing unit for inputting the decoded video data to a plurality of decoding units, wherein the decoding units to which the same compressed video data is input share and decode the compressed video data in parallel. apparatus. 7. The decoding section, wherein an area to be decoded of the input compressed video data is determined according to the video format, and a decoding section to which the same compressed video data is input from the separation section. 7. The video signal processing apparatus according to claim 1, wherein different areas are set as areas to be decoded. 8. The display processing unit combines a plurality of decoded video signals forming a part of one video into one video by combining them, and outputs a plurality of decoded video signals. 8. The video signal processing apparatus according to claim 1, wherein the video signal is divided into a plurality of regions and a video is displayed for each region.