JPH11317887A - Image processing unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To properly and quickly switch an operation mode in response to a connected image output device. SOLUTION: The image processing unit 1 is provided with an image processing circuit 11 consisting of a field programmable gate array FPGA that receives an image signal from an image output device 2 and applies image processing such as emphasis to the signal, a communication port 12 that receives an identification signal denoting a type of the image output device 2 from the image output device 2, a CPU 14 that applies write control to circuit data to the image processing circuit 11 via an I/F section 13 based on the identification signal received from the communication port 12, a ROM 15 that stores pluralities of circuit data to be written in the image processing circuit 11 and a control program of the CPU 14 in advance, and an SRAM 16 that stores data generated in the case of control by the CPU 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly, to an FPGA (Field Programmab).
The present invention relates to an image processing apparatus having a feature in a circuit data setting portion of the “le Gate Array”.

[0002]

2. Description of the Related Art Conventionally, in an image processing apparatus, for example, as disclosed in Japanese Patent Publication No. 1-26252, the type of image processing is switched according to the connected image output device. Although there is no disclosure in the above example as a method thereof, a simple method is to switch a path according to the type of image processing.

For example, as shown in FIG. 12, in a conventional image processing apparatus 101, a plurality of, for example, three image processing circuits 102, 10
3 and 104, each of which is subjected to separate processing and output to an output device 106 such as a monitor via a selection circuit 105. An identification signal indicating the type of an image output device (not shown) is transmitted from an external input unit (not shown) to the communication port 107.
Is input to the CPU 108 via the I / F unit 109 based on the identification signal.
The operation mode (type of image processing) is switched by controlling the image processing circuit 05 and selecting one of the image processing circuits 102, 103, and 104.

Japanese Patent Application Laid-Open No. 6-343137 discloses an example of a video camera whose operation mode changes according to the connection destination.

Recently, an FPGA (Field P)
An LSI called a programmable gate array has become widespread. A feature of the FPGA is that the circuit configuration can be rewritten. The circuit data of the FPGA can be stored in a memory or a medium in the form of binary data. FIG. 13 illustrates a method of switching the type of image processing using an FPGA.

In an image processing apparatus 110 using an FPGA, as shown in FIG. 13, an image signal from an image output device (not shown) is transmitted to an image processing circuit 11 constituted by an FPGA.
1 and processed by the image processing circuit 111 are output to an output device 106 such as a monitor. The configuration of the image processing circuit 111 is written by the CPU 108, and a plurality of circuit data are stored in the ROM 112 in advance. On the other hand, an identification signal indicating the type of an image output device (not shown) is input from an external input unit (not shown) to the CPU 108 via the communication port 107,
The CPU 108 selects circuit data from the ROM 112 based on the identification signal, and writes the circuit data to the image processing circuit 111 via the I / F unit 109. As described above, the operation mode (the type of image processing) can be switched according to the type of the image output device.

[0007]

SUMMARY OF THE INVENTION However, FPG
Although writing of A takes time, the above-described image processing apparatus 1
In 10, since the FPGA is written after the type of device is transmitted, if the transmission of the type is delayed for any reason, for example, if the power-on of the image output device is delayed, the operator will be notified. The problem is that you will have to wait longer.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an image processing apparatus capable of appropriately and promptly switching an operation mode according to a connected image output device. And

[0009]

According to the present invention, there is provided an image processing apparatus for processing an image signal input from an image output device, wherein a mode storage for storing an operation mode corresponding to a type of the image output device is provided. Means, mode processing means for processing the image signal according to the setting of the operation mode stored in the mode storage means, determination information input means for inputting determination information for determining the type of the image output device, and the mode processing The operation mode set in the means is compared with the operation mode corresponding to the type of the image output device determined by the determination information input by the determination information input means, and the operation mode is stored in the mode storage means based on the comparison result. Operating mode updating means for updating the operating mode.

In the image processing apparatus according to the present invention, the operation mode updating means determines the operation mode set in the mode processing means and the type of the image output device determined based on the determination information input by the determination information input means. By comparing the operation mode according to the above, and updating the operation mode stored in the mode storage unit based on the comparison result, switching of the operation mode according to the connected image output device, appropriately and Enables quick action.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

1 to 11 relate to an embodiment of the present invention. FIG. 1 is a diagram showing a connection relationship between an image processing device and an image output device. FIG. 2 is a diagram showing a configuration of the image processing device in FIG. FIG. 3 is a diagram showing a memory map of the SRAM of FIG. 2, FIG. 4 is a diagram showing a memory map of the ROM of FIG.
FIG. 6 is a flowchart showing the flow of processing by the CPU in FIG. 2, FIG. 6 is an explanatory diagram for explaining the connected device confirmation processing in step S3 in FIG. 5, FIG. 7 is a diagram showing an example of message display in step S5 in FIG. FIG. 8 is a block diagram showing an example of an image processing circuit constituted by an FPGA in which circuit data is written by the processing of FIG. 5, and FIG. 9 shows delays generated in the first block and the second block of FIG. FIG. 10 is an explanatory diagram for explaining a first FIFO circuit to be adjusted. FIG. 10 is an explanatory diagram for explaining a second FIFO circuit for adjusting a delay generated in the first block and the second block in FIG.
11 is a timing chart showing the timing of each signal of the FIFO circuit of FIG.

As shown in FIG. 1, in an image processing apparatus 1 according to the present embodiment, an image signal output from an image output device 2 is input via an image transmission unit 3, and the image processing device 1 The devices 1 are connected by a communication unit 4 so that one-way or two-way communication from the image output device 2 to the image processing device 1 can be performed.

As shown in FIG. 2, an image processing apparatus 1 receives an image signal from an image output device 2 via an image transmission means 3 and performs an image processing such as emphasis by using an FPGA (Field).
An image processing circuit 11 composed of a programmable gate array, a communication port 12 for inputting an identification signal indicating the type of the image output device 2 from the image output device 2, and an I / O based on the identification signal input from the communication port 12. A CPU 14 that controls writing of circuit data to the image processing circuit 11 via the F unit 13;
SRAM for storing data generated during control of U14
16 and a battery 17 for backing up the SRAM 16
And a display controller 18 for superimposing character data and the like on the image data processed by the image processing circuit 11.
And is provided.

Communication port 12, I / F unit 13, CPU1
4. The ROM 15, the SRAM 16, and the display controller 18 are connected to a data bus 19 by a CPU.
The respective circuits are controlled by 14 and the image data processed by the image processing circuit 11 on which the character data and the like are superimposed is output to an output device 20 such as a monitor.

As shown in FIG. 3, the SRAM 16 is provided with an operation mode data area 21 at a predetermined address position. As shown in Table 1, the operation mode data area 21 corresponds to the connected device. The operation mode data is stored numerically.

[0017]

[Table 1] In addition to the control program of the CPU 14, the ROM 15 stores the FP at a predetermined address position as shown in FIG.
A plurality of types of circuit data corresponding to the operation mode data to the image processing circuit 11 configured by the GA are stored in the first circuit data area 25, the second circuit data area 26, and the third circuit data area 27.

Next, the operation of the embodiment constructed as described above will be described.

As shown in FIG. 5, after the power is turned on, the CPU 1
4 reads the operation mode data held in the SRAM 16 in step S1 after initializing the basic hardware. Next, the circuit data corresponding to the operation mode data read in step S2 is read from the ROM 15, and the read circuit data is written to the image processing circuit 11 configured by the FPGA. At the same time, hardware setting according to the operation mode can be performed.

Then, in step S3, the image output device 2 actually connected is checked. The confirmation is performed by the communication means 4 via the communication port 12, for example, RS
-232C is known. FIG. 6 shows a procedure for confirming the connected device. First, from the image processing apparatus 1 to the image output device 2
Then, a “device type inquiry command” 31 is transmitted. Accordingly, the image output device 2 sends the image processing device 1
To the device type notification 32.

Note that the image output device 2 sends the image processing device 1
It is also possible that the device type is always transmitted and the image processing apparatus 1 appropriately receives the device type. In this case, the communication means 4 may be one-way communication.

Next, in step S4, the operation mode data corresponding to the image output device 2 obtained as described above is compared with the operation mode data stored in the SRAM 16. If the two match, the image processing circuit 11 corresponding to the image output device 2 has been written, and the process ends. If they are different, the process proceeds to step S5.

In step S5, the operation mode data corresponding to the actually connected image output device 2 is stored in the SRA
Store it in M16. In step S6, as shown in FIG. 7, the display controller 18 superimposes the message 36 on the processed image 35 of the image processing circuit 11, and informs the operator that correct circuit data has not been written to the image processing circuit 11. And terminate the process.

Here, it is assumed that the operator once turns off and on the power of the image output device 2 in accordance with the message 36.

The image processing apparatus 1 executes the procedure of the flowchart of FIG. 5 again. Step S1 to Step S3
Is the same as at the start-up. In step S4, the operation mode data stored in the SRAM 16 matches the operation mode data corresponding to the image output device 2 actually connected. This is because the operation mode corresponding to the image output device 2 that is actually connected is stored in the SRAM 16 in step S5 at the time of the previous startup.

Next, the operation of the image processing circuit 11 composed of an FPGA in which circuit data has been written under the control of the CPU 14 will be described.

As shown in FIG. 8, the image processing circuit 11 created based on the circuit data includes, for example, a first block 41 and a second block 41 which perform different processes on an input image signal.
Block 42, first block 41 and second block 4
And a synthesizing block 43 for synthesizing the image processed in Step 2.

Then, in the image processing circuit 11, the input image is input to the first block 41 and the second block 42, where different processing is performed. Each output is input to the synthesizing block 43, synthesized into one image, and output.

Here, for example, the first block 41 outputs the processing result of full-color 24 bits, and the second block 42
Is 1-bit information indicating whether to display the processed image,
It outputs so-called mask information.

At this time, if there is a difference in the delay between the first block 41 and the second block 42, the position of the image is shifted. Therefore, it is necessary to adjust one or both delays. Therefore, to adjust the delay, the FIFO (Fi
A rst In FirstOut = first in first out) memory is used.

The FIFO memory can be arbitrarily delayed, but the maximum value of the image size is limited to the range of the capacity. If an image of 640 dots × 480 lines is to be delayed, a capacity of 640 × 480 = 307,200 dots is required. If the capacity of the memory is smaller than this, a plurality is used to expand the capacity.

If the memory capacity is smaller than this,
To expand the capacity by using a plurality of memories, for example, in a FIFO circuit 50 as shown in FIG. 9, two inputs and outputs of which are connected in parallel, for example, a capacity of 262,144 dots (< 307 and 200 dots), and the two FIFO memories 51 and 52 are used.
Data is alternately input to the memories 51 and 52 one dot at a time, and output is alternately performed, thereby expanding the capacity.

The FIFO memory has an input / output data width, and is widely distributed with an 8-bit width. However, in actual applications, one bit information is sufficient, such as the above-described mask signal for an image. In such a case, if the 1-bit width data is delayed using the 8-bit width FIFO memory shown in FIG. 9, 7 bits of the FIFO memory are not always used and are wasted.

Therefore, a method for expanding the capacity without using a plurality of FIFO memories in such a case will be described.

As shown in FIG. 10, the 1-bit wide FIFO circuit 60 that has realized the capacity expansion is provided with a shift register 6.
1, a FIFO memory 62 and a selector 63. A signal input from Din is sent to a shift register 61 with reference to the timing chart of FIG. The data is converted from one bit to two bits and input to the FIFO memory 62.

The FIFO memory 63 has a pixel clock φ
The clock φ2 divided by 2 is supplied, and data from the shift register 61 is taken into the FIFO memory 62 at the timing of the rising edge ↑ of the clock φ2. The amount of delay of the FIFO memory 62 is determined by the time difference between the pulses of the write reset and the read reset, and the data input to the shift register 61 is output to the inputs D1 and D2 of the FIFO memory 62 after a certain delay time.

The outputs Q 1 and Q 2 of the FIFO memory 62 are returned from 2 bits to 1 bit again by the selector 63 and output from the selector 63. Note that the selector 63 may be configured by a shift register.

As described above, the image processing apparatus 1 according to the present embodiment
Then, after writing the circuit data previously stored in the SRAM 16 to the FPGA configuring the image processing circuit 11, the image output device 2 of the connection destination is performed. Therefore, the image processing device can be used without waiting for confirmation of the image output device 2. 1 can be launched. That is, for example, the image output device 2 to be connected
Even if the power-on of the image processing apparatus 1 is delayed, the image processing apparatus 1 can be started up first, and thereafter,
The operator does not have to wait a long time.

The FPG constituting the image processing circuit 11
If the type of the circuit data written in A is different from the type of the image output device 2, the circuit data corresponding to the image output device 2 of the connection destination is read from the ROM 15 and the SRAM 16 is read.
And the message instructs the restart of the image output device 2 of the connection destination, so that the operator restarts the image output device 2 in accordance with this message, so that the image processing apparatus 1 is reliably and easily. Can be launched.

[Appendix] (Appendix 1) In an image processing apparatus for processing an image signal input from an image output device, a mode storage means for storing an operation mode corresponding to a type of the image output device, and the mode storage A mode processing unit configured to process the image signal, a determination information input unit configured to input determination information for determining a type of the image output device, and a mode setting unit configured to set the mode processing unit. The operation mode is compared with the operation mode corresponding to the type of the image output device determined by the determination information input by the determination information input unit, and the mode stored in the mode storage unit is based on a comparison result. An image processing apparatus comprising: an operation mode updating unit that updates an operation mode.

(Additional Item 2) The mode processing means is
PGA (Field Programmable Ga)
2. The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus.

(Additional Item 3) In an image processing method for processing an image signal input from an image output device, the image processing method according to the type of the image output device for processing the image signal stored in a mode storage means. A mode setting step of setting an operation mode, a device determination step of determining the type of the image output device, the operation mode set in the mode processing step, and a type of the image output device determined by the device determination step Comparing with the operation mode according to,
An operation mode updating step of updating the operation mode stored in the mode storage means based on a comparison result.

[0043]

As described above, according to the image processing apparatus of the present invention, the image output determined by the operation mode updating means based on the operation mode set in the mode processing means and the determination information input by the determination information input means. Since the operation mode according to the type of the device is compared and the operation mode stored in the mode storage unit is updated based on the comparison result,
There is an effect that the operation mode can be switched appropriately and quickly according to the connected image output device.

[Brief description of the drawings]

FIG. 1 is a diagram showing a connection relationship between an image processing apparatus and an image output device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of the image processing apparatus of FIG. 1;

FIG. 3 is a diagram showing a memory map of the SRAM of FIG. 2;

FIG. 4 is a diagram showing a memory map of a ROM shown in FIG. 2;

FIG. 5 is a flowchart showing the flow of processing by the CPU of FIG. 2;

FIG. 6 is an explanatory diagram illustrating a connected device confirmation process in step S3 of FIG. 5;

FIG. 7 is a view showing an example of a message display in step S5 of FIG. 5;

8 is a configuration diagram illustrating an example of an image processing circuit configured by an FPGA that is realized by writing circuit data by the processing of FIG. 5;

9 is an explanatory diagram illustrating a first FIFO circuit that adjusts a delay generated in a first block and a second block in FIG. 8;

FIG. 10 is an explanatory diagram illustrating a second FIFO circuit that adjusts a delay generated in the first block and the second block of FIG. 8;

11 is a timing chart showing the timing of each signal of the FIFO circuit of FIG.

FIG. 12 is a configuration diagram showing a first configuration example of a conventional image processing apparatus.

FIG. 13 is a configuration diagram showing a second configuration example of a conventional image processing apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus 2 ... Image output equipment 11 ... Image processing circuit 12 ... Communication port 13 ... I / F part 14 ... CPU 15 ... ROM 16 ... SRAM 17 ... Battery 18 ... Display controller 19 ... Data bus 20 ... Output equipment

Claims (1)

[Claims] 1. An image processing apparatus for processing an image signal input from an image output device, wherein: a mode storage means for storing an operation mode corresponding to a type of the image output device; and the operation stored by the mode storage means. A mode processing unit configured to process the image signal by setting a mode; a determination information input unit configured to input determination information for determining a type of the image output device; an operation mode set in the mode processing unit; An operation of comparing the operation mode corresponding to the type of the image output device determined based on the determination information input by the determination information input unit and updating the operation mode stored in the mode storage unit based on the comparison result An image processing apparatus comprising: a mode updating unit.