JPH11317677A - Address generating device, interleave device and deinterleave device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To successively generate addresses jumping at a prescribed interval in a simple constitution by adding the 1st address data having a prescribed address interval to the 2nd address data, which show the positions that are successively shifted 1 every row to the 1st address data at each address interval. SOLUTION: At a write address generation part 51, the write addresses WA10 are generated at every prescribed address interval and in response to the capacity of 1st and 2nd interleave memories 2 and 3. Thus, the order of addresses WA10 is rearranged at random, when the data are written. Then the part 51 sends the generated addresses WA10 to the 1st and 2nd address selectors 6 and 10 at every interval of 18 addresses. A memory switch control part 4 supplies the addresses WA10 to the memory 2 or 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an address generation device,
The interleave device and the deinterleave device are suitable for application to a wireless communication system such as a mobile phone system.

[0002]

2. Description of the Related Art Conventionally, in a radio communication system of this type, an area for providing a communication service is divided into cells of a desired size, and base stations as fixed radio stations are installed in the cells, respectively. A mobile phone as a wireless station is configured to wirelessly communicate with a base station in a cell in which the mobile phone is located, and constructs a so-called cellular system.

At this time, various communication systems have been proposed between the portable telephone and the base station, but CDMA (Code Division Multiple Access) has recently attracted attention.
There is a code division multiple access system called a system. This CD
In the MA system, a unique PN (Pseude random Noise sequence) code composed of a pseudo random number sequence code is assigned to each communication line on the transmitting side, and the primary modulation wave is multiplied by the PN code to obtain an original frequency band. The spread spectrum is spread over a wider band (hereinafter referred to as spread spectrum), and the secondary modulated wave subjected to the spread spectrum processing is transmitted.

[0004] In such a mobile station of a cellular system in the CDMA system, voice data is transmitted at the time of transmission.
After adding a RC (Cyclic Redundancy Check) code, a transmission symbol sequence obtained by performing a convolutional coding process (hereinafter, the process up to this point is called an encoding process) is an interleave processing circuit (hereinafter, called an interleaver). ) Is stored in the internal memory in a predetermined writing order,
By reading in a reading order different from the writing order, the order of each symbol is randomly rearranged.
That is, an interleave process is performed.

In a mobile station, each symbol of a received symbol sequence generated by converting a received signal upon reception into a digital signal is transmitted to a transmitting side by a deinterleave processing circuit (hereinafter referred to as a deinterleaver). By storing the symbols in the internal memory in the same writing order as in the case of the above, and reading them out in a reading order different from the writing order, the order of each symbol is restored (hereinafter, this is called deinterleaving). Then, Viterbi decoding processing is performed, and error detection processing using a CRC code is performed.

Here, in a transmission symbol sequence subjected to convolutional encoding processing at the time of transmission by a mobile station, errors do not always occur randomly (average) in a transmission path but tend to occur in bursts (locally). When a burst-like error occurs as described above, if the error in that portion exceeds the error correction capability, an error that cannot be completely corrected remains.
In order to prevent such a situation from occurring, an interleaving process is performed on a transmission symbol sequence so that errors occurring on a transmission path can be dispersed and an error correction process can be efficiently performed on a receiving side. I have.

[0007]

When the above-described interleaving process is performed, the interleaver 1 converts convolutionally encoded transmission symbol sequence data D16 as input data into 8-bit parallel data as shown in FIG. It is supplied to a first interleave memory 2 and a second interleave memory 3.

At this time, the memory switching control unit 4 outputs the write address W generated by the write address counter 5.
A1 is output only to the first interleave memory 2 via the first address selector 6. Thereby, the first interleave memory 2 writes the transmission symbol sequence data D16 in a predetermined area in units of 8 bits according to the write address WA1.

Here, the write address WA1 is also output to the second address selector 10. At this time, under the control of the memory switching control unit 4, the read address is output from the second address selector 10. Is set in the second address selector 1
From 0, the write address WA1 is not output to the second interleave memory 3.

Next, the memory switching control unit 4 sends the read address RA0 generated by the read address counter 8 of the read address generation unit 7 to the address conversion ROM 9. The address conversion ROM 9 stores a new read address R set so as to rearrange the order of writing at random based on the read address RA0.
A1 and outputs it to only the first interleave memory 2 via the first address selector 6.

Also here, the read address RA1 is the second address.
At this time, the second address selector 10 is set to output the write address WA1 under the control of the memory switching control unit 4 at this time. The read address RA1 is not output from the selector 10 to the second interleave memory 3.

The first interleave memory 2 reads the previously written transmission symbol sequence data D16 in units of 8 bits in accordance with the read address RA1, and outputs the data as an interleaved converted data D2.
Output via 1 At this time, the read address RA1
Are converted by the address conversion ROM 9 into a read address different from that at the time of writing, so that the interleaved conversion data D2 is output.

Further, the memory switching control unit 4 converts the converted data D2 interleaved from the first interleave memory 2.
During the reading of the second address selector 10
To output the write address WA1 to the second interleave memory 3 so that the next transmission symbol sequence data D16 is written in a predetermined area of the second interleave memory 3 in units of 8 bits according to the write address WA1.

When the reading of the conversion data D2 from the first interleave memory 2 is completed, the memory switching control unit 4 switches the second address selector 10 to read the read address RA1 output from the read address generation unit 7. To the second address selector 10
To the second interleave memory 3 via Thereby, the second interleave memory 3 reads out the transmission symbol sequence data D16 written earlier and reads out the address RA
The data is read out in units of 8 bits according to 1, and is output as interleaved converted data D3 via the data selector 11.

At this time, the memory switching controller 4 reads the write address WA1 from the first address selector 6 while reading the interleaved conversion data D3 from the second interleave memory 3, Output to As described above, the memory switching control unit 4
While reading the conversion data D2 from the first interleave memory 2, writing the transmission symbol sequence data D16 to the second interleave memory 3, and reading the conversion data D3 from the second interleave memory 3,
By writing the transmission symbol sequence data D16 in the first interleave memory 2, the input transmission symbol sequence data D16 is efficiently interleaved.

As described above, in the conventional interleaver 1, in order to perform interleaving, the read address generation unit 7
Requires that an address conversion ROM 9 be provided. The mobile station as a whole also needs a deinterleaver (not shown) having the same address translation ROM 9 as the interleaver 1 in addition to the interleaver 1. Therefore, as the mobile station, as the data amount increases and the number of patterns of the write address and the read address when performing the interleave and deinterleave processing increases, the data amount stored in the address conversion ROM 9 increases. There is a problem that the circuit scale becomes large.

In the interleaver 20, as shown in FIG. 17, in which the same reference numerals are given to parts corresponding to those in FIG.
3 is output to the first address selector 6 and the second address selector 10, and the read address RA3 is fed back to the address control circuit 22.

As a result, the address control unit 22 generates a new read address RA3 at a position skipped by a predetermined interval by adding a predetermined value based on the read-back read address RA3. Via the first address selector 6 and the second
, And feeds back to the address control unit 22 again. Also in this case, as a whole mobile station, the interleaver 1 is provided with the read address generation unit 21 including the address control unit 22 and the read address counter 23, and the same is applied to the read address generation unit of the deinterleaver (not shown). Since it is necessary to provide an address control unit and a read address counter, the processing of the address control unit 22 becomes more complicated as the number of patterns of write addresses and read addresses when performing interleave and deinterleave processing increases. There was a problem.

In the interleavers 1 and 20,
Depending on the pattern for performing the interleaving, the array for writing to the first interleave memory 2 and the second interleave memory 3 may not be simply formed in units of 8 bits (1 byte). There was a problem that it could not be used efficiently.

The present invention has been made in consideration of the above points, and has an address generating apparatus, an interleaving apparatus, and a data generating apparatus capable of generating an address for outputting data in a state of being rearranged at random, with a simple configuration. An interleave device is proposed.

[0021]

According to the present invention, in order to solve such a problem, when data is written to or read from predetermined storage means, a predetermined predetermined value is stored in the storage means. A first address data generating means for generating a plurality of first address data at a predetermined address interval, a first address data generating means for generating a plurality of first address data at a predetermined address interval, Second address data generating means for respectively generating the generated second address data, and addition for sequentially generating addresses at predetermined intervals by sequentially adding the second address data to each of the first address data. Means. Thus, even if the number of address patterns for rearranging and outputting the data order at random is large, a predetermined configuration can be achieved with a simple configuration including only the first address data generating means, the second address data generating means, and the adding means. Addresses at intervals can be generated in order.

Further, according to the present invention, in an interleave device for randomly rearranging the order of each symbol of a transmission symbol sequence generated by encoding original data for each frame and outputting the same, the first interleaving device having a predetermined address interval is used. First address data generating means for generating a plurality of pieces of address data, second address data generating means for respectively generating second address data continuous with the first address data at each address interval, and An address generating device comprising: adding means for sequentially generating addresses at predetermined intervals by sequentially adding second address data to each of the first address data;
By assigning addresses at predetermined intervals to the transmission symbol sequence in order, a control means for randomly rearranging and outputting the order of each symbol in the transmission symbol sequence is provided. Thus, even if the number of address patterns for randomly rearranging and outputting the transmission symbol sequence in the interleaving device is large, only the first address data generation unit, the second address data generation unit, and the addition unit are used. With the simple configuration described above, addresses at predetermined intervals can be sequentially generated.

Further, in the present invention, the transmission data output by rearranging the order of each symbol of the transmission symbol sequence generated by encoding the original data at random for each frame is subjected to a predetermined transmission process. A plurality of first address data having a predetermined address interval are generated in a deinterleave device that receives a transmitted transmission signal and returns the order of each symbol of a received symbol sequence extracted from the received signal to the original arrangement order. First address data generating means for generating, and second address data generating means for respectively generating second address data continuous with the first address data for each address interval;
An address generating device comprising an adding means for sequentially generating addresses at predetermined intervals by sequentially adding second address data to each of the first address data, and converting the addresses at predetermined intervals into a received symbol sequence. By allocating in order, there is provided control means for returning the order of each symbol of the received symbol sequence to the original arrangement order and outputting the same. With this, even if the number of address patterns for rearranging the order of the received symbol sequence at random in the deinterleave device and outputting it is large,
With a simple configuration including only the first address data generating means, the second address data generating means, and the adding means, addresses at predetermined intervals can be sequentially generated.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Overall Configuration of Communication Terminal In FIG. 1, reference numeral 1 denotes a communication terminal as a whole on which an address generation device of the present invention is mounted, and a voice signal S1 picked up by a microphone 2 during a telephone call is transmitted and received. The signal is interface-converted via the interface 3 and sent to the audio codec 4. The audio codec 4 increases the transmission processing speed of the audio signal S1 to 9600 based on the detection result obtained by detecting the line quality, the quality of the audio signal S1, and the amount of information thereof.
One of four types, [bps], 4800 [bps], 2400 [bps], and 1200 [bps] is selected.

The audio codec 4 digitizes the audio signal S 1 having the selected transmission processing speed to generate audio data D 1, and sends it to the channel encoder 6 of the channel code 5. In addition, the voice codec 4 generates speed information data D2 representing the selected transmission processing speed every time the transmission processing speed is selected, and sends it to the controller 7.

The controller 7 generates control data D 3 corresponding to the transmission processing speed indicated by the speed information data D 2 and sends it to the channel encoder 6. The channel encoder 6 performs transmission processing according to the transmission processing speed based on the control data D3, and performs convolutional encoding with the communication control data D4 supplied from the controller 7 added to the audio data D1, and then performs predetermined processing. The conversion data D5 obtained by converting the data into a data format is transmitted to the transmitter 8.

The transmitter 8 is supplied with a frequency control signal S2 for controlling the transmission frequency from the synthesizer 9, modulates the converted data D5 in a predetermined format based on the frequency control signal S2, and obtains the transmission data D6 obtained as a result. Is transmitted to a base station (not shown) at a predetermined wireless transmission rate via the duplexer 10 and the antenna 11.

Also at the base station, transmission processing is performed at a transmission processing speed of 9600 [bps], 4800 [bps], 2400 [bps], or 1200 [bps], similarly to the transmission data D6 described above. The communication terminal 1 receives data transmitted from the base station via the antenna 11 and supplies the received data D7 to the receiver 12 via the duplexer 10 as transmitting data.

The receiver 12 is supplied with a frequency control signal S3 for controlling the reception frequency from the synthesizer 9,
The demodulated data D8 is generated by demodulating the received data D7 in a predetermined format based on the frequency control signal S3, and is transmitted to the channel decoder 13 of the channel codec 5.

The channel decoder 13 is connected to the controller 7
9600 [bps], 4800 [bps], 2400 which are the same as the transmission processing speed when used in the base station on the transmission side.
The reception processing of the demodulated data D8 is executed at a reception processing speed of either [bps] or 1200 [bps]. In this case, the channel decoder 13 converts the demodulated data D8 into a predetermined format corresponding to the reception processing speed, performs error correction by the Viterbi decoding method, and then decodes the data to generate decoded data.

In addition, the channel decoder 13 sends to the voice codec 4 voice data D10 corresponding to the voice of the other party in the decoded data obtained by decoding the demodulated data D8. The communication control data D11 of the data is sent to the controller 7.

The voice codec 4 converts the voice data D10 into an analog voice signal S5 based on the control signal S4 input from the controller 7, converts the voice signal D10 into an analog voice signal S5 through the handset 3, and then sends it to the speaker 14. I do. Thus, in the communication terminal 1, a voice call with the other party can be realized by generating a voice from the speaker 14.

The controller 7 generates communication control data D4 to be added to the voice data D1 and decodes the communication control data D11 input from the channel decoder 13 to set, cancel, and maintain a call. Key/
The I / O (In / Out) control of the outing chair play 15 is executed.
In addition, the controller 7 controls a synthesizer 9 that generates a transmission frequency and a reception frequency.

As shown in FIGS. 2 and 3 in which the same reference numerals are given to the parts corresponding to those in FIG. 1, first, at the time of data transmission, the channel encoder 6 outputs the audio codecs 4 to 96.
The audio data D1 having a transmission processing speed of any of 00 [bps], 4800 [bps], 2400 [bps] or 1200 [bps] is CRC.
It is input to the generator 20.

When audio data D1 having a transmission processing speed of 9600 [bps] is input, the CRC generator 20 adds a total of 172 bits by adding communication control data D4 supplied from the controller 7 to the audio data D1. And the following formula based on the generated raw data:

[0037]

(Equation 1)

Using the generator polynomial G1 (X)
A 184-bit data is generated by generating a 12-bit CRC code and adding this to the original data. Thereafter, the CRC generator 20 adds 8-bit tail bits to the 184-bit data to generate 192-bit code-added data D15, and sends this to the convolutional encoder 21.

The CRC generator 20 is 4800 [bp]
s], the communication control data D4 supplied from the controller 7 is added to the audio data D1 to add a total of 80 audio data D1.
In addition to generating the original data of the bit, based on the generated original data,

[0040]

(Equation 2)

An 8-bit CRC code is generated using the generator polynomial G2 (X) expressed by the following formula, and is added to the original data to generate 88-bit data. After this C
The RC generator 20 adds an 8-bit tail bit to the 88-bit data to generate a 96-bit code-added data D.
15 is sent to the convolutional encoder 21.

Further, the CRC generator 20 has a capacity of 2400 [b
ps], the communication control data D4 supplied from the controller 7 is added to the audio data D1 to add a total of 40 audio data D1.
The original bit data is generated, and an 8-bit tail bit of "0" is added to the generated original data.
The 48-bit code additional data D15 is generated and sent to the convolutional encoder 21.

Further, the CRC generator 20 operates at 1200 [b
ps], the communication control data D4 supplied from the controller 7 is added to the audio data D1 so that a total of 16
The original bit data is generated, and an 8-bit tail bit of "0" is added to the generated original data.
The 24-bit code additional data D15 is generated and sent to the convolutional encoder 21.

The convolutional encoder 21 converts the code addition data D15 generated by the CRC generator 20 for each transmission processing speed into a preset constraint length k (set to "9" in this embodiment) and The convolutional coding is performed based on the coding rate R (set to “１ ／” in this embodiment), and the resulting transmission symbol sequence data D16 is sent to the interleaver 22.

By the way, the convolutional encoder 21 has 9600 [bps].
192 bits of code-added data D consisting of a transmission processing speed of
15 is input, the convolutional coding is performed on the basis of the 192 bit code additional data D15.
When 576-bit transmission symbol sequence data D16 is generated and 96-bit code addition data D15 having a transmission processing speed of 4800 [bps] is input, convolution is performed based on the 96-bit code addition data D15. By encoding, 288 bits of transmission symbol sequence data D
16 is generated.

The convolutional encoder 21 has a 48-bit code addition data D15 having a transmission processing speed of 2400 [bps].
Is input, convolutional coding is performed based on the 48-bit code additional data D15 to generate 144-bit transmission symbol sequence data D16, and a 24-bit transmission processing speed of 1200 [bps]. When the sign-added data D15 is input, convolutional coding is performed on the basis of the 24-bit sign-added data D15 to generate 72-bit transmission symbol sequence data D16.

In the interleaver 22, the number of data repetitions is set in advance for each transmission processing speed.
When the transmission symbol sequence data D16 of 576 bits generated according to the transmission processing speed of ps] is input, the data is stored in an interleave memory (not shown) provided internally without repeating the data. After sequentially writing data in 8-bit units according to a predetermined write address, an interleave process is performed by sequentially reading data in 8-bit units according to a predetermined read address. The resulting 576-bit converted data D5 is 28800 [bps]. ] (576 bits / 20 [msec]) to the transmitter 8.

When the interleaver 22 receives the 288-bit transmission symbol sequence data D16 generated according to the transmission processing speed of 4800 [bps], the interleaver 22 repeats the data one bit at a time and uses it once ( That is, by repeating the same data two by two), 576-bit repeated data is generated, and the 576-bit repeated data is sequentially written in an internal interleave memory in 8-bit units according to a predetermined write address. , An interleave process is performed by sequentially reading data in units of 8 bits according to a predetermined read address, and the result is obtained.
Conversion data D5 of 576 bits is converted to 28800 [bps] (576 bits).
/ 20 [msec]) to the transmitter 8 at the line transmission speed.

When the 144-bit transmission symbol sequence data D16 generated according to the transmission processing speed of 2400 [bps] is input, the interleaver 22 sequentially uses the data three times, one bit at a time. That is, by repeating the same data four by four), repeated data of 576 bits is generated, and the repeated data of 576 bits is sequentially written in an internal interleave memory in units of 8 bits according to a predetermined write address. , An interleave process is performed by sequentially reading data in units of 8 bits according to a predetermined read address, and the result is obtained.
Conversion data D5 of 576 bits is converted to 28800 [bps] (576 bits).
/ 20 [msec]) to the transmitter 8 at the line transmission speed.

Further, when the 72-bit transmission symbol sequence data D16 generated according to the transmission processing speed of 1200 [bps] is input, the interleaver 22 sequentially uses the data seven times, one bit at a time. That is, by repeating the same data eight by two), 576-bit repetition data is generated, and the 576-bit repetition data is sequentially written in an internal interleave memory in 8-bit units according to a predetermined write address. , An interleave process is performed by sequentially reading data in units of 8 bits according to a predetermined read address, and the result is obtained.
Conversion data D5 of 576 bits is converted to 28800 [bps] (576 bits).
/ 20 [msec]) to the transmitter 8 at the line transmission speed.

As shown in FIG. 4, the interleaver 22 generates three types of data (288 bits, 144 bits) corresponding to the transmission processing speeds of 4800 [bps], 2400 [bps] and 1200 [bps]. By performing the above-described data repetition processing and interleave processing on the transmission symbol sequence data D16 consisting of 72 bits and 72 bits, 9600 [b]
ps], the conversion data D5 having the same bit length (576 bits) as the interleaved transmission symbol sequence data D16 generated according to the transmission processing speed of ps] is generated, and this is converted to a line transmission speed of 28800 [bps]. To the transmitter 8.

On the other hand, in FIG. 2 and FIG. 5 in which the same reference numerals are given to the parts corresponding to FIG. 1, at the time of data reception, the channel decoder 13 sends the demodulated data D8 supplied from the receiver 12 input.

The deinterleaver 25 sequentially stores the demodulated data D8 in an internal deinterleave memory (not shown) by a length of 576 bits (for one cycle at the time of transmission), and 576 demodulated data D8 from the deinterleave memory. Read out for each bit length. Here, when reading out the demodulated data D8 from the deinterleave memory, 9600 [bps], 4800 [bps], and 24 according to the transmission processing speed used on the transmission side.
Reading is performed at a reception processing speed of either 00 [bps] or 1200 [bps].

In addition, the deinterleaver 25 calculates
The bit demodulation data D8 is rearranged in the procedure completely opposite to that when rearranged on the transmission side according to the respective reception processing speeds, thereby returning the original rearrangement order (hereinafter, referred to as the following).
This is called deinterleaving), and the resulting 576
The bit length soft decision data (hereinafter referred to as first soft decision data) D 28 is sent to the data addition processor 26.

The data addition processor 26 generates soft-decision data (hereinafter referred to as soft-decision data) consisting of a predetermined number of bits before each one-bit data is repeated a predetermined number of times for each reception processing speed based on the first soft-decision data D28. D29) (referred to as second soft decision data). Accordingly, when the first soft decision data D28 is input at the reception processing speed of 9600 [bps], the data addition processor 26 performs the first processing.
Is not subjected to data processing because repetition processing has not been performed, and the second soft decision data D
29 and transmitted to the Viterbi decoder 27.

The data addition processor 26 outputs 4800 [bps].
When the first soft decision data D28 is input at the reception processing speed of, the second soft decision data D29 of 288 bits is generated by performing data addition processing based on the first soft decision data D28. To the Viterbi decoder 27. When the first soft decision data D28 is input at a reception processing speed of 2400 [bps], the data addition processor 26
By performing data addition processing based on the first soft decision data D28, the second soft decision data D2 of 144 bits is obtained.
9 and sends it to the Viterbi decoder 27.

Further, the data addition processor 26 outputs 1200 [bp]
s], the second soft decision data D29 of 72 bits is generated by performing data addition processing based on the first soft decision data D28. Are sent to the Viterbi decoder 27.

The Viterbi decoder 27 applies a Viterbi algorithm to the second soft-decision data D29 input at each reception processing speed, using a constraint length k of "9" and a coding rate R of "9". By performing the maximum likelihood decoding process set to "1/3", decoded data D30 (tail bits of 8 bits are removed) is generated and sent to the error detector 29.

Here, when the second soft decision data D29 is input at a reception processing speed of 9600 [bps], the Viterbi decoder 27 generates 184-bit decoded data D30 and outputs 4800.
When the second soft decision data D29 is input at the reception processing speed of [bps], 88-bit decoded data D30 is generated, and the second soft decision data D is received at the reception processing speed of 2400 [bps].
When 29 is input, 40-bit decoded data D30
Is generated, and when the second soft decision data D29 is input at a reception processing speed of 1200 [bps], 16-bit decoded data D30 is generated.

When the decoded data D30 corresponding to the reception processing speed of 9600 [bps] is input, the error detector 29 converts the decoded data D30 into the generator polynomial G1 shown in the equation (1).
After detecting an error using (X), the 12-bit data of the portion to which the CRC code is estimated to be added is removed from the decoded data D30, and the resulting 172-bit audio data D10 is output to the audio codec 4. Send out.

When the decoded data D30 corresponding to the reception processing speed of 4800 [bps] is input, the error detector 29 converts the decoded data D30 using the generator polynomial G2 (X) shown in the equation (2). After detecting an error, the decoded data D30
Of the portion estimated to have a CRC code added from
The bit data is removed, and the resulting 80-bit audio data D10 is sent to the audio codec 4.

Further, when the decoded data D30 corresponding to the reception processing speed of 2400 [bps] is input, the error detector 29 does not perform the data processing because the decoded data D30 does not have the CRC code added thereto. The bit decoded data D30 is transmitted to the audio codec 4 as audio data D10. Further, when the decoded data D30 corresponding to the reception processing speed of 1200 [bps] is input, the error detector 29 does not perform the data processing because the decoded data D30 is not added with the CRC code. The data is transmitted to the audio codec 4 as data D10.

(2) Configuration of Interleaver Next, in the interleaver 22 of the channel encoder 6 on the transmission side, as shown in FIG. An address generation unit 51 and a read address generation unit 52,
Transmission symbol sequence data D1 subjected to convolutional encoding processing
6 is serially input to the serial / parallel converter 53 in serial.

When the transmission symbol sequence data D16 has accumulated for 8 bits, the serial / parallel converter 53 uses the 3-bit clock signal S10 supplied from the write address generation unit 51 as a trigger to transmit the transmission symbol sequence data D16.
16 is output to the first interleave memories 2 and 3 in units of 8 bits.

The write address generator 51 sends a 7-bit write address WA10 to the first address selector 6 and the second address selector 10. The memory switching control unit 4 controls switching of the outputs of the first address selector 6 and the second address selector 10, and stores the write address WA10 in the first interleave memory via the first address selector 6. Output to 2 only.

Here, the write address WA10 is the second
However, at this time, the second address selector 10 is switched to output a read address under the control of the memory switching control unit 4, so that the second address selector 10 outputs the read address. The write address WA10 is not output from the address selector 10 to the second interleave memory 3.

Thus, the first interleave memory 2
Writes the transmission symbol sequence data D16 in a random write order in units of 8 bits in accordance with the write address WA10.

The read address generator 52 sends a 7-bit read address RA10 to the first address selector 6 and the second address selector 10. The memory switching control unit 4 switches the output of the first address selector 6 and the output of the second address selector 10 to output the read address RA10 only to the first interleave memory 2 via the first address selector 6. .

Here, the read address RA10 is also output to the second address selector 10. At this time, the write address WA10 is output from the second address selector 10 under the control of the memory switching controller 4. As a result, the read address RA10 is not output from the second address selector 10 to the second interleave memory 3.

Thus, the first interleave memory 2
Reads out the transmission symbol sequence data D16 sequentially in units of 8 bits in accordance with a read address RA10 in a different order from the write address WA10, and sends this to the data selector 11 as read data D11.
The data selector 11 specifies the bit position of the 8-bit read data D11 based on the 3-bit address data S22 supplied from the read address generator 51, thereby converting the serially interleaved converted data D5 one by one. Is output.

The memory switching control section 4 outputs the write address WA10 from the second address selector 10 to the second interleave memory 3 while reading the conversion data D11 from the first interleave memory 2. , The transmission symbol sequence data D16 to be transmitted next is sequentially written into the second interleave memory 3 in a random writing order in units of 8 bits in accordance with the write address WA10.

When the reading of the conversion data D11 from the first interleave memory 2 is completed, the memory switching control unit 4 switches the second address selector 10 to read the read address RA10 output from the read address generation unit 52. To the second interleave memory 3 via the second address selector 10. As a result, the second interleave memory 3 reads out the transmission symbol sequence data D16 written in advance in units of 8 bits in accordance with the read address RA10, and sends this to the data selector 11 as read data D12.

The data selector 11 receives the 3-bit address data S supplied from the read address generator 51.
By specifying the bit position of the 8-bit read data D12 based on the P.22, the converted data D5 serially interleaved one bit at a time is output.

At this time, the memory switching control section 4 outputs the write address WA10 from the first address selector 6 to the first interleave memory 2 while the read data D12 is being read from the second interleave memory 3. . As described above, the memory switching control unit 4 writes the transmission symbol sequence data D16 to the second interleave memory 3 while reading the read data D11 from the first interleave memory 2, and reads the data from the second interleave memory 3. By writing the transmission symbol sequence data D16 to the first interleave memory 2 while reading the read data D12, the input transmission symbol sequence data D16 is efficiently interleaved.

(2-1) Configuration of Write Address Generation Unit In the write address generation unit 51, the write address WA10 is provided at predetermined address intervals according to the memory capacities of the first interleave memory 2 and the second interleave memory 3. Is generated, whereby the order is randomly rearranged when writing data.

The write address generation unit 51 performs the first
If the interleave memory 2 and the second interleave memory 3 are composed of 8-bit memories capable of storing a maximum of 576 bits of data at a transmission processing speed of 9600 [bps], the write address WA10 is written four times at intervals of 18 addresses. Are generated one by one. Here the first
The interleave memory 2 and the second interleave memory 3 are designed to write data in units of 8 bits (1 byte) per address, and store 576 bits of data with a total of 72 addresses.

Accordingly, as shown in FIG. 7, the write address generator 51 generates the addresses 18, 36, and 54 in order from the address 0 expressed in decimal notation, and then generates the addresses 0, 18, and 36. And 54-1
The address 1, the address 19, the address 37, and the address 55 at the position shifted line by line are generated, and then the address 2, the address 20, the address 38, and the address at the position shifted by two lines from the addresses 0, 18, 36, and 54. 5
6 is generated, and finally, addresses 17, 35, 53, and 71 shifted by 17 lines from the addresses 0, 18, 36, and 54 are generated, so that a total of 72 types are provided at intervals of 18 addresses. A write address WA10 is generated.

Here, the numbers “001” to “576” written in the map of the memory correspond to the write addresses WA.
10 shows a writing order of data written in accordance with No. 10.

In practice, the write address generation unit 51 uses the 3-bit counter 61 to control the serial number 0 to 7 at a timing synchronized with the timing at which the transmission symbol series data D16 is serially input one bit at a time to the serial / parallel converter 53. It is made to count up to the value.

Accordingly, the 3-bit counter 61 sends a counter output S10 to the serial / parallel converter 53 and supplies a carry output (so-called carry signal) S11 to the 2-bit counter 62.

Thus, the serial / parallel converter 53
Is “1, 1, 1” where the value of the counter output S10 represents 7.
, The counter output S10 is used as a trigger to transmit the transmission symbol sequence data D16 in units of 8 bits in the first interleave memory 2 and the second interleave memory 3.
Output to

The 2-bit counter 62 counts from 0 to 3 each time the carry output S11 is given from the 3-bit counter 61, and 2-bit address data S12 ("0, 0" to "1, 1") to the multiplier 63. The two-bit counter 62
Every time the count value 3 is counted, the carry output S14 is set to 5
The data is supplied to a bit counter 65.

The multiplier 63 multiplies the 2-bit address data S12 supplied from the 2-bit counter 62 by 12 times the hexadecimal (hex) representation, ie, 18 times the decimal representation, thereby producing 6 bits at every 18 address intervals.
The bit address data S13 is generated and sent to the 6-bit adder 64.

In this case, the multiplier 63 does not actually perform the multiplication processing, but (a) of the two-bit data S12.
₁ , a ₂ ) can be converted to 6-bit address data S13 by bit-shifting to “a ₁ , a ₂ , 0, a ₁ , a ₂ , 0”. Has formed.

Thus, “0, 0” representing the count value 0
The two-bit address data S12 of "0, 0,
6-bit address data S1 consisting of "0, 0, 0, 0"
The address is converted to "3," and similarly, "0, 1" representing the count value 1 is converted to 6-bit address data S13 consisting of "0, 1, 0, 0, 1, 0" to represent the count value 2. “1,0” is “1,0,0,1,0,0”
The address is converted into 6-bit address data S13, and “1, 1” representing the count value 3 is changed to “1, 1, 0,
The address is converted into 6-bit address data S13 of "1, 1, 0".

That is, the multiplier 63 generates an address 0 based on the count value 0 supplied from the two-bit counter 62, generates an address 18 based on the count value 1, and generates an address 36 based on the count value 2. Generate
The address 54 is generated based on the count value 3. Here, the addresses 0, 18, 36, and 54 are address values in decimal notation, and in binary notation, "0, 0,
0, 0, 0, 0 "," 0, 1, 0, 0, 1, 0 ",
“1, 0, 0, 1, 0, 0” and “1, 1, 0, 1,
1, 0 ".

The 5-bit counter 65 sets 0 to 17 every time the carry output S14 is supplied from the 2-bit counter 62.
And the 5-bit address data S15 (“0, 0, 0, 0, 0” to
"1, 0, 0, 0, 1") to the 6-bit adder 64.

The 6-bit adder 64 generates a 7-bit write address WA10 by adding each of the 5-bit address data S15 representing the count value 0 to 17 to the 6-bit address data S13. ing.

In practice, the 6-bit adder 64 outputs "0, 0,
6-bit address data S1 consisting of "0, 0, 0, 0"
The count value output from the 5-bit counter 65 is 0 to 3
Address data S15 of “0, 0, 0, 0, 0” representing
Are added to obtain “0, 0,
0, 0, 0, 0, 0 ”write address WA10 (7
Bit).

Subsequently, the 6-bit adder 64 outputs "0, 1,.
6-bit address data S1 consisting of "0, 0, 1, 0"
The count value output from the 5-bit counter 65 is 0 to 3
Address data S15 of “0, 0, 0, 0, 0” representing
Are added to obtain “0, 0,
1, 0, 0, 1, 0 ”write address WA10 (7
Bit).

Subsequently, the 6-bit adder 64 outputs "1,
The address data S13 of "0, 0, 0, 0, 0" representing the count value 0 output from the 5-bit counter 65 is added to the 6-bit address data S13 of "0, 0, 1, 0, 0".
By adding “15,” “0,
Write address WA10 of "1, 0, 0, 1, 0, 0"
(7 bits) is generated, and “0, 0, 0” representing the count value 0 output from the 5-bit counter 65 is added to the 6-bit address data S13 of “1, 1, 0, 1, 1, 0”.
By adding the address data S15 of “0, 0, 0”, “0, 1, 1, 0, 1, 1,.
A write address WA10 (7 bits) of "0" is generated.

Similarly, when the count value 1 of the 5-bit counter 65 is input based on the carry output S14 from the 2-bit counter 62, the 6-bit adder 64 outputs "0, 0".
In the 6-bit address data S13 consisting of “0, 0, 0, 0, 0”, “0, 0, 0, 0,
By adding the address data S15 of “1”, “0,
0, 0, 0, 0, 0, 1 "write address WA10
Generate

Subsequently, the 6-bit adder 64 outputs "0, 1,.
6-bit address data S1 consisting of "0, 0, 1, 0"
Count value 1 output from 5-bit counter 65 to 3
Address data S15 of “0, 0, 0, 0, 1”
Are added to obtain “0, 0, 1, 0, 0, 1, 1” representing the address 19 shifted by one row from the address 18.
The write address WA10 is generated.

Subsequently, the 6-bit adder 64 outputs "1,
The address data S13 of "0, 0, 0, 0, 1" representing the count value 1 output from the 5-bit counter 65 is added to the 6-bit address data S13 of "0, 0, 1, 0, 0".
By adding 15, “0,1,0,0,1,0,0” representing the address 37 shifted by one row from the address 36.
A write address WA10 of “1, 1” is generated.
0, 1, 1, 0 "6-bit address data S1
Count value 1 output from 5-bit counter 65 to 3
Address data S15 of “0, 0, 0, 0, 1”
Are added, “0, 1, 1, 0, 1, 1, 1” representing the address 55 shifted by one row from the address 54
The write address WA10 is generated.

In the same manner, 6-bit adder 64
By adding 5-bit address data S15 representing the count values 2 to 17 to the bit address data S13, respectively, address 2, address 20, address 3
8, an address 56 is generated, and subsequently, an address 3, an address 21, an address 39, and an address 57 are generated, and an address 4, an address 22, an address 40, and an address 58 are generated.
3. The address 71 is sequentially generated as the write address WA10.

Thus, the write address generator 51
Write address WA generated every 18 address intervals
10 is sent to the first address selector 6 and the second address selector 10. The memory switching control unit 4 switches between the first address selector 6 and the second address selector 10 and synchronizes with the timing at which the transmission symbol sequence data D16 is output from the serial / parallel converter 53 in units of 8 bits. The write address WA10 is stored in the first interleave memory 2 or the second interleave memory 3.
Supply.

[0097] Thus the first interleave memory 2 or the second interleave memory 3, a transmission symbol sequence bit b data D16 to the write address WA10 in the row direction for each slave connexion 18 address space ₀ to bit b ₇
("001" to "576") in this order.

(2-2) Configuration of Read Address Generation Unit On the other hand, the read address generation unit 52 uses the same read address RA10 as the write address WA10 in a read order different from that of the write address WA10.
Has been made to generate. 5-bit counter 66
Counts from 0 to 17, sends the count value to the 6-bit adder 67 as 5-bit address data S20, and supplies the carry output S21 to the 3-bit counter 68 when the count value 17 is counted. It has been done.

The 3-bit counter 68 has a carry output S2
The count value is counted from 0 to 7 based on 1 and the count value is output to the data selector 11 as 3-bit address data S22. When the count value 7 is counted, the carry output S23 is supplied to the 2-bit counter 69. It has been done.

The 2-bit counter 69 has a carry output S2
Count from 0 to 3 according to 3 and count the value to 2
It is sent to the multiplier 70 as bit address data S24. The multiplier 70 has a 2-bit address data S
24 are respectively multiplied by 12 times in hexadecimal notation (hex), that is, 18 times in decimal notation, thereby generating 6-bit address data S25 every 18 address intervals,
This is sent to a 6-bit adder 67.

Here, the multiplier 70 does not actually perform the multiplication processing, but substitutes (a ₁ , a ₂ ) of the 2-bit address data S 24 with “a ₁ , a ₂ , 0, a ₁ ,
a ₂ , 0 ", so that the data can be converted into 6-bit address data S25, forming a so-called shift operation unit.

The 6-bit adder 67 adds the 5-bit address data S20 and the 6-bit address data S25 to generate a 7-bit read address RA10 representing addresses 0 to 71 in order.
This is sent to the first address selector 6 and the second address selector 10.

In practice, the read address generation unit 52
First, 3-bit address data S22 representing a count value of 0 is supplied from a 3-bit counter 68 to the data selector 11, and 5-bit address data S20 representing a count value of 0 to 17 is supplied from a 5-bit counter 66 to a 6-bit adder 67. Supply.

In this case, since the carry output S23 is not supplied from the 3-bit counter 68, the 2-bit counter 69 sends the 2-bit address data S24 representing the count value 0 to the multiplier 70. The multiplier 70 converts the 2-bit address data S24 representing the count value 0 into a value 12 times hexadecimal (hex), that is, 10 times.
By multiplying by 18 times the base number, "0, 0, 0, 0,
The address data S25 of "0,0" is added to the 6-bit adder 67.
To supply.

The 6-bit adder 67 has a count value of 0 to 1
7, 5-bit address data S20 and "0, 0,
By adding the address data S25 of "0, 0, 0, 0" to each other, a 7-bit read address RA10 representing addresses 0 to 17 is generated, and these are read out by the first address selector 6 and the second address. It is sent to the selector 10.

The read address RA1 sent to the first address selector 6 and the second address selector 10
0 indicates the first interleave memory 2 or the second interleave memory 3 according to the switching control of the memory switching controller 4.
, The data from addresses 0 to 17 are sequentially read and output to the data selector 11. At this time, the data selector 11 is supplied with 3-bit address data S22 indicating the position of the bit b ₀ (count value 0) in the row direction from the 3-bit counter 68, and thus the data selector 11 outputs Only the bit data located at the position b ₀ is set to “00”.
"1", "033", "065" ... "545" in this order.

Subsequently, the read address generation unit 52
The bit counter 68 sends 3-bit address data S22 representing the count value 1 to the data selector 11 based on the carry output S21. Even in this case, since the 3-bit counter 68 does not output the carry output S23,
The count value of the bit counter 69 is not incremented, and accordingly, the 6-bit address data S25 output from the multiplier 70 is "0, 0, 0, 0, 0,
0 ".

The 6-bit adder 67 receives the 5-bit address data S20 representing the count values 0 to 17 from the 5-bit counter 66, and outputs "0, 0, 0, 0, 0, 0" from the multiplier 70. The address data S25 is input and added to each other, thereby obtaining a 7-bit read address R representing addresses 0 to 17 in the same manner as described above.
A10 is generated and sent to the first address selector 6 and the second address selector 10.

The read address RA1 sent to the first address selector 6 and the second address selector 10
0 indicates the first interleave memory 2 or the second interleave memory 3 according to the switching control of the memory switching controller 4.
, The data from addresses 0 to 17 are sequentially read and output to the data selector 11. At this time, the data selector 11 is supplied with 3-bit address data S22 representing the position of the bit b ₁ (count value 1) in the row direction from the 3-bit counter 68, so that the bit data only "00 located at position b ₁
2 ”,“ 034 ”,“ 066 ”...“ 546 ”are output in this order.

As described above, the read address generation unit 52
Until the 3-bit counter 68 supplies the carry output S23 to the 2-bit counter 69, the 7-bit read address RA representing the addresses 0 to 17 is the same as before.
10 is generated eight times (b _{0 to} b ₇ ). Every time the read address RA 10 is generated, the count value is incremented from the 3-bit counter 68 and output to the data selector 11. Thus, the data selector 11 determines the bit positions b _{0 to} b ₇ of the data of the addresses ₀ to ₁₇ based on the 3-bit address data S22 supplied from the 3-bit counter 68.
The bit data for each bit position is output in order.

Next, the read address generation unit 52 supplies the carry output S23 to the 2-bit counter 69 by counting the 3-bit counter 68 up to the count value 7, and the 2-bit counter 69 outputs the 2-bit value representing the count value 1. Is output to the multiplier 70.

The multiplier 70 converts the address data S24 of “0, 1” representing the count value 1 into 1 in hexadecimal notation.
By multiplying by 2 times, that is, by 18 times the decimal notation, 6 represented by “0, 1, 0, 0, 1, 0” representing the address 18
It generates bit address data S25 and sends it to a 6-bit adder 67. The 6-bit adder 67 provides 5-bit address data S20 representing the count values 0 to 17.
And address data S25 of “0, 1, 0, 0, 1, 0”
Are added, the addresses 18 to 35 are obtained.
Are generated, and are sent to the first address selector 6 and the second address selector 10, respectively.

At this time, the data selector 11 receives the 3-bit address data S22 representing the position of the bit b ₀ (count value 0) in the row direction from the 3-bit counter 68, and thereby the data of the addresses 18 to 35 are supplied. and it outputs the bit data written to the bit position b ₀ of the "009", in the order of "041" ...... "553".

As described above, the read address generation unit 52
Until the 3-bit counter 68 supplies the carry output S23 to the 2-bit counter 69, the addresses 18 to 35
A 7-bit read address RA10 representing the read address RA1 is generated eight times.
Each time 0 is generated, the count value is incremented from the 3-bit counter 68 and output to the data selector 11. Thus, the data selector 11, 3 bits data for each bit position in the bit position b ₀ ~b ₇ among the data of the address 18 to 35 based on the address data S22 in 3 bits supplied from the bit counter 68 sequentially The output has been made.

The read address generator 52 generates the read addresses RA10 representing the addresses 36 to 53 and the addresses 54 to 71 as described above, and sends them to the first address selector 6 and the second address selector 10. together, and it sends the address data S22 in three bits representing the bit positions b ₀ ~b ₇ to the data selector 11.

The data selector 11 has addresses 36 to 5
3 sequentially outputs bit data for each bit position at bit positions b _{0 to} b ₇ , and finally, for data at addresses 54 to 71, bit data for each bit position at bit positions b _{0 to} b ₇ . The data is output in order. As a result, the data selector 11
The interleaved conversion data D5 can be serially output one bit at a time.

As shown in FIG. 8, the conversion data D5 has write positions 1, 33, 65,.
4, 66,... 546, 3, 35, 67,.
... 32, 64, 96,... 576 are output in this order.

When the first interleave memory 2 and the second interleave memory 3 store data of a maximum of 288 bits at a transmission processing speed of 4800 [bps], the write address generation unit 51 sets the write address WA10 to 18 addresses. It is generated twice at intervals.

Accordingly, the write address generator 51 generates an address 18 next to the address 0 expressed in decimal notation as shown in FIG.
, An address 1 and an address 19 at positions shifted by one row from each other, and then an address 2 and an address 20 at a position shifted by two rows from the addresses 0 and 18... By generating the address 17 and the address 35 at positions shifted by 17 rows from each other, a total of 36 types of write addresses WA10 are generated at intervals of 18 addresses.

In this case, the write address generator 51
The 2-bit counter 62 counts from 0 to 1 and counts the count value as 2-bit address data S12 (“0,
0 "and" 0, 1 ") to the multiplier 63, and when the count value 1 is incremented, the carry output S1
4 is supplied to a 5-bit counter 65.

At this time, the read address generation unit 5
2 is such that a 2-bit counter 69 counts 0 to 1 and outputs the count value as 2-bit address data S22, thereby generating a 7-bit read address RA10 representing addresses 0 to 35 in order. Has been made.

As a result, the read address generator 52
Is sends out the read address RA10 of 7 bits to a first address selector 6 and a second address selector 10 transmits the address data S22 in three bits representing the bit positions b ₀ ~b ₇ to the data selector 11.

The data selector 11 sequentially outputs bit data for each bit position at the bit positions b _{0 to} b ₇ among the data at the addresses ₀ to ₁₇ read based on the read address RA10, and outputs the next address. 18 ~
And to output sequentially bit data for each bit position in the bit position b ₀ ~b ₇ among the data of 35. As a result, the data selector 11 can output the interleaved converted data D5 serially one bit at a time.

At this time, the converted data D5 is such that the same data is output twice each time by the data selector 11 being controlled by the memory switching controller 4. As a result, as shown in FIG. 10, the converted data D5 repeatedly outputs the data of 1, 17, 33, 49,... 273 in the first row twice, and outputs 2, 18, 34,.
The data of 74 are repeatedly output twice, and the data of 16, 32, 48... 288 in the 31st row are repeatedly output twice.

Further, when the first interleave memory 2 and the second interleave memory 3 store a maximum of 144 bits of data at a transmission processing speed of 2400 [bps], the write address generation unit 51 sets the address as shown in FIG. The write address WA10 is generated in order from address 0 to address 17.

In this case, the write address generator 51
The 2-bit counter 62 counts 0, sends the count value as a 2-bit address data S12 ("0, 0") to the multiplier 63, and outputs the carry output S14 to the 5-bit counter every time the count value 0 is incremented. 65
To be supplied.

At this time, the read address generation unit 5
2 indicates the addresses 0 to 17 in order by the 2-bit counter 69 counting 0 and outputting the count value as 2-bit address data S24.
A bit read address RA10 is generated.

Thus, the read address generator 52
Is sends out the read address RA10 of 7 bits to a first address selector 6 and a second address selector 10 transmits the address data S22 in three bits representing the bit positions b ₀ ~b ₇ to the data selector 11.

The data selector 11 sequentially outputs the bit data for each bit position at the bit positions b _{0 to} b ₇ among the data at the addresses ₀ to ₁₇ read based on the read address RA10. I have. As a result, the data selector 11 can output the interleaved converted data D5 serially one bit at a time.

At this time, the converted data D5 is such that the same data is output four times by controlling the data selector 11 by the memory switching controller 4. As a result, as shown in FIG. 12, the converted data D5 repeatedly outputs the data of 1, 9, 17,... 137 in the first row four times, and the data of 2, 10, 18,. It is repeatedly output four times, and ...
6, 24... 144 are repeatedly output four times.

Further, when the first interleave memory 2 and the second interleave memory 3 store a maximum of 72 bits of data at a transmission processing speed of 1200 [bps], the write address generation unit 51 performs the operation as shown in FIG. The write address WA10 is generated in order from address 0 to address 17.

In this case, the write address generator 51
The 3-bit counter 61 counts from 0 to 3 and outputs its counter output S10. When the count value 3 has been counted, the carry output S11 is supplied to the 2-bit counter 62. Further, the write address generation unit 51 generates a 2-bit address data S12 representing the count value 0 by the 2-bit counter 62 counting 0.
(“0, 0”) is sent to the multiplier 63 and the count value 0
Each time is incremented, the carry output S14 is supplied to the 5-bit counter 65.

At this time, the read address generation unit 5
In the case of 2, the 3-bit counter 68 counts 0 to 3 and outputs the count value as address data S22. When the count value 3 is counted, the carry output S23 is set to 2
The data is supplied to a bit counter 69. The read address generation unit 52 includes a 2-bit counter 6
9 counts 0 and outputs the count value as address data S24, thereby generating a 7-bit read address RA10 representing addresses 0 to 17 in order.

As a result, the read address generator 52
Is sends out the read address RA10 of 7 bits to a first address selector 6 and a second address selector 10 transmits the address data S22 in three bits representing the bit positions b ₀ ~b ₃ to the data selector 11.

The data selector 11 sequentially outputs the bit data for each bit position at the bit positions b _{0 to} b ₃ among the data at the addresses ₀ to 17 read based on the read address RA10. I have. As a result, the data selector 11 can output the interleaved converted data D5 serially one bit at a time.

At this time, the converted data D5 is such that the same data is output eight times by the data selector 11 being controlled by the memory switching controller 4. As a result, as shown in FIG. 14, the converted data D5 repeatedly outputs the data of 1, 5, 9,... 69 in the first row eight times, and the data of 2, 6, 10,. 8
... Are output repeatedly 25 times.
.. 72 are repeatedly output eight times.

(3) Operation and Effect In the above configuration, the write address generation unit 51
The address data S12 output from the bit counter 62 is multiplied by the multiplier 63 by a predetermined number, so that the address data S1 having a predetermined address interval is obtained.
3 and a 5-bit counter 65 generates address data S15 continuous with the address data S13 at predetermined address intervals.
By sequentially adding the address data S15 to each of the address data S13 by the bit adder 64, the number of patterns is such that all data can be stored in the first interleave memory 2 and the second interleave memory 3. The write addresses WA10 can be sequentially generated at predetermined intervals.

Therefore, the write address generator 51 generates a 72-bit write address WA10 corresponding to the data capacity to be stored in the first interleave memory 2 and the second interleave memory 3, and generates a 2-bit counter 62, It can be formed with a simple configuration including the multiplier 63, the 5-bit counter 65, and the adder 64, and can be formed by using the address conversion ROM 9 (FIG. 16) or using the address control unit 22 (FIG. 17) as in the related art. In addition, the generation of addresses at predetermined intervals does not require an increase in circuit size or the need for complicated processing.

At this time, the multiplier 63 in the first address generator does not actually perform the multiplication processing, but performs the multiplication processing only by performing a bit shift based on the address data S12 output from the two-bit counter 62. You get the same result as what you did. In this way, the multiplier 63 need only actually constitute a shift operation unit, and thus can have a simpler configuration.

In the read address generating section 52, the same connection state as that of the write address generating section 51 can be obtained by changing the connection state by the same 5-bit counter 66, 2-bit counter 69, multiplier 70 and adder 67. With such a configuration, the same read address RA10 as the write address WA10 can be generated in a different read order from the write address WA10.

According to the above configuration, the write address generator 51 generates a plurality of address data S13 having a predetermined address interval by the 2-bit counter 62 and the multiplier 63, and generates the predetermined address data by the 5-bit counter 65. A simplified address data S15 is generated for each address data S13 at each address interval, and the address data S13 and the address data S15 are sequentially added by the 6-bit adder 64, respectively. With a simple configuration and simple processing, the write addresses WA10 can be sequentially generated at predetermined intervals.

(4) Other Embodiments In the above embodiment, the write address generation unit 52 generates the write address WA10 at intervals of 18 addresses, and the read address generation unit 52 sets the read address RA10 to the address 0. In the present invention, the write addresses WA10 are sequentially generated from addresses 0 to 71, and the read addresses RA10 are arranged at intervals of 18 addresses. They may be generated in a changed order.

In the above embodiment, the case has been described in which the address generating device of the present invention is used for the interleaver 22 of the channel encoder 6 on the transmitting side. However, the present invention is not limited to this. The deinterleaver 25 of the channel decoder 13 may use the address generation device of the present invention. in this case,
It is assumed that the write address and the read address are generated such that the rearranged order is restored in the interleaver 22 on the transmission side.

Further, in the above-described embodiment, the interleaver 22 as the interleaver is provided with the write address generator 51 as the address generator, the memory switching controller 4 as the control means, the first address selector 6, and the first address selector 6. Although the description has been made of the case where the configuration is made up of the two address selectors 10, the first interleave memory 2, and the second interleave memory 3, the present invention is not limited to this, and has the same configuration as the write address generation unit 51. May be constituted by an address generation device comprising a read address generation section and a control means, or may be similarly constituted in a deinterleave device.

Further, in the above-described embodiment, a case has been described in which transmission symbol sequence data D16 is output in 8-bit units via serial / parallel converter 53 and stored in interleave memories 6 and 10. The present invention is not limited to this, and may be stored in units of a predetermined number of bits according to the configuration of the interleave memories 6 and 10.

Further, in the above-described embodiment, the 2-bit counter 62 as the first counter is configured as the read address generation unit 52 as the address generation device.
First address generating means, comprising:
A case has been described in which the second address generating means composed of a bit counter and the adding means composed of the 6-bit adder 64 are provided. However, the present invention is not limited to this. As one configuration of the address generating means, a counter means for generating 6-bit address data, and a specific address value at a predetermined interval added to the 6-bit address data to generate and output first address data. An adder and a memory for temporarily storing the first address data, and sequentially adding specific address values to the first address data stored in the memory to generate addresses at predetermined intervals. Alternatively, the first address generating means may be formed by other various configurations.

Further, in the above-described embodiment, the two-bit address data S12 is used as the multiplier 63 by 12 times hexadecimal notation, that is, 18 bits in decimal notation.
A case has been described in which the address data S13 of 6 bits are generated at intervals of 18 addresses by multiplication. However, the present invention is not limited to this, and the present invention is not limited to this. May be generated.
Further, using other various multiples that cannot be bit-shifted, 6-bit address data S13 at predetermined address intervals is used.
May be generated.

[0148]

As described above, according to the present invention, there is provided an address generation apparatus for generating addresses in a predetermined order when writing data to predetermined storage means or reading data from storage means. First address data generating means for generating a plurality of first address data having a predetermined address interval, and a second address representing a position sequentially shifted by one line with respect to the first address data at each address interval By providing second address data generating means for respectively generating data, and adding means for sequentially generating addresses at predetermined intervals by adding the first address data and the second address data, Even if the number of address patterns for rearranging and outputting the data order at random is large, the first address The address of the jump predetermined intervals may be generated sequentially with a simple configuration in which only the adding means data generating means and the second address data generating means.

Further, according to the present invention, in an interleave apparatus for randomly rearranging the order of each symbol of a transmission symbol sequence generated by encoding original data for each frame and outputting the resultant data, the interleaving apparatus having a predetermined address interval is used. 1
A first address data generating means for generating a plurality of address data, and a second address data indicating a position sequentially shifted by one line with respect to the first address data at each address interval.
Address data generating means for generating the address data of each of the first and second address data, and adding means for sequentially generating addresses at predetermined intervals by adding the first address data and the second address data. By providing a generating device and control means for randomly rearranging and outputting the order of each symbol of the transmission symbol sequence by assigning addresses at predetermined intervals to the transmission symbol sequence in order, the order of the transmission symbol sequence is Even if the number of address patterns to be rearranged and output at random is large, addresses arranged at predetermined intervals can be sequentially arranged with a simple configuration of only the first address data generating means, the second address data generating means and the adding means. Can be generated.

Further, according to the present invention, the transmission data output by rearranging the order of each symbol of the transmission symbol sequence generated by encoding the original data at random for each frame is subjected to predetermined transmission processing. A deinterleave device that receives the transmitted transmission signal and returns the order of each symbol of the received symbol sequence extracted from the received signal to the original arrangement order. First address data generating means for generating, and second address data generating means for respectively generating second address data representing positions shifted by one line with respect to the first address data at each address interval. , The first address data and the second address data are respectively added, so that An address generating apparatus comprising an adding means for sequentially generating, and a control means for returning the order of each symbol of the received symbol sequence to the original arrangement order by assigning addresses at predetermined intervals to the received symbol sequence in order, and outputting the received symbol sequence. Is provided, even if the number of address patterns for rearranging the order of the received symbol sequence at random and outputting is large, only the first address data generating means, the second address data generating means, and the adding means are required. Addresses at predetermined intervals can be sequentially generated with a simple configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a communication terminal according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a channel code.

FIG. 3 is a block diagram for explaining a flow of a transmission process in a channel code;

FIG. 4 is a schematic diagram for explaining conditions of transmission processing in a channel codec.

FIG. 5 is a block diagram for explaining a flow of a receiving process in a channel code;

FIG. 6 is a block diagram showing a configuration of an interleaver.

FIG. 7 is a schematic diagram showing a map configuration of an interleave memory at 9600 bps.

FIG. 8 is a schematic diagram showing the reading order of converted data at 9600 bps.

FIG. 9 is a schematic diagram showing a map configuration of an interleave memory at 4800 bps.

FIG. 10 is a schematic diagram showing a reading order of converted data at 4800 bps.

FIG. 11 is a schematic diagram showing a map configuration of an interleave memory at 2400 bps.

FIG. 12 is a schematic diagram illustrating a reading order of converted data at 2400 bps.

FIG. 13 is a schematic diagram showing a map configuration of an interleave memory at 1200 bps.

FIG. 14 is a schematic diagram showing a reading order of converted data at 1200 bps.

FIG. 15 is a block diagram showing a configuration of an interleaver according to another embodiment.

FIG. 16 is a block diagram for explaining a conventional interleaving method 1;

FIG. 17 is a block diagram for explaining a conventional interleaving method 2;

[Explanation of symbols]

2 ... first interleave memory, 3 ... second interleave memory, 4 ... memory switching control unit, 6 ... first address selector, 8 ... serial / parallel converter,
10 second address selector, 11 data selector, 51 write address generator, 52 read address generator, 51A first address generator, 61, 68 3-bit counter, 62, 69 ...
2-bit counter, 63, 70 ... Multiplier, 64, 6
7... 6-bit adder, 65, 66... 5-bit counter.

Claims (13)

[Claims] 1. An address generating apparatus for generating addresses in a predetermined order to said storage means when writing data to said storage means or reading said data from said storage means, First address data generating means for generating a plurality of first address data having the following address intervals; and a second address data generating means for respectively generating second address data continuous with the first address data for each of the address intervals. 2 address data generating means, and adding means for sequentially generating the addresses at predetermined intervals by sequentially adding the second address data to each of the first address data. Address generation device. 2. The first address data generating means comprises: a first counter for counting up to a predetermined value; and a predetermined address interval by multiplying a counter output of the first counter by a predetermined value. 2. The address generator according to claim 1, further comprising a multiplier for generating a plurality of first address data. 3. The multiplier according to claim 2, wherein the multiplier is a shift operation circuit that generates first address data having the predetermined address interval by bit-shifting a predetermined bit position of a counter output of the first counter. 3. The address generation device according to claim 2, wherein: 4. An interleave apparatus for randomly rearranging the order of each symbol of a transmission symbol sequence generated by encoding original data for each frame, and outputting the first address data having a predetermined address interval. A plurality of first address data generating means for generating a plurality of first address data, and a second address data generating means for respectively generating second address data continuous with the first address data at each address interval.
An address generating apparatus comprising: address data generating means; and an adding means for sequentially generating addresses at predetermined intervals by sequentially adding the second address data to each of the first address data. An interleave device comprising: control means for randomly arranging and outputting the order of each symbol of the transmission symbol sequence by sequentially assigning addresses at predetermined intervals to the transmission symbol sequence. 5. The control means has a storage means for storing the transmission symbol sequence, writes the transmission symbol sequence in the storage means based on the address at the predetermined interval, and a reading order different from the address. 5. The interleave device according to claim 4, wherein the data is read out by: 6. The control means has a storage means for storing the transmission symbol sequence, writes the transmission symbol sequence in a predetermined writing order in the storage means, and stores the transmission symbol sequence in addresses at the predetermined intervals. 5. The interleaving device according to claim 4, wherein the reading is performed based on the following. 7. The first address data generating means comprises: a first counter for counting up to a predetermined value; and a predetermined address interval by multiplying a counter output of the first counter by a predetermined value. 5. The interleave device according to claim 4, further comprising a multiplier for generating a plurality of first address data. 8. The shifter according to claim 1, wherein the multiplier is a shift operation circuit that generates first address data having the predetermined address interval by bit-shifting a predetermined bit position of a counter output of the first counter. The interleaving device according to claim 7, characterized in that: 9. A transmission system in which the order of symbols of a transmission symbol sequence generated by encoding original data is randomly rearranged for each frame, and transmission data outputted and subjected to predetermined transmission processing and transmitted. In a deinterleave device that receives a signal and returns the order of each symbol of a received symbol sequence extracted from the received signal to the original arrangement order, a first interleaving device that generates a plurality of first address data having a predetermined address interval Address data generating means for generating second address data continuous with the first address data at each address interval;
An address generating apparatus comprising: address data generating means; and an adding means for sequentially generating addresses at predetermined intervals by sequentially adding the second address data to each of the first address data. A deinterleaving apparatus comprising: control means for sequentially allocating addresses at predetermined intervals to the received symbol sequence, thereby returning the order of each symbol of the received symbol sequence to the original arrangement order and outputting the same. 10. The control means has a storage means for storing the received symbol sequence, writes the received symbol sequence in the storage means based on the address at intervals of the predetermined interval, and a reading order different from the address. 10. The deinterleaving device according to claim 9, wherein the data is read out by: 11. The control means has storage means for storing the received symbol sequence, writes the received symbol sequence in a predetermined writing order in the storage means, and stores the received symbol sequence in the address at predetermined intervals. 10. The deinterleaving device according to claim 9, wherein reading is performed based on the following. 12. The first address data generating means comprises: a first counter for counting up to a predetermined value; and a predetermined address interval by multiplying a counter output of the first counter by a predetermined number. The deinterleave apparatus according to claim 9, further comprising a multiplier for generating a plurality of first address data. 13. The multiplying device according to claim 1, wherein the multiplier is a shift operation circuit for generating first address data having the predetermined address interval by bit-shifting a predetermined bit position of a counter output of the first counter. 13. The deinterleaving device according to claim 12, wherein: