JPH11316619A - Clock skew control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock skew control circuit capable of automatically controlling the timing of access to a memory even after packaging of a device and controlling the dispersion in products, the dispersion in the wiring length of the device and further the dispersion of timing caused by the external factor of the memory or the like. SOLUTION: When the power source of a device 11 is turned on, the write/ read of data to a memory 13 is performed by a semiconductor integrated circuit 12, a control circuit 14 judges whether the data can be normally written/read or not and when the data can not be normally written/read, skew is controlled by delay circuits 15a and 15b. Then, the write/read of data to the memory 13 is performed again. This sequence is repeated until the write/read of the memory 13 can be normally performed, and a skew value is controlled within the range controllable for the control circuit 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a skew adjustment circuit, and more particularly to a skew adjustment circuit for automatically adjusting a memory access timing.

[0002]

2. Description of the Related Art In a conventional semiconductor integrated circuit device, generally, the access timing to a memory device is fixed, and a device designer must specify a timing range defined at the time of designing a semiconductor integrated circuit for accessing a memory. It is necessary to design the device to meet the timing of access to the device. For this reason, it has been difficult to absorb variations in the timing of each device.

[0003] Some semiconductor integrated circuit devices can adjust the timing, but the adjustment requires an individual adjustment work process such as using a dip switch or the like, which is cumbersome, and furthermore, the mounting of the device. After that, an adjustment operation for adjusting the variation due to a change over time or the like is required.

As a circuit for automatically adjusting the clock skew without using any manpower or time, for example, a circuit disclosed in Japanese Patent Application Laid-Open No.
Reference is also made to the configuration described in, for example, JP-A-100768.

[0005]

As described above, it has conventionally been difficult to automatically absorb variations in access timing of individual semiconductor integrated circuits to a memory at the device design stage. The reason is that individual product variations of the semiconductor integrated circuit cannot be automatically absorbed at the design stage.

[0006] Further, even when the timing is adjusted after the device is mounted, there is a problem that man-hours such as manual work are required.

[0007] Therefore, the present invention has been made in view of the above-mentioned problems, and an object of the present invention is to make it possible to automatically adjust the access timing to a memory even after the device is mounted. An object of the present invention is to provide a circuit capable of adjusting a variation in wiring length and a variation in timing due to an external factor such as a memory.

[0008]

In order to achieve the above object, the present invention provides a method for automatically writing / reading data to / from a memory and determining whether or not the writing / reading has been normally performed, and a skew adjustment target. Means for adjusting the skew by varying the delay time of the variable delay means inserted in the path,
If it is not possible to write / read the memory normally, after adjusting the skew, write / read data to / from the memory again, and repeat the above sequence until writing / reading to the memory can be performed normally. To adjust the skew value.

[0009]

Embodiments of the present invention will be described below. The clock skew adjustment circuit of the present invention automatically enables access timing adjustment to a memory,
This makes it possible to absorb not only variations in the semiconductor integrated circuit itself but also variations due to external factors such as a memory.

In a clock skew adjusting circuit according to a preferred embodiment of the present invention, referring to FIG. 1, when a power supply of a device (11) is turned on, a semiconductor integrated circuit (12) writes data into a memory (13). Reading (for example, a write-after-read test) is performed, and it is determined by the adjustment circuit (14) whether or not writing / reading has been normally performed.
If writing / reading cannot be performed normally, the skew is adjusted by the delay circuits (15a, 15b), and data writing / reading to / from the memory 13 is performed again. This sequence is repeated until the writing / reading of the memory (13) can be performed normally, and the skew value is adjusted within a range adjustable by the adjusting circuit (14).

[0011] The present invention, in a preferred embodiment thereof,
Referring to FIG. 1, a delay inserted in a clock supply path to a clock synchronous memory (13) and a delay inserted in a path supplying a clock to an internal logic means (17) for supplying an address / data to the clock synchronous memory, respectively. The first and second delay means (15a, 15a,
15b) and upon power-on or reset, etc.,
Data writing / reading to / from the memory is automatically performed, and it is determined whether or not writing / reading to / from the memory (13) has been normally performed.
And / or an adjusting means (14) for adjusting the skew by varying the delay time of the second delay means. If the writing and reading cannot be performed normally, the skew is adjusted by the adjusting means (14) and then again. , Writing data to the memory
The skew value is adjusted by repeating the above sequence until reading and writing / reading of the memory can be performed normally.

In another preferred embodiment of the present invention, referring to FIG. 2, a control signal generating means (42) for generating and supplying a control signal to a clock asynchronous memory (33) is provided. First and second delay means which can variably set delay times inserted in a clock supply path and a path which supplies a clock to a logic means (37) for supplying an address / data to the clock asynchronous memory, respectively. (35a, 35b), when the power is turned on or at the time of reset, etc., the data is automatically written and read to and from the memory (33), and it is determined whether or not the writing and reading have been normally performed. Adjusting means (34) for adjusting the skew by varying the delay time of the first and / or second delay means in such a case. In this case, after the skew adjustment, the data is read and written to the memory again, and the skew value is adjusted by repeating the above sequence until the writing and reading of the memory can be performed normally. .

In the embodiment of the present invention, referring to FIG. 1 and FIG. 2, a clock from an oscillator (19, 39) is inputted, and a clock is distributed to the first and second delay means and supplied. Clock division means (18, 38) are provided.

In the embodiment of the present invention, the clock skew adjustment circuit is incorporated in a semiconductor integrated circuit, and can automatically adjust the skew after mounting the device together with a clock generation oscillator and a memory. Further, the clock skew adjustment circuit may be provided in the CPU.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention. Referring to FIG. 1, a device 11 includes a semiconductor integrated circuit 1
2, a clock synchronous memory 13 and an OSC (oscillator) 19 for generating a clock.

The semiconductor integrated circuit 12 includes the clock division circuit 1
2. It includes delay circuits 15a and 15b, internal logic 17, and adjustment circuit 14.

The clock generated by the OSC 19 is input to the semiconductor integrated circuit 12, is divided by the clock dividing circuit 18, passes through a delay circuit 15a and a delay circuit 15b whose delay time can be set variably, and outputs an internal logic signal. 17 and the clock synchronous memory 13.

When the power of the device 11 is turned on (or reset), the adjustment circuit 14 automatically reads and writes data from / to the clock synchronous memory 13 (for example, a read test after writing data to a memory). It is determined whether the data has been read or written normally, and the delay circuits 15a, 15a,
5b is performed.

[0020] Internal logic 17 and clock synchronous memory 13
Are connected by a data bus / address bus 20, and a clock synchronous memory 13 delay circuit exchanges data with the semiconductor integrated circuit 12 in synchronization with a clock signal 21 output to the clock synchronous memory 13 from 15b. Do.

The operation of one embodiment of the present invention will be described with reference to FIG. In FIG. 1, when the power of the device 11 is turned on,
The adjustment circuit 14 reads and writes data from and to the clock synchronous memory 13 via the internal logic 17. The adjustment circuit 14 determines whether data has been read or written normally. If the data is normal, the delay circuits 15a and 15b shift to the subsequent sequence in the initial state.

If the data cannot be read and written normally, the delay circuit 15a or the delay circuit 15b is controlled to change the skew between the clock signal to the internal logic 17 and the clock signal to the clock synchronous memory 13, and then, again to the clock synchronization. Data is read from and written to the type memory 13. This operation is continued until data can be read and written normally, or until the data can be adjusted by the delay circuits 15a and 15b.

Next, another embodiment of the present invention will be described with reference to the drawings.

In the present invention, the memory is not limited to a clock synchronous memory. FIG. 2 is a diagram showing the configuration of the second embodiment of the present invention. Referring to FIG.
In the second embodiment of the present invention, unlike the above embodiment, a clock asynchronous memory 33 is used instead of a clock synchronous memory, and a clock signal to an internal logic 37 and a control signal generation logic 42 is used. Delay circuits 35a, 3
5b, the clock asynchronous memory 3
3 is changed.

FIG. 3 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 3, in a third embodiment of the present invention, an OSC (oscillator) 52 and a central processing unit (CP)
U) 51, clock skew circuit 54, memory 52
During the skew adjustment period of the clock skew circuit 54, the CPU 51 prohibits the access to the memory 53, and permits the memory access after the skew adjustment. The clock skew adjustment circuit 54 according to the third embodiment of the present invention
The circuit 12 of the embodiment described with reference to FIG. 1 or FIG.
Or 32, and the description of the configuration and operation is omitted.

FIG. 4 is a diagram showing the configuration of the fourth embodiment of the present invention. Referring to FIG. 4, in a fourth embodiment of the present invention, a clock skew circuit 64 is incorporated in the central processing unit 61 in the third embodiment shown in FIG. The clock skew adjusting circuit 64 according to the fourth embodiment of the present invention has the same configuration as the circuit 12 or 32 of the above-described embodiment described with reference to FIG. 1 or FIG. Omitted.

[0027]

As described above, according to the present invention, the following effects can be obtained.

A first effect of the present invention is that a variation in timing of each semiconductor integrated circuit can be automatically absorbed.

The reason is that, in the present invention, since a delay circuit is inserted in each clock signal after being divided by the clock dividing circuit, it is possible to cope with either early or late timing due to individual variations. .

A second effect of the present invention is that variations in timing due to the wiring length between the semiconductor integrated circuit and the memory and variations in individual memories can be absorbed.

The reason is that, in the present invention, the skew can be automatically adjusted after the semiconductor integrated circuit is mounted as a device, so that the skew can be adjusted in a mounted state.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a diagram illustrating a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a diagram illustrating a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a fourth exemplary embodiment of the present invention.

[Explanation of symbols]

 11, 31 device 12, 32 semiconductor integrated circuit 12 clock synchronous memory 32 clock asynchronous memory 14, 34 adjustment circuit 15a, 15b, 35a, 35b delay circuit 17, 37 internal logic 18, 28 clock division circuit 19, 52, 62 Oscillator (OSC) 42 Control signal generation circuit 51, 61 CPU 52, 64 Clock skew adjustment circuit 53, 63 Memory

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04L 7/00 G11C 11/34 354C 362S

Claims (8)

[Claims] Claims: 1. A means for automatically writing / reading data to / from a memory to determine whether writing / reading has been performed normally, and a delay which can be variably set and inserted into a skew adjustment target path Means for adjusting the skew by varying the delay time of the means.If writing / reading of data to / from the memory cannot be performed normally, after adjusting the skew, the data is again transferred to the memory. A clock skew adjustment circuit which performs writing / reading and adjusts a skew value by repeating this sequence until writing / reading of the memory can be performed normally. 2. A delay means inserted into a transmission path of a clock signal, the delay time of which can be variably set, and automatically writing / reading data to / from a memory at power-on or at a reset or the like. Means for judging whether or not writing / reading has been successfully performed, and, if writing / reading cannot be performed normally, means for adjusting the skew by varying the delay time of the delay means. in case of,
After adjusting the skew, writing and reading data to and from the memory are performed again, and the skew value is adjusted by repeating this sequence until writing and reading to and from the memory can be performed normally. Adjustment circuit. 3. A delay time variably settable to a clock supply path to a clock synchronous memory and a path to supply a clock to a logic circuit means for supplying an address / data to the clock synchronous memory. The first and second delay means automatically write and read data to and from the memory when power is turned on or when a reset or the like is performed.
Adjusting means for judging whether or not reading is possible, and adjusting the skew by varying the delay time of the first and / or second delay means when writing and reading cannot be performed normally; If you cannot write / read normally,
After adjusting the skew by the adjusting means, the data is written / read from / to the memory again, and the above sequence is repeated until the writing / reading to / from the memory can be performed normally, thereby adjusting the skew value. Characteristic clock skew adjustment circuit. 4. A clock supply path to a control signal generating means for generating and supplying a control signal to a clock asynchronous memory, and a clock to a logic circuit means for supplying an address / data to the clock asynchronous memory. First and second delay times that can be variably set respectively inserted in the path
The delay means of the present invention automatically performs writing and reading of data to and from the memory at the time of power-on or at the time of reset, etc., and determines whether or not writing and reading can be performed normally. Adjusting means for adjusting the skew by varying the delay time of the first and / or second delay means. If the memory cannot be written and read normally, the skew is adjusted by the adjusting means and then re-adjusted. A clock skew adjustment circuit for writing and reading data to and from the memory and adjusting the skew value by repeating the above sequence until writing and reading to and from the memory can be performed normally. 5. The method according to claim 1, wherein a clock from an oscillator is input and said first,
5. The clock skew adjustment circuit according to claim 3, further comprising a clock dividing unit that distributes and supplies a clock to the second delay unit. 6. The clock skew adjustment circuit according to claim 1 is incorporated in a semiconductor integrated circuit, and can automatically adjust skew even after mounting the device together with a clock generation oscillator and a memory. Electronic devices. 7. A clock skew adjustment circuit according to claim 1, an oscillator for generating a clock,
An electronic device including a memory and a CPU. 8. A central processing unit provided with the clock skew adjustment circuit according to claim 1 in a CPU connected to a memory.