JPH11297959A - Structure of high-ferroelectric memory cell and manufacture therefor - Google Patents
Structure of high-ferroelectric memory cell and manufacture thereforInfo
- Publication number
- JPH11297959A JPH11297959A JP10104326A JP10432698A JPH11297959A JP H11297959 A JPH11297959 A JP H11297959A JP 10104326 A JP10104326 A JP 10104326A JP 10432698 A JP10432698 A JP 10432698A JP H11297959 A JPH11297959 A JP H11297959A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- ferroelectric memory
- ferroelectric
- electrode layer
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 18
- 239000002184 metal Substances 0.000 claims abstract description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract description 9
- 239000001257 hydrogen Substances 0.000 claims abstract description 7
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 7
- 230000003197 catalytic effect Effects 0.000 claims description 14
- 239000003054 catalyst Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 claims description 6
- 230000001629 suppression Effects 0.000 claims description 4
- 239000003990 capacitor Substances 0.000 abstract description 11
- 239000013078 crystal Substances 0.000 abstract description 5
- 125000004435 hydrogen atom Chemical group [H]* 0.000 abstract description 4
- 238000007772 electroless plating Methods 0.000 abstract description 3
- 238000006555 catalytic reaction Methods 0.000 abstract 3
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 229910052707 ruthenium Inorganic materials 0.000 abstract 1
- 238000007747 plating Methods 0.000 description 9
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 6
- 239000000243 solution Substances 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 3
- 229910052700 potassium Inorganic materials 0.000 description 3
- 239000011591 potassium Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- GSMCZRMXOTVCGF-UHFFFAOYSA-N 2-bromo-1-(5-methyl-1,2-oxazol-3-yl)ethanone Chemical compound CC1=CC(C(=O)CBr)=NO1 GSMCZRMXOTVCGF-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- JGLCONSOSSTGDG-UHFFFAOYSA-N gold(3+);tetracyanide Chemical compound [Au+3].N#[C-].N#[C-].N#[C-].N#[C-] JGLCONSOSSTGDG-UHFFFAOYSA-N 0.000 description 1
- HWSZZLVAJGOAAY-UHFFFAOYSA-L lead(II) chloride Chemical compound Cl[Pb]Cl HWSZZLVAJGOAAY-UHFFFAOYSA-L 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- NNFCIKHAZHQZJG-UHFFFAOYSA-N potassium cyanide Chemical compound [K+].N#[C-] NNFCIKHAZHQZJG-UHFFFAOYSA-N 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000002269 spontaneous effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は高・強誘電体メモリ
素子の構造及びその製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a high-ferroelectric memory device and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図３は従来のこの種の高・強誘電体メモ
リ素子のキャパシタ断面構造の一例を示す図である。高
・強誘電体メモリ素子のキャパシタは図示するように、
ＳｉＯ ２等の絶縁層１の上にＴｉＮ等のバリアメタル層
２を形成し、該バリアメタル層２の上にＰｔ等の下部電
極層３を形成し、該下部電極層３の上にＢＳＴ、Ｙｌ等
の高・強誘電体層４を形成し、該高・強誘電体層４の上
にＰｔ等の上部電極層５を形成した構造である。なお、
６はＰ−Ｓｉ等のプラグ層である。2. Description of the Related Art FIG. 3 shows a conventional high-ferroelectric memo of this kind.
It is a figure showing an example of the capacitor section structure of a re-element. High
・ The capacitor of the ferroelectric memory element is
SiO 2Barrier layer such as TiN on insulating layer 1 such as
2 and a lower electrode such as Pt is formed on the barrier metal layer 2.
An electrode layer 3 is formed, and BST, Yl, etc. are formed on the lower electrode layer 3.
Of the high / ferroelectric layer 4 is formed on the high / ferroelectric layer 4.
And an upper electrode layer 5 made of Pt or the like. In addition,
Reference numeral 6 denotes a plug layer of P-Si or the like.
【０００３】上記構造の高・強誘電体メモリ素子におい
て、上記各層を形成してキャパシタを形成後、例えばパ
シベーション膜堆積時、ダングリングボンドの終端処理
時、モールド中の樹脂からの水素放出時等に繰返し、水
素雰囲気中で高温に曝されることが不可避となってい
る。In the high / ferroelectric memory device having the above structure, after forming the above layers to form a capacitor, for example, when depositing a passivation film, terminating a dangling bond, releasing hydrogen from a resin in a mold, etc. It is unavoidable to be repeatedly exposed to high temperatures in a hydrogen atmosphere.
【０００４】[0004]
【発明が解決しようとする課題】上記構造では、高温の
水素ガス雰囲気中にＰｔ等の触媒活性の高い金属が露出
しているので、この触媒作用によって水素ガスから活性
水素原子が発生し、この活性水素原子が高・強誘電体層
４の中に浸入拡散し、その結晶の原子結合を切断し、本
来あるべき結晶構造を損傷してしまうためキャパシタ特
性やリーク特性が著しく劣化（所謂、誘電体特性の喪
失）するという問題があった。なお、高誘電体が高い比
誘電率をもち、強誘電体が高い比誘電率と自発分極性を
維持するため、結晶がペロブスカイト構造を保つことが
不可欠である。In the above structure, since a metal having high catalytic activity such as Pt is exposed in a high-temperature hydrogen gas atmosphere, active hydrogen atoms are generated from hydrogen gas by this catalytic action. The active hydrogen atoms penetrate and diffuse into the high / ferroelectric layer 4 to break the atomic bonds of the crystal and damage the original crystal structure, so that the capacitor characteristics and leak characteristics are significantly deteriorated (so-called dielectrics). (Loss of body characteristics). In addition, in order for a high dielectric substance to have a high relative dielectric constant and a ferroelectric substance to maintain a high relative dielectric constant and spontaneous polarization, it is essential that the crystal maintain a perovskite structure.
【０００５】本発明は上述の点に鑑みてなされたもの
で、水素ガス雰囲気中で高温に保持する操作を複数回繰
返しても活性水素原子が高・強誘電体層の中に浸入し、
その結晶の原子結合を切断してキャパシタ特性やリーク
特性を劣化させることのない高・強誘電体メモリ素子の
構造及びその製造方法を提供することを目的とする。The present invention has been made in view of the above points, and active hydrogen atoms penetrate into a high / ferroelectric layer even when an operation of maintaining a high temperature in a hydrogen gas atmosphere is repeated a plurality of times.
It is an object of the present invention to provide a structure of a high / ferroelectric memory element which does not degrade the capacitor characteristics and leak characteristics by breaking atomic bonds of the crystal and a method of manufacturing the same.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
請求項１に記載の発明は、高・強誘電体層に接して触媒
活性の高い金属からなる通電電極層を有する高・強誘電
体メモリ素子の構造において、通電電極層の露出面を触
媒活性の低い金属又は物質からなる触媒抑制層で被覆し
たことを特徴とする。In order to solve the above-mentioned problems, the present invention is directed to a high-ferroelectric material having a current-carrying electrode layer made of a metal having high catalytic activity in contact with the high-ferroelectric layer. In the structure of the memory element, the exposed surface of the current-carrying electrode layer is covered with a catalyst suppressing layer made of a metal or a substance having low catalytic activity.
【０００７】また、請求項２に記載の発明は、請求項１
に記載の高・強誘電体メモリ素子の構造において、通電
電極層がＰｔ層であり、触媒抑制層がＡｕ層であること
を特徴とする。[0007] The invention described in claim 2 is the first invention.
Wherein the energized electrode layer is a Pt layer and the catalyst suppression layer is an Au layer.
【０００８】また、請求項３に記載の発明は、高・強誘
電体層に接して触媒活性の高い金属からなる通電電極層
を有する構造を形成した後に、これを水素雰囲気中で高
温に保持する操作を行なう高・強誘電体メモリ素子の製
造方法において、各層を形成した後、通電電極の露出面
を触媒活性の低い金属又は物質からなる触媒抑制層で覆
い、その後水素雰囲気中で高温に保持する操作を行なう
ことを特徴とする。According to a third aspect of the present invention, after forming a structure having a conductive electrode layer made of a metal having high catalytic activity in contact with the high / ferroelectric layer, the structure is maintained at a high temperature in a hydrogen atmosphere. In the method for manufacturing a high-ferroelectric memory element, the exposed surface of the current-carrying electrode is covered with a catalyst suppressing layer made of a metal or a substance having low catalytic activity, and then exposed to a high temperature in a hydrogen atmosphere. The holding operation is performed.
【０００９】また、請求項４に記載の発明は、請求項３
に記載の高・強誘電体メモリ素子の製造方法において、
通電電極層がＰｔ層であり、触媒抑制層がＡｕ層である
ことを特徴とする。[0009] The invention described in claim 4 is the invention according to claim 3.
In the method for manufacturing a high-ferroelectric memory element according to
The current-carrying electrode layer is a Pt layer, and the catalyst suppressing layer is an Au layer.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態例を図
面に基づいて説明する。図１は本発明の高・強誘電体メ
モリ素子のキャパシタ断面構造の一例を示す図である。
本発明の高・強誘電体メモリ素子のキャパシタは、図１
に示すように、ＳｉＯ２等の絶縁層１の上にＴｉＮ等の
バリアメタル層２を形成し、該バリアメタル層２の上に
Ｐｔ等の下部電極層３を形成し、該下部電極層３の上に
ＢＳＴ、Ｙｌ等の高・強誘電体層４を形成し、該高・強
誘電体層４の上にＰｔ等の上部電極層５を形成し、更に
下部電極層３及び上部電極層５の露出面をＡｕ等の触媒
抑制層７で覆った構造である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a cross-sectional structure of a capacitor of a high / ferroelectric memory device according to the present invention.
The capacitor of the high / ferroelectric memory device of the present invention is shown in FIG.
As shown in FIG. 1, a barrier metal layer 2 such as TiN is formed on an insulating layer 1 such as SiO 2 , and a lower electrode layer 3 such as Pt is formed on the barrier metal layer 2. A high / ferroelectric layer 4 such as BST or Yl is formed thereon, an upper electrode layer 5 such as Pt is formed on the high / ferroelectric layer 4, and a lower electrode layer 3 and an upper electrode layer are formed. 5 has a structure in which the exposed surface is covered with a catalyst suppressing layer 7 of Au or the like.
【００１１】下部電極層３及び上部電極層５がＰｔ層で
ある場合、該下部電極層３及び上部電極層５の露出面上
にＡｕの触媒抑制層７を形成するには、ここでは無電解
Ａｕメッキで行なう。無電解メッキは元来、被メッキ基
材の触媒活性を利用してメッキ液からの析出を限定した
場所に行なうことができるものであるから、下部電極層
３及び上部電極層５の露出面にＰｔの触媒活性を利用し
て、その露出面だけに無電解Ａｕメッキ膜を形成する。In the case where the lower electrode layer 3 and the upper electrode layer 5 are Pt layers, in order to form the Au catalyst suppressing layer 7 on the exposed surfaces of the lower electrode layer 3 and the upper electrode layer 5, it is necessary to use an electroless It is performed by Au plating. Originally, since electroless plating can be performed at a place where deposition from a plating solution is limited by utilizing the catalytic activity of a substrate to be plated, the exposed surfaces of the lower electrode layer 3 and the upper electrode layer 5 Utilizing the catalytic activity of Pt, an electroless Au plating film is formed only on the exposed surface.
【００１２】メッキ条件は常法によって、例えば図２に
示す条件で行なう。即ち、浴型式がＡｕ（I）浴では、
メッキ液の成分種はジシアノ金（I）酸カリウム５．８
ｇ／ｌ、シアン化カリウム１３ｇ／ｌ、水酸化カリウム
１１．２ｇ／ｌ及び水素化ホウ素カリウム２１．６ｇ／
ｌの混合液であり、メッキ液温度７５℃で行なう。ま
た、Ａｕ（III）浴では、メッキ液の成分種はテトラシ
アノ金（III）酸カリウム３．０ｇ／ｌ、水酸化カリウ
ム１１．２ｇ／ｌ、塩化鉛０．５ｍｇ／ｌ及び水素化ホ
ウ素カリウム３．０ｇ／ｌの混合液であり、メッキ液温
度７０℃で行なう。The plating is performed by a conventional method, for example, under the conditions shown in FIG. That is, if the bath type is Au (I) bath,
The component of the plating solution is potassium dicyanoaurate (I) 5.8.
g / l, potassium cyanide 13 g / l, potassium hydroxide 11.2 g / l and potassium borohydride 21.6 g / l
and a plating solution temperature of 75 ° C. In the Au (III) bath, the components of the plating solution are potassium tetracyanoaurate (III) 3.0 g / l, potassium hydroxide 11.2 g / l, lead chloride 0.5 mg / l and potassium borohydride 3 g / l. It is a mixed solution of 0.0 g / l and is carried out at a plating solution temperature of 70 ° C.
【００１３】なお、上記例では、下部電極層３及び上部
電極層５にＰｔを用いる例を示したが、これに限定され
るものではなく、誘電率、耐久性、形成容易性等の条件
を満たすものなら良く、例えば、Ｒｕ等の金属層を用い
てもよい。また、触媒抑制層７として上記例ではＡｕの
無電解メッキ層としたが、これに限定されるものではな
く、下部電極層３及び上部電極層５の触媒活性を抑制す
る作用を有する金属又は物質の層であればよい。In the above example, Pt is used for the lower electrode layer 3 and the upper electrode layer 5. However, the present invention is not limited to this, and conditions such as permittivity, durability, and ease of formation are not limited to this. Any material that satisfies the condition may be used. For example, a metal layer such as Ru may be used. Further, in the above example, the catalyst suppression layer 7 is an Au electroless plating layer. However, the present invention is not limited to this. A metal or a substance having an action of suppressing the catalytic activity of the lower electrode layer 3 and the upper electrode layer 5 Layer.
【００１４】[0014]
【発明の効果】以上、説明したように各請求項に記載の
発明によれば、上下電極層の露出面を触媒活性の低い金
属又は物質からなる触媒抑制層で被覆するので、キャパ
シタ特性やリーク特性の劣化のない高・強誘電体メモリ
素子の提供及びその製造方法を提供できるという優れた
効果が得られる。As described above, according to the invention described in the claims, the exposed surfaces of the upper and lower electrode layers are covered with the catalyst suppressing layer made of a metal or a substance having a low catalytic activity, so that the capacitor characteristics and the leakage are reduced. An excellent effect of providing a high-ferroelectric memory element without deterioration in characteristics and a method of manufacturing the same can be obtained.
【図１】本発明の高・強誘電体メモリ素子のキャパシタ
断面構造の一例を示す図である。FIG. 1 is a diagram showing an example of a cross-sectional structure of a capacitor of a high-ferroelectric memory element according to the present invention.
【図２】Ａｕメッキの条件を示す図である。FIG. 2 is a diagram showing conditions of Au plating.
【図３】従来の高・強誘電体メモリ素子のキャパシタ断
面構造の一例を示す図である。FIG. 3 is a diagram showing an example of a cross-sectional structure of a capacitor of a conventional high / ferroelectric memory element.
１ 絶縁層 ２ バリアメタル層 ３ 下部電極層 ４ 高・強誘電体層 ５ 上部電極層 ６ プラグ層 ７ 触媒抑制層 DESCRIPTION OF SYMBOLS 1 Insulating layer 2 Barrier metal layer 3 Lower electrode layer 4 High / ferroelectric layer 5 Upper electrode layer 6 Plug layer 7 Catalyst suppression layer
フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０１Ｌ 29/792 Continued on the front page (51) Int.Cl. 6 Identification code FI H01L 29/792
Claims (4)
金属からなる通電電極層を有する高・強誘電体メモリ素
子の構造において、 前記通電電極層の露出面を触媒活性の低い金属又は物質
からなる触媒抑制層で被覆したことを特徴とする高・強
誘電体メモリ素子の構造。1. A structure of a high-ferroelectric memory element having a current-carrying electrode layer made of a metal having a high catalytic activity in contact with a high-ferroelectric layer, wherein an exposed surface of said current-carrying electrode layer is formed of a metal having a low catalytic activity. Or a structure of a high-ferroelectric memory element characterized by being coated with a catalyst suppressing layer made of a substance.
子の構造において、 前記通電電極層がＰｔ層であり、前記触媒抑制層がＡｕ
層であることを特徴とする高・強誘電体メモリ素子の構
造。2. The structure of a high / ferroelectric memory device according to claim 1, wherein said conductive electrode layer is a Pt layer, and said catalyst suppressing layer is Au.
A structure of a high-ferroelectric memory element, which is a layer.
金属からなる通電電極層を有する構造を形成した後に、
これを水素雰囲気中で高温に保持する操作を行なう高・
強誘電体メモリ素子の製造方法において、 前記各層を形成した後、前記通電電極の露出面を触媒活
性の低い金属又は物質からなる触媒抑制層で覆い、その
後水素雰囲気中で高温に保持する操作を行なうことを特
徴とする高・強誘電体メモリ素子の製造方法。3. After forming a structure having a current-carrying electrode layer made of a metal having high catalytic activity in contact with the high / ferroelectric layer,
The operation of maintaining this at a high temperature in a hydrogen atmosphere
In the method for manufacturing a ferroelectric memory element, after forming each of the layers, the exposed surface of the current-carrying electrode is covered with a catalyst suppression layer made of a metal or a substance having a low catalytic activity, and thereafter, an operation of holding at a high temperature in a hydrogen atmosphere is performed. A method for manufacturing a high-ferroelectric memory element.
子の製造方法において、 前記通電電極層がＰｔ層であ
り、前記触媒抑制層がＡｕ層であることを特徴とする高
・強誘電体メモリ素子の製造方法。4. The method for manufacturing a high / ferroelectric memory device according to claim 3, wherein the current-carrying electrode layer is a Pt layer, and the catalyst suppressing layer is an Au layer. A method for manufacturing a dielectric memory element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10104326A JPH11297959A (en) | 1998-04-15 | 1998-04-15 | Structure of high-ferroelectric memory cell and manufacture therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10104326A JPH11297959A (en) | 1998-04-15 | 1998-04-15 | Structure of high-ferroelectric memory cell and manufacture therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11297959A true JPH11297959A (en) | 1999-10-29 |
Family
ID=14377821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10104326A Pending JPH11297959A (en) | 1998-04-15 | 1998-04-15 | Structure of high-ferroelectric memory cell and manufacture therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11297959A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333660B1 (en) * | 1999-06-30 | 2002-04-24 | 박종섭 | Method for forming ferroelectric capacitor |
| KR100351056B1 (en) * | 2000-06-27 | 2002-09-05 | 삼성전자 주식회사 | Method of manufacturing semiconductor device including step of selectively forming metal oxide layer |
| KR100402943B1 (en) * | 2000-06-19 | 2003-10-30 | 주식회사 하이닉스반도체 | High dielectric capacitor and a method of manufacturing the same |
-
1998
- 1998-04-15 JP JP10104326A patent/JPH11297959A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100333660B1 (en) * | 1999-06-30 | 2002-04-24 | 박종섭 | Method for forming ferroelectric capacitor |
| KR100402943B1 (en) * | 2000-06-19 | 2003-10-30 | 주식회사 하이닉스반도체 | High dielectric capacitor and a method of manufacturing the same |
| KR100351056B1 (en) * | 2000-06-27 | 2002-09-05 | 삼성전자 주식회사 | Method of manufacturing semiconductor device including step of selectively forming metal oxide layer |
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