JPH1127329A - Fsk demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and to attain a low cost by sampling binary logic data of a base band FSK signal at a rate of twice per one symbol period or over and discriminating logically a frequency shift state for each symbol period from a logic code pattern state of a data stream sampled for 2-symbol period at least so as to generate demodulation data. SOLUTION: The demodulation circuit is provided with a sampling circuit 3 that samples binary logic data of a base band FSK signal (fb') waveform- shaped into a binary pulse signal at a rate of twice per one symbol period Ts or over, and also with a frequency shift discrimination logic circuit 5 that discriminates logically a frequency shift state for each symbol period from a logic code pattern state of a data string sampled at least over 2 symbol periods, and a data generating circuit 6 that generates demodulation data based on the discrimination result. Thus, digital data are demodulated from an FSK signal with a comparatively simple logic operation without complicated analog processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an FSK demodulation circuit,
Further, the present invention relates to a technology effective when applied to digital demodulation of a multi-frequency FSK signal, and relates to a technology effective for use in, for example, a pager terminal or a mobile communication device that receives character data.

[0002]

2. Description of the Related Art In the field of digital data communication such as a pager, an FSK modulation method for shifting a frequency according to a logical value of "1" and "0" is often used (for example,
Published by Nikkei BP, "Nikkei Electronics 1997
10 (No. 682), pp. 137, 138).

[0003] More recently, in order to increase the data transmission efficiency, a multi-frequency FSK modulation system that takes a plurality of frequency shift states has attracted attention. In this multi-frequency FSK modulation method, for example, +4.8 kHz, -4.8 kHz, +1.
By associating four frequency shift states of 6 kHz and -1.6 kHz with four digital data values of "10", "00", "11", and "01", one frequency shift operation, that is, one frequency shift operation, i. It is possible to transmit 2-bit digital data in a symbol period.

[0004] Regarding the demodulation processing of the above-mentioned multi-frequency FSK modulation signal, conventionally, an FSK modulation signal at an IF (intermediate frequency) stage before being demodulated into a base hand signal is converted to a modulation signal component of ± 4.8 kHz, for example. The signal is separated into ± 1.6 kHz modulated signal components, and “1” is output from each separated signal.
After demodulating the binary data "0" and "0", demodulated data "10", "00", "11", and "01" are generated from the two demodulated data.

[0005]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, since the conventional FSK demodulation circuit has a high dependence on analog circuits, it has been difficult to increase the semiconductor integration rate and to achieve low power consumption by reducing the circuit scale.

Therefore, digitalization of an analog circuit using a DSP or the like has been studied. In many cases, the digitalization that has been studied in the past simply replaces the function of a conventional analog circuit with a digital circuit as it is. In itself, the operation of analog circuits was merely digitally simulated. Specifically, A
A / D converter is provided, and the FSK modulated signal digitized (quantized) by the A / D converter is processed using a digitized band pass filter, a digitized IF amplifier circuit, and the like. In other words, the analog circuit was simply replaced by a digital circuit.

In this case, although the semiconductor integration rate can be increased, digital processing that simulates the operation of an analog circuit as it is requires a huge amount of data to be handled, and furthermore, the processing of the data requires a large number of man-hours. It gets very complicated.

As described above, the digitization of the FSK demodulation circuit, which has been conventionally studied, can be expected to have an effect of increasing the semiconductor integration rate, but the effect is not so large in terms of the reduction in the circuit scale and the resulting reduction in power consumption. Could not be expected.

An object of the present invention is to provide a technique for achieving digitization of an FSK demodulation circuit with a simple and small-sized configuration, thereby achieving a great reduction in power consumption and cost. .

The above and other objects and features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the binary logic data of the baseband FSK signal, which has been shaped into a binary pulse signal, is sampled at a rate of two or more times in one symbol period. The logic shift state of each symbol period is logically determined from the logical code pattern state, and demodulated data is generated based on the determination result.

According to the above-described means, a single binary pulse signal whose waveform is shaped from a baseband FSK signal received and processed by a single analog processing system is used to generate the FS signal.
The modulated data included in the K signal can be directly demodulated.

This achieves the object of realizing digitization of the FSK demodulation circuit with a simple and small-scale configuration, thereby realizing a great reduction in power consumption and cost.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a baseband FS having a waveform shaped into a binary pulse signal.
Sampling means (3) for sampling binary logical data of the K signal (fb ') at least twice in one symbol period (Ts), and a logical code pattern state of a data string sampled in at least two symbol periods And a frequency shift determining means (5) for logically determining a frequency shift state for each symbol period, and a data generating means (5) for generating demodulated data based on the determination result of the frequency shift determining means (5). Thus, digital data demodulation from an FSK signal can be performed by relatively simple logical operations without depending on complicated analog processing.

According to a second aspect of the present invention, in the first aspect, a serial data sequence on a time series sampled in one or a plurality of symbol periods is sequentially converted into a plurality of bits of parallel data every sampling. A serial-to-parallel conversion circuit (4), and frequency shift determining means (5) for logically determining the frequency shift state for each symbol period from the logical code pattern state of the parallel data. The logical state of the transition state in the time series can be accurately determined.

According to a third aspect of the present invention, in the first or second aspect, the symbol synchronization detecting means (71) for logically detecting the symbol switching timing of the FSK signal (fb ') from the logical code pattern state of the sampled data sequence. ) And a clock generation means (72) for providing a sampling clock (φp) to the sampling means (3) based on the detection result of the symbol synchronization detection means (71).
Thus, the sampling timing of the FSK signal can be correctly determined according to the symbol period.

The invention according to claim 4 is the invention according to claims 1 to 3
A serial-to-parallel conversion circuit (4) for sequentially converting a serial data sequence on a time series sampled in a plurality of symbol periods into parallel data of a plurality of bits each time sampling is performed; Symbol synchronization detection means (71) for logically detecting the symbol switching timing of the FSK signal (fb ') from the logical code pattern state
Accordingly, symbol switching detection can be accurately performed in units of a sampling rate.

The invention described in claim 5 is the invention according to claims 1 to 4
In any one of the above, a symbol synchronization detecting means (71) for logically detecting a symbol switching timing of the FSK signal (fb ') and a PLL operating in synchronization with the symbol switching timing detected by the symbol synchronization detecting means (71) And a sampling clock generating means (72) for generating a sampling clock (φp) based on a signal generated by the synchronous operation of the PLL, whereby the sampling clock having a fixed synchronous relationship with the symbol period is provided. (Φp) can be generated stably.

[0021] The invention according to claim 6 is the invention according to claims 1 to 5.
In any one of the above, a symbol synchronization detecting means (71) for logically detecting the symbol switching timing of the FSK signal (fb '), and a multi-phase sampling clock (.phi.1) based on the detection result of the symbol synchronization detecting means (71). , Φ2, φ3,..., Φn), and a sampling data sequence in each symbol period of the FSK signal (fb ′) from among the sampling clocks of the plurality of phases. And a phase selecting unit (83) for selecting a sampling clock having a phase so as to have a predetermined logical code pattern state according to the frequency shift state and supplying the selected sampling clock to the sampling unit (3). Can be optimized to further enhance the quality of demodulated data.

According to a seventh aspect of the present invention, there is provided a detection circuit (17) for demodulating a baseband FSK signal (fb ') waveform from an FSK-modulated radio reception signal (fr), and a demodulated baseband FSK signal (fb'). fb ′) into a binary pulse signal of “1” and “0”, and a baseband FSK signal (f
sampling means (3) for sampling b ′) twice or more in one symbol period (Ts), and a frequency shift state for each symbol period from a logical code pattern state of a data sequence sampled in at least two symbol periods And a data generating means (5) for generating demodulated data based on the result of the determination by the frequency shift determining means (5). The digitalization rate and the semiconductor integration rate of the FSK receiver can be increased, and the power consumption can be significantly reduced by simplifying the configuration of the digital portion.

According to an eighth aspect of the present invention, in the seventh aspect, there is provided a detection circuit (17) for demodulating the FSK-modulated radio reception signal (fr) into a baseband FSK signal (fb ') waveform by synchronous detection. A reference oscillation circuit (20) for oscillating a detection reference signal (fL2) for performing the synchronous detection, and a logical code pattern state of a data string sampled by the sampling means (3) are set to a predetermined state. And a frequency calibration control means (81) for calibrating and controlling the oscillation frequency of the reference oscillation circuit (20). This makes it possible to eliminate the need for FSK synchronous detection and to achieve error-free correct reception and operation. Data demodulation can be performed.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a first embodiment of an FSK demodulation circuit to which the technique of the present invention is applied.

The FSK demodulation circuit shown in FIG. 1 comprises a sampling circuit 3, a serial / parallel conversion circuit 4, a frequency shift discrimination circuit 5, a data generation circuit 6, and a synchronization formation circuit 7, and generates a binary pulse from the baseband FSK signal fb. It operates with the FSK signal fb 'shaped into a signal as an input signal.

In the figure, the sampling circuit 3 converts the binary logical data of the baseband FSK signal fb ′, which has been shaped into a binary pulse signal by the waveform shaping circuit 31, into a signal at a rate of twice or more in one symbol period Ts. Sampling at
The sampled data is input to the frequency shift determination circuit 5 via the serial / parallel conversion circuit 4.

The serial-to-parallel conversion circuit 4 is constituted by using a shift register, holds sampling data for at least two symbol periods in the input order, and outputs the held data in parallel.

The frequency shift discriminating circuit 5 constantly monitors the state of the bit pattern (logical code pattern) of the parallel data that is updated each time sampling is performed, and based on the bit pattern state of the data sequence sampled in at least two symbol periods. , Logically determine the frequency shift state for each symbol period Ts.

The data generation circuit 6 generates demodulated data Dout based on the result of the logical determination by the frequency shift determination circuit 5.

The details of the synchronization forming circuit 7 will be described later.
The switching timing of the symbol period Ts of the SK signal fb ′ is logically detected, and a sampling clock φp that determines the sampling timing of the FSK signal fb ′ is generated based on the detection.

Next, the operation will be described.

FIG. 2 shows an operation waveform chart of a main part of the circuit shown in FIG.

In the figure, the baseband FSK signal f
b is a multi-frequency FSK signal with frequency detuning of ± 4.8 kHz and ± 1.6 kHz, and each symbol period (Ts
= 1 / 6.4 kHz), +4.8 kHz, -4.
There are four frequency shift states of 8 kHz, +1.6 kHz and -1.6 kHz. The four frequency shift states correspond to four 2-bit digital data values of “10”, “00”, “11”, and “01”.

The baseband FSK signal fb is subjected to level discrimination at a zero crossing point and shaped into a binary pulse signal of "1" and "0". The binary logic data of the baseband FSK signal fb ′ whose waveform has been shaped is sampled at a rate of six times in one symbol period.

As a result, 6 times per one symbol period Ts
The binary data sequence for the bits is sampled and sent to the frequency shift determination circuit 5.

The frequency shift determining circuit 5 logically determines the frequency shift state for each symbol period Ts from the bit pattern of "1" and "0" of the sampled binary data sequence. The bit pattern in each symbol period reflects the period and the waveform state of the FSK signal fb, and has a unique logical characteristic according to the frequency shift state.

For example, in FIG. 2, +4.8 kHz
Alternatively, the FSK signal fb in the frequency shift state of -4.8 kHz takes one symbol period (Ts = 1/6.
4 kHz), a waveform change of 3/2 wavelength occurs. When this waveform change occurs, different bit values are sampled between a 2/3 period (= 2Ts / 3) and a 1/3 period (Ts / 3) of one symbol period Ts. When sampling is performed six times in one symbol period Ts,
Four continuations of "1" and two continuations of "0", or four continuations of "0" and two continuations of "1" appear in the one symbol period Ts. Thereby, “111100”, “0”
When a bit pattern of “00011”, “110000”, or “001111” appears, the frequency shift state in the symbol period Ts in which the bit pattern appears is ± 4.8 k.
Hz can be logically determined.

In addition, +1.6 kHz or -1.6 kHz
FSK signal fb when the frequency shift state of z is taken
Causes a waveform change of 波長 wavelength during one symbol period (Ts = 1 / 6.4 kHz). When this waveform change occurs, the same bit value is continuously sampled throughout one symbol period Ts. One symbol period T
If s is sampled six times, either "1" or "0" will appear six consecutive times. Accordingly, when a bit pattern of “111111” or “000000” appears, it can be logically determined that the frequency shift state in the symbol period Ts in which the bit pattern appears is ± 1.6 kHz.

The shift direction of the frequency can also be logically determined by the transition state of the bit pattern sampled in each of two successive symbol periods in the time series. For example, as shown in FIG.
The transition from “111100” to “111111” is +
The transition from "111111" to "111100" can be logically determined as a frequency shift from 4.8 kHz to -1.6 kHz as a frequency shift from -1.6 kHz to -4.8 kHz.

In this case, the types of bit patterns sampled in each symbol period are “111100”, “0000011”,
“110000”, “001111”, ± 1.6 kHz
“000000”, “11111” appearing in the waveform of z
1 ". Thus, each frequency shift state is +4.8 kHz, -4.8 kHz, +1.6 kHz.
z, -1.6 kHz is in the next frequency shift state +4.8
kHz, -4.8 kHz, +1.6 kHz, -1.6 kHz
There are 36 possible bit pattern combinations when transitioning to Hz. Therefore, if the bit pattern sampled in two successive symbol periods corresponds to any of the above 36 patterns, the shift direction of the frequency can be logically determined.

By sampling the binary logic data of the baseband FSK signal fb ', which has been shaped into a binary pulse signal as described above, twice or more in one symbol period Ts, the baseband FSK Signal f
The frequency shift state of b ′ can be logically determined. Then, based on the result of the logical determination, as shown in FIG. 3, +4.8 kHz, -4.8 kHz, +1.6 kHz.
z, “10”, “0” corresponding to each state of −1.6 kHz
The symbol patterns of “0”, “11”, and “01” can be created for each symbol period to obtain demodulated data Dout.

It should be noted that ± 4.8 kHz
And a multi-frequency F that takes two kinds of frequency detuning of ± 1.6 kHz
The demodulation process of the SK signal is performed by a logical determination process on a single baseband FSK signal fb ′ that has been shaped into a binary pulse signal. This allows
Digitization of the FSK demodulation circuit is achieved with a simple and small-scale configuration, and significant reduction in power consumption and cost can be achieved.

FIG. 3 shows a symbol pattern diagram of the 4FSK signal.

The 4FSK signal is, as described above, +4.
8 kHz, -4.8 kHz, +1.6 kHz, -1.6
There are four frequency shift states of kHz. in this case,
Two bits (four patterns) of data “10”, 2 bits in one symbol period are provided by an I axis indicating two shift frequencies (4.8 kHz / 1.6 kHz) and a Q axis indicating a shift direction (+/−). “00”, “11”, and “01” are expressed.

FIG. 4 shows a symbol pattern diagram of the 2FSK signal.

The shift frequency of the 2FSK signal is one (±
4.8 kHz), and its frequency shift state is +
There are only two types, 4.8 kHz and -4.8 kHz. In this case, 1-bit data of "1" or "0" is represented only by the Q axis indicating the frequency shift direction (+/-).

In the FSK demodulation circuit shown in FIG.
4FSK signal can be demodulated, but + 4.8k
Hz and -4.8 kHz frequency shift state "1"
And 1-bit data of “0” are generated,
It can be adapted to demodulation of FSK signals.

FIG. 5 shows a specific configuration example of the synchronization forming circuit 7.

The synchronizing circuit 7 shown in FIG. 7 includes a symbol detection logic circuit 71 for logically detecting the symbol period Ts.
And a sampling clock generation circuit 72 using a PLL (phase control loop).

The symbol synchronization detection circuit 71 logically detects the switching timing of the symbol period Ts based on the transition state of the bit pattern obtained by sampling the FSK signal fb ', and detects the symbol synchronization synchronized with the switching timing. A clock φs is generated.

The detection of the symbol period Ts in this case can be logically performed as follows.

That is, the types of bit patterns sampled for each symbol period Ts are "111100", "0000011", and "1100" as described above.
00 "," 001111 "," 000000 "," 11
1111 ". Therefore, the point in time when any of the bit patterns is completed is determined by the symbol period T.
This can be regarded as the switching timing of s.

In this case, if bit patterns such as "111111" or "000000" appear continuously, the delimitation of the bit patterns becomes unclear, and the timing for switching the symbol patterns can be accurately determined. May disappear. But,
If it is determined in advance that the specific data such as “10” (= + 4.8 kHz) is to be repeatedly transmitted in the training procedure executed at the beginning of the data transmission procedure, the bit pattern ( For example, from “111100”), the break of the bit pattern can be specified, and the cycle of the symbol period Ts and the switching timing thereof can be accurately detected.

In this way, once the delimitation of the symbol period can be correctly determined, no matter how the type of bit pattern appearing in the subsequent symbol period changes in a predetermined manner, the symbol period of that symbol period can be changed. It becomes possible to correctly logically identify a break.

The sampling clock generation circuit 72 outputs V
It is configured using a PLL including a CO (variable frequency oscillator) 73, first and second frequency dividing circuits 741 and 742, a phase comparator 75, and an LPF (low-pass filter) 76.

The VCO 73 sets the number of times of sampling for each symbol period Ts to k and the symbol cycle (1 / Ts).
Is set to fs, and when n is an arbitrary integer of 2 or more, a signal having a frequency fx near k × n × fs is continuously oscillated.

The first frequency dividing circuit 741 divides the oscillation frequency fx of the VCO 73 by n to generate a frequency of fx / n.
The second frequency dividing circuit 742 further divides the frequency of fx / n by k to generate a frequency of fx / (k × n).

The phase comparator 75 includes frequency dividing circuits 741 and 74
The oscillation frequency fx / divided by fx / (k × n) at 2
The (k × n) signal is compared in phase with the symbol synchronization clock φs output from the symbol synchronization detection circuit 71. An LPF 7 whose comparison output has a predetermined delay time constant
6 and is fed back to the VCO 73 as a frequency control signal. Thereby, the oscillation frequency fx of the VCO 73 becomes k × the frequency of the symbol synchronization clock φs.
Phase locked to n times the frequency.

In this phase locked state, a symbol cycle fs (= 1 / T) is input from the input side of the second frequency dividing circuit 741.
A sampling clock φp (= k × fs) having a frequency (k × fs) k times the frequency of s) can be extracted. For example, if the symbol cycle fs is 6.4 kHz and the number of samplings k per symbol period is 6, 6.4
A sampling clock φp of kHz × 6 times = 38.4 kHz is obtained.

FIG. 6 shows a first embodiment of the FSK receiving apparatus using the FSK demodulation circuit according to the present invention.

The FSK receiver shown in FIG.
The pager receiver receives modulated character data, and includes a wireless receiving unit 1 mainly including an analog circuit and a data demodulating unit 2 mainly including a digital circuit.

The radio receiving section 1 includes an RF (high frequency) preamplifier 12 for pre-amplifying a radio signal input from an antenna 11, a BPF (band pass filter) 13 for extracting a target reception frequency band, and a radio reception signal fr. Mixer 14 for frequency conversion (down-converting) to IF (intermediate frequency) signal fi, BP for extracting frequency-converted IF signal fi
F15, an IF unit 16 including an IF amplifier circuit and an AGC (automatic gain control circuit), a synchronous detector 17 for demodulating the baseband FSK signal fb from the IF signal fi, an LPF 18 for extracting the demodulated FSK signal fb, and the mixer 14 includes a local oscillator circuit (first local oscillator) 19 for supplying a local signal fL1 for frequency conversion, a reference oscillator circuit (second local oscillator) 20 for supplying a detection reference signal fL2 to the synchronous detector 17, and the like. Have been.

The data demodulation unit 2 has a waveform shaping circuit 31 for shaping the baseband FSK signal fb received and demodulated by the radio reception unit 1 into a binary pulse signal with reference to the zero level. Band FSK signal f
The binary logical data of b ′ is k times (6 times in one symbol period Ts).
), A serial-to-parallel conversion circuit 4 for sequentially converting the sampled binary logical data sequence into parallel data every sampling, and a frequency shift based on the bit pattern of the parallel-converted sampled data sequence. A frequency shift determining circuit 5 for logically determining the state; a data generating circuit 6 for generating demodulated data Dout based on the logical determination result of the frequency shift determining circuit 5;
It is composed of a synchronization forming circuit 7 that logically detects the switching timing of the symbol period Ts of the SK signal fb ′ and generates the sampling clock φp of the FSK signal fb ′.

FIG. 7 shows an operation waveform chart of a main part of the above-mentioned FSK receiving apparatus.

In the figure, fi is ± 4.8 kHz and ±
2 shows an IF signal that is FSK-modulated with two types of frequency detuning of 1.6 kHz. By performing synchronous detection using the detection reference signal fL2 having the same frequency as the center frequency fo of the IF signal fi, +4.8 kHz is used for each symbol period Ts.
z, -4.8 kHz, +1.6 kHz, -1.6 kHz
Baseband FS in any frequency shift state
The K signal fb is obtained. This baseband FSK signal f
b is shaped into a binary pulse signal (fb '), and sampling is performed k times (six times) in one symbol period Ts, so that a bit corresponding to the frequency shift state is obtained for each symbol period Ts. A binary logical data sequence exhibiting a pattern is obtained. Therefore, demodulated data Dout for each symbol period Ts can be generated by logically determining the bit pattern.

FIG. 8 is a waveform chart for demodulating a GMSK-modulated received signal.

In the GMSK modulation, in order to suppress the spread of the frequency bandwidth of the modulation signal, the waveform change between the symbol periods Ts and the symbol periods Ts is gentle as shown in FIG. Also, data demodulation can be performed by digital processing similar to that described above.

FIG. 9 shows a second embodiment of the FSK receiving apparatus according to the present invention.
Is shown.

The FSK receiving apparatus shown in FIG. 13 is provided with a frequency calibration control circuit 81 for calibrating the frequency of the detection reference signal fL2 supplied to the synchronous detection unit 17, in addition to the configuration of the receiving apparatus shown in FIG. Have been.

The frequency calibration control circuit 81 operates such that the bit pattern state of the data string sampled by the sampling circuit 3 becomes a state assumed in advance for each frequency shift state. ) 2
The oscillation frequency (fL2) of 0 is variably set.

FIG. 10 shows an operation waveform chart of the main part of the receiving apparatus shown in FIG.

In the figure, (A) shows the synchronous detection unit 17.
The frequency of the detection reference signal fL2 supplied to the
7 shows a detection waveform when the center frequency fo of i is correctly adjusted.

The IF signal fi, which is FSK-modulated with frequency detuning of ± 4.8 kHz and ± 1.6 kHz, has fo ± 4.8 kHz and fo ±, based on the center frequency fo.
A frequency shift state of 1.6 kHz is taken. By synchronously detecting the IF signal fi with the detection reference signal fL2 having the same frequency as the center frequency fo, as shown in (A), +4.8 kHz, -4.8 kHz, +1.6 kHz.
A baseband FSK signal fb that correctly takes any one of the frequency shift states of z and -1.6 kHz is obtained.

However, if the detection reference signal fL2 is detuned from the center frequency fo, as shown in FIG.
Distortion occurs in the waveform of the K signal fb. When this distortion becomes larger than a certain level, the bit pattern of the binary data sequence sampled for each symbol period Ts deviates from a normal state assumed in advance, and the bit pattern state is used to determine the logic of the frequency shift state based on the bit pattern state. An error will occur.

For example, in the training procedure, +4.8
When the frequency shift state of kHz (= “10”) continues, the baseband FSK signal fb synchronously detected with the detection reference signal fL2 of the normal frequency fo has its +4.8 value.
The frequency shift state of kHz appears exactly. As a result, also in the binary sampling data of the baseband FSK signal fb, only the normal bit pattern “111100” corresponding to the +4.8 kHz frequency shift repeatedly appears.

However, if the detection reference signal fL2 is detuned from the normal frequency fo, the baseband F synchronously detected with the detection reference signal fL2 (= fo + Δ) is used.
In the SK signal fb, a frequency shift (+4.8 kHz- [Delta]) corresponding to the detuning occurs, and the frequency shift state of +4.8 kHz does not accurately appear. That is, frequency distortion occurs in the baseband FSK signal fb. Thereby, “111110” (or “111110”) is added to the binary sampling data of the baseband FSK signal fb.
An incorrect bit pattern such as 000 ") appears, which hinders the logical discrimination for data demodulation.

Therefore, in the FSK receiving apparatus shown in FIG. 9, when an incorrect bit pattern that should not appear in the normal frequency shift state appears by the frequency calibration control circuit 81, the state of the incorrect bit pattern appears. Logically determines the frequency detuning direction of the detection reference signal fL2 from
The detection reference signal fL2 is calibrated to the normal frequency fo by variably setting the oscillation frequency (fL2) of the reference oscillation circuit 20 based on the determination result.

FIG. 11 shows a second embodiment of the FSK demodulation circuit according to the present invention.

The demodulation circuit shown in the figure comprises a sampling circuit 3, a serial / parallel conversion circuit 4, a frequency shift discrimination circuit 5, a data generation circuit 6, a synchronization formation circuit 7, a multi-phase clock generation circuit 82, and a phase selection circuit 83. Have been.

Here, the sampling circuit 3 and the serial-parallel conversion circuit 4 are configured using first and second two-stage serial shift registers 32 and 33. The baseband FSK signal fb 'shaped into a binary pulse signal is distributed to the shift inputs of the two shift registers 32 and 33, and is sampled and serially transferred.

The frequency shift discriminating circuit 5 is provided for each shift stage (F1 to F6) of the first and second shift registers 32 and 33.
Logically determine the frequency shift state for each symbol period Ts based on the bit data string extracted in parallel from.

The data generating circuit 6 generates demodulated data based on the result of the logical determination by the frequency shift determining circuit 5.

The synchronizing circuit 7 has a PL as in the case described above.
L, and logically detects the switching timing of the symbol period Ts of the FSK signal fb ′.
Based on this detection, a sampling clock φp that determines the sampling timing of the FSK signal fb ′ is generated.

In this case, the synchronization forming circuit 7 generates, as the sampling clock φp, two-phase clocks I and IB having a period that is ２ times the symbol period Ts of the baseband FSK signal fb ′. The two-phase clocks I and IB are clocks having phases opposite to each other. One clock I is given to the first shift register 32 and the other clock I is given to the second shift register 33 as a sampling and shift clock, respectively. Can be

The multi-phase clock generating circuit 82 generates an n-phase (n is an integer of 2 or more) phase clock φ based on the symbol synchronization detection result of the synchronizing circuit 7.
1, φ2, φ3, φ4, ..., φn are generated.

The phase selection circuit 83 shifts the frequency of the sampling data train in each symbol period Ts of the FSK signal fb ′ from the n-phase sampling clocks φ1, φ2, φ3, φ4,. A clock having a phase such that a predetermined logical code pattern state corresponding to the state is selected, and this is selected as a sampling clock φp (I, I
This is given to the sampling circuit 3 as B).

The phase selection by the phase selection circuit 83 is performed based on the state of the bit pattern of the sampled binary data sequence. That is, when the bit pattern of the binary data string sampled for each symbol period Ts is out of the normal state assumed in advance, a sampling clock having a phase such that the bit pattern is in the normal state is searched. And select.
This makes it possible to automatically determine the optimal sampling timing that minimizes the discrimination error in the frequency shift discrimination circuit 5.

FIG. 12 shows a configuration example of the multiphase clock generation circuit 82.

The multi-phase clock generation circuit 82 shown in FIG.
The clock signal fp generated based on the symbol period Ts by the synchronization forming circuit 7 is shifted and input to the n-stage shift register 84, and the clock signal n · fp having a frequency n times the clock signal fp is input to the shift register 84. Perform serial shift transfer.

As a result, as shown in FIG. 13, each of the shift stages (F1, F2, F3, F
4,..., Fn), it is possible to extract n-phase multiphase clocks having phases different by 1 / n.

FIG. 13 shows multi-phase clocks φ1, φ2, φ3, φ4,... Generated by multi-phase clock generation circuit 82.
And the waveform chart of φn.

FIG. 14 shows a specific configuration example of the synchronization forming circuit 7 used in the demodulation circuit of FIG.

As shown in the figure, the synchronization forming circuit 7 includes a symbol detection logic circuit 71 for logically detecting the symbol period Ts and a sampling clock generation circuit 72 using a PLL (phase control loop). It is configured.

The symbol synchronization detecting circuit 71 logically detects the switching timing of the symbol period based on the transition state of the bit pattern obtained by sampling the FSK signal fb ′, and outputs the symbol synchronization clock φs synchronized with the switching timing. Generate

The sampling clock generation circuit 72 outputs V
CO 73, the first to fourth frequency dividers 741 to 744, the phase comparator 75, and the LPF (low-pass filter) 76
It is configured using LL.

When the number of times of sampling in one symbol period Ts is k and the symbol cycle (1 / Ts) is fs, the VCO 73 has a frequency near k × fs × n (n is the number of phases of the multiphase clock). fx is configured to self-run.

The first frequency dividing circuit 74 divides the oscillation frequency fx of the VCO 73 by 1 / n. The second frequency dividing circuit 742 calculates f
The frequency signal divided by x / n is further divided by ３. The third frequency divider 743 divides the frequency signal divided by fx / n by １ ／. The fourth frequency dividing circuit 744 is VC
Oscillation frequency fx of O73 is divided by 1/2.

The phase comparator 75 includes frequency dividing circuits 741 and 74
2, the frequency signal fx / divided by fx / (3 × n)
The phase of (3 × n) is compared with the symbol synchronization clock φs output from the symbol synchronization detection circuit 71. The LPF 7 having the comparison output having a predetermined delay time constant
6 is fed back to the VCO 73 as a frequency control signal, whereby the oscillation frequency fx of the VCO is phase-locked to a frequency 3 × n times the symbol cycle fs.

Here, the symbol cycle fs (= 1 / T)
Assuming that s) is 6.4 kHz, the sampling clock φp (I, IB) having a frequency of 9.6 kHz, which is 3/2 times the frequency (ie, a period of 2/3 of the symbol period Ts), is supplied to the third frequency dividing circuit. 743 can be extracted from the divided output. At the same time, the sampling clock φp
A clock signal n · fp having a frequency n times as high as (I, IB)
Can be extracted from the divided output of the fourth frequency dividing circuit 744.

FIGS. 15 and 16 show the relationship between the 4FSK signal and the sampling value. Each figure shows a state in which the frequency shift state of the 4FSK signal fb input as a baseband signal changes every symbol period Ts,
The bit pattern of the binary data sampled according to each transition state is shown.

In this case, FIG. 15 shows a state of sampling performed at the rise of the normal phase clock I in the two-phase sampling clock φp (I, IB). FIG. 16 shows the two-phase sampling clock φp
In (I, IB), the state of binary sampling performed at the rising edge of the reverse phase clock IB is shown.

As described above, the baseband 4FSK signal fb is binary-sampled at a rate of three times for each symbol period Ts by sampling performed at each rising edge of the two-phase clocks I and IB which are in opposite phases to each other. You. The binary sampling result is sent to the frequency shift discriminating circuit 5 while being sequentially and parallel-converted, where it is subjected to a logic discriminating process of the frequency shift state.

FIGS. 17 and 18 show the relationship between the 2FSK signal waveform and the sampling value. Each figure shows a state in which the frequency shift state of the 2FSK signal fb input as a baseband signal changes for each symbol period,
The bit pattern of the binary data sampled according to each transition state is shown. In FIG. 17, the binary logical value of the FSK signal fb is sampled at the rising edge of the normal phase clock I, and in FIG. 18, the binary logical value of the FSK signal fb is sampled at the rising edge of the negative phase clock IB.

Also in this case, the baseband 2FSK signal fb is binary-sampled at a rate of three times for each symbol period Ts by sampling performed at each rising edge of the two-phase clocks I and IB which are in opposite phases. You. The binary sampling result is also sent to the frequency shift determination circuit 5 while being sequentially and parallel-converted, where it is subjected to a logic determination process of the frequency shift state.

FIG. 19 is a table showing the relationship between the frequency shift state and data.

As shown in the figure, the frequency shift states (+4.8 kHz, -4.8 kHz, +
(1.6 kHz, -1.6 kHz) correspond to 2-bit data ("10", "00", "01", "11"). Therefore, if the frequency shift state in each symbol period can be determined, demodulated data for each symbol period can be logically generated from the determination result.

FIG. 20 shows the relationship between sampling values and demodulated data in a truth table.

[0110] As shown in FIG.
The bit pattern (truth value) of the binary data sequence sampled in one symbol period can correspond to the combination of the symbol patterns in the two symbol periods. This makes it possible to logically generate demodulated data for each symbol period from the sample values in two successive symbol periods.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof. Needless to say.

For example, the number of times of sampling in one symbol period is not limited to six or three, but is at least two.
Any number of times equal to or more than the number of times is sufficient.

The logical processing functions such as the frequency shift discriminating circuit can be realized by program processing by a CPU (microcomputer).

In the case of program processing by the CPU, 1
Each time a sampling value is input, the state is left by a flag, a counter, or the like, so that it is not always necessary to create parallel data by a serial-parallel conversion circuit. It is possible to generate demodulated data.

In the above description, the case where the invention made by the present inventor is applied to the pager receiving apparatus, which is the background of the application, has been mainly described. However, the present invention is not limited to this.
It can also be applied to data communication systems.

[0116]

The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.

In other words, the digitization of the FSK demodulation circuit can be achieved with a simple and small-scale configuration, thereby achieving an effect of significantly reducing power consumption and cost.

Further, the data demodulation section of the FSK receiving apparatus can be digitized with a relatively small configuration, and the configuration of the analog section can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of an FSK demodulation circuit to which the technique of the present invention is applied.

FIG. 2 is an operation waveform chart of a main part of the circuit shown in FIG. 1;

FIG. 3 is a symbol pattern diagram of a 4FSK signal;

FIG. 4 is a symbol pattern diagram of a 2FSK signal.

FIG. 5 is a block diagram showing a specific configuration example of a synchronization forming circuit 7;

FIG. 6 is a block diagram showing a first embodiment of an FSK receiving apparatus to which the technology of the present invention has been applied;

7 is an operation waveform chart of a main part of the FSK receiving apparatus shown in FIG.

FIG. 8 is a waveform chart for demodulating a GMSK-modulated received signal.

FIG. 9 is a block diagram showing a second embodiment of the FSK receiving apparatus according to the present invention.

10 is an operation waveform chart of a main part of the receiving apparatus shown in FIG.

FIG. 11 is a block diagram showing a second embodiment of the FSK demodulation circuit according to the present invention.

FIG. 12 is a block diagram illustrating a configuration example of a multiphase clock generation circuit.

FIG. 13 is a waveform chart showing a polyphase clock.

FIG. 14 is a block diagram showing a specific configuration example of a synchronization forming circuit used in the demodulation circuit of FIG. 11;

FIG. 15 is a diagram showing a relationship between a 4FSK signal and its sampling value.

FIG. 16 is a diagram showing a relationship between a 4FSK signal and its sampling value.

FIG. 17 is a diagram showing the relationship between a 2FSK signal and its sampling value.

FIG. 18 is a diagram showing a relationship between a 2FSK signal and its sampling value.

FIG. 19 is a table showing a relationship between a frequency shift state and data.

FIG. 20 shows a relationship between sampling values and demodulated data in a truth table.

[Explanation of symbols]

 Reference Signs List 1 radio receiving unit 11 antenna 12 RF (high frequency) preamplifier 13 BPF (bandpass filter) 14 mixer 15 BPF 16 IF (intermediate frequency) unit 17 synchronous detection unit 18 local oscillation circuit 19 reference oscillation circuit 2 data demodulation unit 3 sampling circuit Reference Signs List 31 waveform shaping circuit 32, 33 shift register 4 serial-parallel conversion circuit 5 frequency shift discrimination circuit 6 data generation circuit 7 synchronization formation circuit 71 symbol synchronization detection circuit 72 sampling clock generation circuit 73 VCO (variable frequency oscillator) 741, 742, 743, 744 frequency divider circuit 75 phase comparator 76 LPF (low-pass filter) 81 frequency calibration control circuit 82 polyphase clock generation circuit 83 phase selection circuit 84 shift register fb, fb 'baseband FSK signal fs symbol cycle Do t frequency shift determination circuit fx VCO oscillation frequency φs symbol synchronization clock fs symbol cycle φp sampling clock fp clock signal (sampling) Ts symbol period fr radio reception signal fi IF (intermediate frequency) signal fL1 local signal fL2 detection reference signal

Claims (8)

[Claims] 1. Sampling means for sampling binary logic data of a baseband FSK signal which has been shaped into a binary pulse signal at least twice in one symbol period, and data sampled in at least two symbol periods. Frequency shift determining means for logically determining a frequency shift state for each symbol period from a logical code pattern state of a column; and data generating means for generating demodulated data based on a determination result by the frequency shift determining means. FSK demodulation circuit characterized by the following. 2. A serial / parallel conversion circuit for sequentially converting a serial data sequence on a time series sampled in one or a plurality of symbol periods into parallel data of a plurality of bits every sampling, and a logic of the parallel data. 2. The FSK demodulation circuit according to claim 1, further comprising frequency shift determining means for logically determining a frequency shift state for each symbol period from a code pattern state. 3. A symbol synchronization detecting means for logically detecting a timing of symbol switching of an FSK signal from a logical code pattern state of a sampled data sequence, and a sampling clock is supplied to the sampling means based on a detection result by the symbol synchronization detecting means. 3. The FSK demodulation circuit according to claim 1, further comprising a clock generation unit for applying the clock. 4. A serial-parallel conversion circuit for sequentially converting a serial data sequence on a time series sampled in a plurality of symbol periods into parallel data of a plurality of bits every sampling, and a logical code pattern of the parallel data FS from the state
4. The FSK demodulation circuit according to claim 1, further comprising symbol synchronization detection means for logically detecting a symbol switching timing of a K signal. 5. A symbol synchronization detecting means for logically detecting a symbol switching timing of an FSK signal, a PLL operating in synchronization with the symbol switching timing detected by the symbol synchronization detecting means, and a signal generated by the synchronous operation of the PLL. 5. The method according to claim 1, further comprising: a sampling clock generating unit configured to generate a sampling clock based on the sampling clock.
SK demodulation circuit. 6. A symbol synchronization detecting means for logically detecting a symbol switching timing of an FSK signal, a multi-phase clock generating means for generating a plurality of phases of sampling clocks based on a detection result of the symbol synchronization detecting means,
The FSK is selected from the sampling clocks of the plurality of phases.
Phase selecting means for selecting a sampling clock having a phase such that a sampling data sequence in each symbol period of a signal has a predetermined logical code pattern state according to a frequency shift state and supplying the selected sampling clock to the sampling means. The FSK demodulation circuit according to any one of claims 1 to 5. 7. A detection circuit for demodulating a baseband FSK signal waveform from an FSK-modulated radio reception signal, and a waveform for shaping the demodulated baseband FSK signal into binary pulse signals of “1” and “0”. A shaping circuit, sampling means for sampling the waveform-shaped baseband FSK signal at least twice in one symbol period, and a frequency for each symbol period from a logical code pattern state of a data sequence sampled in at least two symbol periods. An FSK receiving apparatus comprising: frequency shift determining means for logically determining a shift state; and data generating means for generating demodulated data based on a result of the determination by the frequency shift determining means. 8. A detection circuit for demodulating a FSK-modulated radio reception signal into a baseband FSK signal waveform by synchronous detection, a reference oscillation circuit for oscillating a detection reference signal for performing the synchronous detection, and a sampling means. 8. A frequency calibration control means for calibrating and controlling the oscillation frequency of the reference oscillation circuit so that the logical code pattern state of the data sequence sampled in the step (c) becomes a predetermined state. FSK receiver.