JPH11272319A - Numerical controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correct the deviation between the control period of a numerical controller and the communication period of a network when the numerical network is connected to a pulse generator for generating two-phase pulse signals and connected also to an I/O unit for counting two-phase pulse signals through the network to read out the count value of two-phase pulse signals counted by the I/O unit. SOLUTION: This numerical controller 4 is provided with a timer circuit 5 to be cleared for every communication period of the network to start counting again, they when data read out at present were latched can be known by reading out the count value of the timer circuit 5 for every control period. Consequently the deviation between the control period of the numerical controller 4 and the communication period of the network can be corrected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is connected to a pulse generator for generating a two-phase pulse signal, connected to an I / O (input / output) unit for counting the two-phase pulse signal via a network, and The present invention relates to a numerical controller configured to read a count value of a two-phase pulse signal counted by an O unit.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a conventional numerical controller. A numerical controller 4 is connected via a network 3 to an I / O unit 2 for counting two-phase pulse signals generated by a pulse transmitter 1. 2 calculated by the I / O unit 2
The count value of the phase pulse signal is read. Two-phase pulse signal PULSE1 generated by pulse transmitter 1
And PULSE2 are received by the receiver 21 of the I / O unit 2, and are synchronized by the synchronous clock CLK generated by the oscillator 26 in the clock synchronizing circuit 22, and the two-phase pulse signal is counted by the counter circuit 23 by UP or DOWN. The count value COUNT of the counter circuit 23 is latched in the latch circuit 24 by the data latch signal DLATCH transmitted from the communication circuit 25 for each communication cycle of the network 3, and the strobe signal STROBE is transmitted from the communication circuit 25.
Is transmitted, the latch circuit 24 transmits the count value to the numerical controller 4 via the network 3. The communication cycle of the network 3 is synchronized with the control cycle of the numerical controller 4, and the numerical controller 4 processes the transmitted count value as it is.

FIG. 6C shows a communication cycle of the network 3 (FIG. 5A) and a control cycle of the numerical controller 4 (FIG. 5B) in the conventional numerical controller as shown in FIG. Is a time chart in the case where synchronization is not established, and L1 (marked by ト レ ー ス) is a trace of the count value of the pulse transmitter 1 taken in each communication cycle of the network 3. L2 (x mark) is obtained by tracing the latest count value at that time for each control cycle of the numerical controller 4.

[0004]

Even if the count values of the two-phase pulse signals PULSE1 and PULSE2 of the pulse generator 1 are scanned in synchronization with the communication cycle of the network 3, the control cycle of the numerical controller 4 is synchronized. When the system is constructed by connecting the network 3 of the communication cycle
Since the communication cycle of the network 3 and the control cycle of the numerical control device 4 are not synchronized, the numerical control device 4 cannot grasp the time relationship between the read data and if the read data is used as it is, the numerical control device 4 shown in FIG. It contains a large error as indicated by the mark ● in FIG. The present invention has been made under the circumstances described above, and an object of the present invention is to provide a method in which a numerical control device is connected to a network having a communication period that is not synchronized with the control period of the numerical control device. It is an object of the present invention to provide a numerical control device capable of correcting a deviation of a communication cycle between a network and a network.

[0005]

A pulse generator for generating a two-phase pulse signal is connected to an I / O unit for counting the two-phase pulse signal via a network.
In a numerical control device for reading a count value of a two-phase pulse signal counted by the I / O unit, the object of the present invention is to provide a counter circuit that is cleared every communication cycle of the network and starts counting again. Achieved by By reading the count value of the timer circuit for each control cycle, it is possible to know how long the data read via the network has been latched before, and to know the control cycle of the numerical control device and the network communication. The deviation from the period can be corrected.

[0006]

FIG. 1 shows a numerical controller according to the present invention in correspondence with FIG. 5. The numerical controller 4 of the present invention is cleared every communication cycle of the network 3 and counts again. It has a timer circuit 5 which starts and reads a count value every control cycle of the numerical controller.

FIG. 2 is a circuit diagram showing an example of the timer circuit 5. The communication cycle of the network 3 is input as a clear signal to the binary counter 51 with synchronous clear through the inverter 53, and the clock TCLK generated by the oscillator 52 is input as the count-up clock CLK.
Outputs QA, QB, Q of binary counter 51 with synchronous clear
Both C and QD are 8-bit D-flip-flops 54
And latched by the control cycle CLK. In the example of FIG. 2, the binary counter 51 with synchronization clear is described, but another counter IC may be used or a flip-flop may be used.

FIG. 3 is a time chart showing an example of the operation of the timer circuit 5. When the communication cycle goes high at time t1 (FIG. 3A) and the clock TCLK rises (FIG. 3B), the synchronization is started. The outputs QA, QB, QC and QD of the binary counter 51 with clear are cleared and become low level (FIGS. (C) to (F)). Then, when the communication cycle becomes low level at time t2 and the clock TCLK rises, the binary counter 51 with synchronous clear starts counting. Further, when the control cycle changes from the low level to the high level at time t3 (FIG. 3 (G)), the 8-bit D-flip-flop 54 latches the outputs QA, QB, QC, and QD of the binary counter 51 with synchronous clear. ((H) ~
(K)), the numerical controller 4 reads the outputs 1Q, 2Q, 3Q, and 4Q of the 8-bit D-flip-flop 54. The control cycle of the numerical controller 4 and the outputs 1Q, 2Q, 3Q,
4Q and the period of the clock TCLK, the pulse generator 1
Can be calculated when the count value is latched.
At the time point t4, the communication cycle becomes high level (FIG. 3
(A)), when the clock TCLK rises ((B) in the figure), the output Q of the binary counter 51 with synchronous clear is output.
A, QB, QC and QD are cleared to low level (FIGS. (C) to (F)). When the communication cycle becomes low level at time t5 and the clock TCLK rises, the binary counter with synchronization clear 51 starts counting. The above operation is repeated. The outputs 1Q, 2Q, 3Q, and 4Q of the 8-bit D-flip-flop 54 are all cleared by the power-on reset signal RESET-N after the power is turned on, and are at the low level.

FIG. 4C is a time chart showing a method of correcting a synchronization shift by the numerical controller 4 of the present invention.
L1 (solid line indicated by ○) is obtained by tracing the count value of. L3 (broken line indicated by ●) is a trace of the command value corrected by the numerical controller 4 of the present invention.
The correction command value of the count value of the pulse transmitter 1 at the timing ta of the control cycle in FIG. 4B is a count value obtained before and after the count value of the timing ta-3 of the control cycle three cycles before the timing ta. The estimated count value obtained by calculation is used. The estimated count value xt at the timing ta-3 of the control cycle is obtained from the following equation 1 from the count values x1 and x2 taken before and after the timing ta-3.

Xt = x1 + (x2-x1) × t1 / T where T is the communication cycle of the network 3 (FIG. 4).
(A)), t1 is the timer circuit 5 in the numerical controller 4
Is the time from the trigger of the immediately preceding communication cycle counted by (see FIG. 4B). This estimated count value is used as a command value at the timing ta of the control cycle. Here, the estimated count value three cycles before is used as the correction command value, but it is not specified how many cycles before the one to use. When this correction method is used, the correction command value includes a delay with respect to the actual count value. However, since the control cycle of the numerical controller is sufficiently short, there is no problem.

[0010]

As described above, according to the numerical controller of the present invention, even if the system is constructed by connecting to a network which is not synchronized with the control cycle of the numerical controller, the numerical controller has just read the data. It is possible to know how long the data was previously latched, and to correct the difference between the control cycle of the numerical controller and the communication cycle of the network.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a numerical control device according to the present invention.

FIG. 2 is a circuit diagram showing an example of a timer circuit according to the present invention.

FIG. 3 is a time chart showing an operation example of the timer circuit according to the present invention.

FIG. 4 is a time chart showing a method of correcting a synchronization shift by the numerical controller according to the present invention.

FIG. 5 is a block diagram illustrating an example of a conventional numerical control device.

FIG. 6 is a time chart showing an operation example of a conventional numerical control device when the control cycle of the numerical control device and the communication cycle of the network are not synchronized.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Pulse transmitter 2 I / O unit 21 Receiver 22 Clock synchronization circuit 23 Counter circuit 24 Latch circuit 25 Communication circuit 26 Oscillator 3 Network 4 Numerical controller 5 Timer circuit 51 Binary counter with synchronous clear 52 Oscillator 53 Inverter 54 8-bit D -Flip-flops

Claims (2)

[Claims] 1. A two-phase pulse signal generator connected to a pulse generator for generating a two-phase pulse signal, connected to an I / O unit for counting the two-phase pulse signal via a network, and the two phases counted by the I / O unit. A numerical control device for reading a count value of a pulse signal, comprising a timer circuit that is cleared every communication cycle of the network and starts counting again. 2. The numerical control device according to claim 1, wherein a count value of said timer circuit is read every control cycle, and a difference between said control cycle and a communication cycle of said network is corrected.