JPH11271792A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a wiring structure which has superior thermal oxidation resistance by forming a metal wire of a 1st layer of Nb or alloy principally comprising Nb and a 2nd layer of nitrides of Nb or nitrides of alloy principally comprising Nb. SOLUTION: A TFT 101 has a channel area 105 formed of an intrinsic polycrystalline Si film and a gate insulator 106 formed on the channel area 105. The TFT 101 is constituted of a laminate type gate electrode 201 comprising a laminate film of the 1st layer 107 of Nb or alloy principally comprising Nb and the 2nd layer 108 of the nitrified film of the 1st layer, and a drain electrode 111 and a source electrode 112 connected through a through hole to an active layer 109 formed by doping the drain-source area of the intrinsic polycrystalline Si film 105 with impurities. When there is no problem of the resistance of the metal wire, the thermal oxidation resistance can be improved as well even when the TFT is composed of a single nitride layer of nitrides of Nb or alloy principally comprising Nb while the 1st layer is omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an electrode wiring of a liquid crystal display.

[0002]

2. Description of the Related Art Japanese Patent Laid-Open No.
Japanese Patent Application Laid-Open No. 3-182723 describes that a Poly-Si film having a high concentration of impurities and an Al (aluminum) film are stacked as a gate wiring.

As a wiring material for a liquid crystal display device, Japanese Patent Application Laid-Open No. 5-55575 discloses an alloy of Ta (tantalum) and Nb having a low resistance value and chemical resistance, a metal material containing Nb or Nb as a main component. Is described.

In Japanese Patent Application Laid-Open No. 2-106723, as a wiring material for a gate line, a material laminated in the order of Nb and Ta from the substrate side is used, the surface is oxidized by anodic oxidation, and then SiO ₂ (silicon oxide) or A TFT in which a gate insulating film made of SiN (silicon nitride) is laminated is proposed. According to this document, it is described that the resistance value can be reduced as compared with the case where a Ta single layer film is used, and it is effective in preventing a short circuit between a gate line and a drain line.

Japanese Patent Application No. 7-147852 proposes to use Nb for all or at least one of the gate and drain electrodes. According to this, a two-layer film made of an alloy or a different metal material is used. It is described that since there is no electrode structure, the throughput is improved, and an electrode structure with low resistance, low stress and easy dry etching can be realized.

[0006]

However, since the melting point (660.4 ° C.) of the Al film is low in the wiring of the conventional liquid crystal display device, particularly in the gate electrode using Al, the hillock is formed by the heat treatment at the time of forming the interlayer insulating film. And whiskers were generated, and because of the low thermal oxidation resistance of Al, the drive waveform was rounded due to an increase in the resistance of the wiring and a short circuit between the wirings occurred.

In addition, since the Al film is usually patterned by wet etching, it is difficult to control the shape of the end portion. This may cause a short circuit or a disconnection of the drain.

It is an object of the present invention to provide a liquid crystal display device to which a wiring structure having excellent thermal oxidation resistance is applied.

[0009]

In a liquid crystal display device having a metal wiring, the metal wiring is made of a first layer made of Nb or an alloy containing Nb as a main component and a nitride of Nb or Nb as a main component. It is composed of a nitride of an alloy to be formed. With this configuration, the thermal oxidation resistance of the metal wiring can be improved. If the resistance of the metal wiring does not matter, the metal wiring may be formed by omitting the first layer made of Nb or an alloy containing Nb as a main component and omitting nitride of Nb or an alloy containing Nb as a main component. Even in the case of a single-layer structure, the thermal oxidation resistance can be similarly improved.

Further, when a third layer composed of a nitride of Nb or a nitride of an alloy containing Nb as a main component is formed under the first layer, a direct connection between the first layer and another member can be obtained. Contact can be avoided. Nb nitride or nitride of an alloy containing Nb as a main component is particularly compatible with the insulating film, so that disconnection of the first layer, increase in resistance, and the like can be prevented. Even if a silicon oxide film is formed on these wirings, the wirings are not thermally oxidized, so that a higher effect can be obtained.

Further, if the first layer and the second layer, preferably the third layer, are collectively etched with the same pattern, the number of process steps can be reduced. The end of the wiring may be formed in a forward tapered shape.

In another configuration, the semiconductor device includes a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates. The pair of substrates has a plurality of gate electrode wirings, and the plurality of gate electrode wirings intersect with the plurality of gate electrode wirings. A liquid crystal display having a plurality of drain electrode wirings formed so as to form, a plurality of thin film transistors formed corresponding to intersections of these wirings, and a plurality of source electrodes formed corresponding to the plurality of thin film transistors When the device has a plurality of gate electrode wirings, drain electrode wirings, source electrodes, a common electrode, and a common electrode wiring, at least one of the common electrode and the common electrode wiring is made of Nb or an alloy containing Nb as a main component. First
And a second layer made of nitride of Nb or an alloy containing Nb as a main component, the thermal oxidation resistance is also improved. Especially effective. When the wiring resistance is not a problem, the first layer made of Nb or an alloy containing Nb as a main component is omitted, and these electrodes or electrode wires are made of nitride of Nb or an alloy containing Nb as a main component. Even if it is composed only of the second layer made of a material, the thermal oxidation resistance can be similarly improved.

[0013] Also for these structures, it is desirable to form a third layer made of a nitride of Nb or a nitride of an alloy containing Nb as a main component under the first layer.

[0014] When an insulating film composed of a silicon oxide film is formed on a wiring composed of a laminated film having a first layer and a second layer, the effect is further clarified.

When the electrode structure of the present invention is used for a gate electrode wiring, it is preferable that the silicon oxide film is formed so as to be at least a part of the gate insulating film of the thin film transistor.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 14 is a plan view of a unit pixel of a liquid crystal display device according to a comparative example constituted by using a coplanar type TFT. FIGS. 15, 16, and 17 correspond to FIG.
It is sectional drawing which follows the line shown by middle xx ', yy', and zz '.

The liquid crystal display device has a gate electrode wiring 202 formed on a glass substrate 103 provided with a base film 104, and a drain electrode wiring 203 formed so as to cross the gate electrode wiring 202.
And a TFT 101 formed near the intersection corresponding to the intersection of these electrode wirings, and a pixel display area 102.

As shown in FIG. 15, the TFT 101 has a channel region 105 made of an intrinsic polycrystalline Si film,
05, a first gate electrode 1401 made of a polycrystalline Si film doped with impurities formed on the gate insulating film 106, and a second gate electrode made of Al (aluminum) 201 and an active layer 109 in which the drain / source region of the channel region 105 made of the intrinsic polycrystalline Si film is doped with impurities.
, A drain electrode 11 connected through a through hole
1 and a source electrode 112. A pixel electrode 113 is connected to a source electrode 112 of the TFT. 1501 and 110 are interlayer insulating films, and 114 is a protective insulating film.

Focusing on the gate electrode of the TFT 101, FIG.
As shown in the above, the first gate electrode 1401 made of polycrystalline Si and the second gate electrode 201 made of Al
It can be seen that this is a two-layer gate electrode structure connected through a through hole TH opened in the interlayer insulating film 1501.

The extended portion of the second gate electrode 201 made of Al in the two-layer electrode structure becomes the gate electrode wiring 202 as it is. As shown in FIG. 17, a gate electrode wiring 202 and a drain electrode wiring 203 made of Al
Has a structure in which an intersecting portion is formed with the interlayer insulating film 110 interposed therebetween.

FIG. 18 is a cross-sectional view showing a gate electrode wiring forming step for each step in the comparative example shown in FIGS. The subject of the present invention will be described in more detail with reference to this sectional view.

First, as shown in FIG.
An island pattern 401 made of an intrinsic polycrystalline Si film is formed on a glass substrate 103 with a mark. Usually, an amorphous Si film formed by a CVD method or the like is polycrystallized by a method such as thermal annealing or laser annealing.

Next, as shown in FIG. 18B, a gate insulating film 106 is formed on the entire surface of the substrate, and an amorphous Si film 18 to be a first gate electrode 1401 after polycrystallization in a step described later.
01 is formed. As the gate insulating film 106, an SiO ₂ film, a SiN film, or the like formed by a normal CVD method is used.

Next, as shown in FIG. 18C, the gate insulating film 106 and the amorphous Si film 1801 are collectively etched in the same pattern. When such a process is adopted, the first gate electrode needs to be formed of an electrode wiring material that can be easily dry-etched with the gate insulating film 106 at a time.

Next, as shown in FIG. 18D, the entire surface of the substrate is doped with phosphorus ions as an n-type dopant. At this time, the gate insulating film 106 and the amorphous Si film 180
The channel pattern 105 made of the intrinsic polycrystalline Si film is formed in a self-aligned manner with the one stacked pattern serving as a mask.

Further, the P-type TFT portion of the peripheral circuit portion is selectively doped with boron ions as a P-type dopant using a photoresist or the like as a mask. For doping of phosphorus and boron, an ion implantation method or an ion doping method is used.

Next, as shown in FIG. 18E, the doped impurity ions are activated by activation annealing to form a first gate electrode 1401 made of a polycrystalline Si film.
Then, an active layer 109 to be a drain / source region is formed. For the activation annealing at this time, techniques such as thermal annealing and laser annealing are used. The temperature of thermal annealing is usually 600 ° C. or higher, and in the case of laser annealing, Si
The surface temperature of the film reaches about 1000 ° C. Therefore, the first gate electrode is required to have heat resistance to these activation annealing steps. For example, Al, which is usually used as an electrode wiring material, cannot be used because it is a low melting point metal as described above. In addition, a film having a low stress is also required due to thermal distortion. Although Cr (chromium) is a high melting point metal (melting point: 1860 ° C.), cracks occur in the electrode after activation annealing due to high film stress, and cannot be used.

Here, although the first gate electrode 1401 made of polycrystalline Si is doped, it has a higher resistance than metal, and therefore cannot be used as the gate electrode wiring 202 for routing in the display device. . Therefore, a second gate electrode wiring made of a low-resistance metal connected to the first gate electrode 1401 made of polycrystalline Si is required.

However, at this stage where the TFT is exposed (FIG. 1)
8 (e)), if the gate electrode 201 made of an Al film is formed as the second gate electrode wiring, the TFT will be contaminated, and the TFT will shift in threshold voltage and increase in off current.
It causes characteristic failure.

Then, as shown in FIG. 18F, an interlayer insulating film 1501 is formed on the entire surface of the substrate. Interlayer insulating film 15
Reference numeral 01 denotes a protective film for preventing contact between the TFT and the gate electrode 201 made of an Al film serving as a second gate electrode wiring. An SiO ₂ film, a SiN film, or the like formed by a normal CVD method is used. Also, although not shown in FIG.
On the gate wiring 202, another interlayer insulating film 110 is formed in the same manner as the interlayer insulating film 1501. These insulating films are formed at a high temperature of 200 to 400 ° C. by a plasma CVD method. Therefore, there is a problem that the surface of the Al film is easily oxidized.

The first and second gate electrode wirings are made of Al
Instead of this, an attempt was made to apply a high melting point metal Nb (melting point: 2470 ° C.) described in JP-A-7-147852, which is an electrode wiring material having low resistance, low stress and easy dry etching. Although the resistance immediately after the formation of the Nb film was low, an insulation film was formed after this film was formed, and then when the wiring resistance was actually measured, the resistance increased. The reason is that an insulating film made of a SiO ₂ film or a SiN film is formed on a wiring made of an Nb film at a high temperature of 200 to 400 ° C. by a plasma CVD method, so that the surface of the Nb film is oxidized,
This is because high-resistance niobium oxide is formed. In particular, when the SiO ₂ film was used, the resistance increased because the surface of the Nb film was exposed to a strong oxidizing plasma atmosphere.

FIG. 1 shows an example of an increase in resistance due to thermal oxidation.
FIG. 9 shows a change in the resistance of the Nb film when the heat treatment was performed while changing the heat treatment temperature (the horizontal axis in the figure). The ratio of the increase in resistance of the Nb film when heat treatment is performed in the air at each temperature for 1 h in the atmosphere (vertical axis in the figure) is shown by the ratio of the resistance before heat treatment to the resistance after heat treatment. The resistance of the Nb film is 180 ° C
It can be seen that the temperature starts to rise from the vicinity and rapidly increases when the temperature exceeds 250 ° C. The rate of increase in resistance at 300 ° C is about 2.5
It can be seen that at 350 ° C., it becomes 4.5 times. This rate of increase in resistance coincides with the tendency of the increase in resistance of the Nb electrode wiring observed when a TFT element is actually formed. Increasing the resistance of the wiring of the liquid crystal display device is a serious problem, and such an increase in the resistance of the electrode wiring is particularly fatal in an active matrix type liquid crystal display device.
Unless any measures are taken to improve the thermal oxidation resistance of the Nb film,
It is difficult to realize wiring using Nb and a metal material containing Nb as a main component. As a method of forming an insulating film for a TFT, there is a method of applying an inorganic polymer such as perhydropolysilazane, which is soluble in an organic solvent, to a substrate by spin coating to form an SiO ₂ film, in addition to the plasma CVD method. Also in the coating method, a baking step of the coating film is indispensable for improving the film characteristics, and similarly, an improvement in the thermal oxidation resistance of the electrode wiring is required.

Referring to FIGS. 20 to 27, Nb or Nb
The structure and effect of a laminated film structure of a first layer made of a compound mainly containing Nb and a second layer made of Nb or a nitride of an alloy mainly containing Nb will be described in principle.

Hereinafter, "Nb or an alloy containing Nb as a main component" is referred to as "Nb-based", and "nitride of Nb or an alloy containing Nb as a main component" is referred to as "NbN-based". In some cases, boundaries are indicated by separating them with “/”.
The first layer (lower layer) is Nb-based, and the second layer (upper layer) is Nb-based.
In the case of an N-based laminated film structure, Nb-based / NbN
It is described as a system laminated film.

FIG. 20 shows that the surface of the Nb film is plasma-nitrided to form a nitrided Nb film and an Nb film.
5 shows a change in resistance when an O ₂ film is formed.

Here, the Nb film is formed by DC magnetron sputtering at a substrate temperature of 130 ° C., an Ar gas flow rate of 60 sccm, a power of 2100 W, and a pressure of 0.2 Pa.
To form a film having a thickness of 200 nm. It was confirmed that the stress of the Nb film formed under these conditions was almost zero.
The Nb film surface was N ₂ gas 200 sccm, power 500 W,
Plasma nitriding was performed at a pressure of 27 Pa. The evaluation was performed by changing the plasma nitriding time. SiO ₂ film is RF plasma CV
Using method D, the substrate temperature was 330 ° C., and the flow rate ratio of TEOS (tetraethoxysilane): O ₂ gas was 15: 3000 sc.
cm, power 1000 W, pressure 133 Pa, film thickness 3
00 nm was formed. This is because in the TFT process,
This corresponds to the SiO ₂ film forming conditions usually used.

The horizontal axis of FIG. 20 is a plasma nitriding treatment (nitrog
en plasma treatment), and the longer the treatment time, the thicker the NbN film formed on the surface. The value at processing time 0 indicates the rate of increase in resistance of the Nb single layer film. The vertical axis in FIG. 20 indicates the rate of increase in resistance as as depo.
It is shown by the ratio of the resistance at the time of the formation and the resistance after forming the SiO ₂ film. The surface of the Nb film is exposed to a strong oxidizing plasma atmosphere at 330 ° C. at the time of SiO ₂ film formation, so that about 2.5
While the resistance is doubled, the processing time is 30mi
It can be seen that the resistance increase is hardly recognized in the film of n. This indicates that the adoption of the Nb-based / NbN-based laminated film structure has greatly improved the thermal oxidation resistance as compared with the Nb-based single-layer film. This makes it possible to form an SiO ₂ film as an interlayer insulating film in a strong oxidizing plasma atmosphere without causing an increase in resistance. The obtained Nb-based / NbN-based laminated film had a high melting point and a low stress similarly to the Nb-based single-layer film. Therefore, hillocks and whiskers as seen in the Al electrode wiring are not generated.
In the case where the SiO ₂ film was formed by the coating method, the effect of improving the thermal oxidation resistance was similarly observed. Specifically, for example, perhydropolysilazane diluted with cyclohexane is applied by spin coating to form an Nb-based / NbN film even after baking in air at 400 ° C. for 1 hour.
It was confirmed that no increase in the resistance of the system laminated film was observed.

FIG. 23 shows the upper NbN-based film thickness.
As described later, the effect of improving the thermal oxidation resistance was observed at 5 nm or more, but the effect tends to increase as the film thickness increases. However, since the specific resistance of the NbN-based film is larger than that of the Nb-based film, making the NbN-based film too thick undesirably increases the resistance of the Nb-based / NbN-based stacked wiring. The thickness of the NbN-based film is 5
The range is preferably from 100 nm to 100 nm. Conversely, if the wiring resistance does not matter at the specific resistance level of the NbN-based film, the underlying Nb-based film is omitted and the NbN-based film is omitted.
The wiring can also be constituted by a system single-layer film.

The specific resistance of the lower Nb-based film is 20 μm.
Ωcm or less is appropriate. Since the Nb-based film having a higher resistance than this value already contains a large amount of oxygen in the film itself at the stage of film formation, the effect of the Nb-based / NbN-based laminated film is difficult to obtain.

As an application of the above-mentioned Nb-based / NbN-based laminated film, as shown in FIGS. 28 and 29, the wiring formed on the insulating film is made of Nb nitride or an alloy containing Nb as a main component. The third layer 150 made of nitride, the first layer 107 made of Nb or an alloy mainly containing Nb, the second layer 108 made of nitride of Nb or nitride of an alloy mainly containing Nb are used. There is a structure composed of laminated films that are sequentially laminated.
As described above, since the Nb-based film is not in direct contact with the insulating film but is interposed through the NbN-based film, the quality of the Nb film is not deteriorated by oxygen diffusion from the insulating film. Also, N
By adding the bN-based film to the lower layer, the adhesion between the Nb-based / NbN-based laminated film and the insulating film can be improved.

As with the thickness of the upper NbN-based film, the thickness of the lower NbN-based film is suitably in the range of 5 to 100 nm.

As a method of forming the Nb-based / NbN-based laminated film, a method of devising a sputtering apparatus such as using a multi-chamber single-wafer sputtering apparatus can be applied in addition to the above-described means of nitriding the surface of the Nb-based film. is there. According to this method, an Nb-based / NbN-based laminated film can be continuously formed,
An increase in steps due to the formation of an NbN-based film can be suppressed.
As another method of forming the Nb-based / NbN-based laminated film, in addition to the above, for example, sputtering is performed on a Nb-based film formed by a sputtering method using an Nb-based target, using a target made of Nb-based nitride. NbN formed by the method
A Nb-based film formed by a reactive sputtering method in which N ₂ (nitrogen) is added to a sputtering gas using an Nb-based target may be formed. Alternatively, the NbN-based film may be formed by performing surface annealing on the Nb-based film by laser annealing in a nitrogen atmosphere. In any case, similarly, Nb / NbN
The system stack film can be formed continuously, and an increase in the number of steps can be suppressed. In addition, not only the Nb film but also a material containing Nb as a main component can form a nitride by the same means.
Needless to say, the same thermal oxidation resistance can be obtained. FIG. 23 shows a change in resistance of the Nb-based / Nb-based laminated film formed by the reactive sputtering method shown in FIGS. 21 and 22 when the heat treatment was performed while changing the heat treatment temperature (horizontal axis in FIG. 23: unit ° C.). 23 vertical axis: ratio of resistance value after heat treatment divided by resistance value before heat treatment as a rate of increase in resistance). The parameter is the thickness of the upper NbN layer. That is,
The ◇ line indicates that the thickness of the upper layer NbN is 0 nm,
This is the case where there is no bN film. The line with a circle indicates the case where the thickness of the upper layer NbN is 5 nm. The line of Δ indicates the case where the film thickness of the upper layer NbN is 20 nm. The □ line indicates the case where the thickness of the upper NbN layer is 40 nm. From FIG. 23, it can be seen that by laminating an NbN film having a thickness of 5 nm or more on the Nb film, sufficient thermal oxidation resistance can be ensured even at a heat treatment at 400 ° C. The thermal oxidation resistance tends to improve as the film thickness of NbN increases, but the degree of the effect is moderate.
Considering the resistance of the NbN-based film itself, as described above,
The NbN-based film thickness applied to the Nb-based / NbN-based stacked wiring is desirably 5 nm or more and 100 nm or less.

FIG. 21 shows a method for forming an NbN-based film.
An example of an NbN-based film obtained by using a reactive sputtering method in which N ₂ is added to a sputtering gas will be described.
The abscissa in FIG. 21 indicates that the sputtering gas Ar is N _2.
This is the N ₂ / (Ar + N ₂ ) flow rate ratio when the gas is added. The vertical axis in FIG. 21 is the specific resistance (Ωcm) of the formed film. Substrate temperature is 130 ℃, total gas flow is 60scc
m, the power is 2100 W, and the pressure is 0.5 Pa. For the formation of the Nb-based / NbN-based laminated film which contributes to the improvement of the thermal oxidation resistance, the N ₂ addition amount is 0.05 in the flow rate ratio of N ₂ / (Ar + N ₂ ).
~ 0.25, 100 ~ 200μΩc in specific resistance of NbN based film
An NbN-based film in the range of m (the range indicated by (b) in FIG. 21) was suitable. At this time, no N _{2 was} added (flow ratio =
The specific resistance of the Nb-based film obtained in 0) was 18 μΩcm.

Next, the structure of the film at each point shown in FIG.
It was examined by a line diffraction method. As a result, it was found that the three regions shown in (a), (b), and (c) have different structures. FIG. 22 shows three regions (a) and (b) shown in FIG.
X of the Nb nitride film (NbN film) selected from (b) and (c)
1 shows a line diffraction spectrum (representative example). The vertical axis is the X-ray diffraction intensity, and the unit is arbitrary units (au.). In FIG. 22, the symbol ● indicates a cubic Nb, the symbol ○ indicates a crystal peak from cubic NbN, and the black triangle indicates an amorphous peak from a base glass substrate. Fig. 21 (a)
<0.05 at the indicated range _{(N 2 / (Ar + N} 2) flow rate ratio
, The film obtained in <range 100Myuomegacm) at resistivity of NbN film, by adding a lack of N _2, Nb single-phase or N
It was found that the state was a mixed crystal of bN and Nb.

On the other hand, Nb shown in FIG.
Range for forming a Ni / NbN stacked film, that is, (N ₂
It can be seen that the film obtained at a flow rate ratio of 0.05 to 0.25 (Ar + N ₂ ) and a specific resistance of the NbN film in the range of 100 to 200 μΩcm) is composed only of NbN having high crystallinity. The range shown in FIG. 21C, that is, (N ₂ /
(Ar + N ₂ ) flow rate ratio> 0.25, specific resistance of NbN-based film in the range of> 200 μΩcm), although the film is composed of only NbN, the crystal peak due to excessive addition of N ₂ Was small and the film was low in crystallinity. These differences in film quality can be presumed to be the cause of the difference in the effect of improving the thermal oxidation resistance when forming the Nb-based / NbN-based laminated film.

When a laminated film is used for a gate electrode wiring, it is desirable that the laminated wiring can be etched at a time without increasing the number of steps. Therefore, Nb / NbN
Also in the case of using a multi-layered film, it is desirable that the Nb-based / NbN-based laminated film can be dry-etched at once. As will be described later with reference to FIGS. 6 to 9, a through hole for forming a contact is formed in the interlayer insulating film 110 on the gate electrode 201 in the TFT portion forming the CMOS inverter and the terminal portion of the active matrix. There is a need to. Therefore, the condition is that the interlayer insulating film 110 can be selectively etched on the Nb-based / NbN-based laminated film. As described above, the interlayer insulating film 110 is made of SiO.
_Two films or SiN films are used.

FIG. 24 shows Nb and Nb when etched using a typical SF ₆ gas as an F-based etching gas.
The evaluation results of the etching rates of the N film, the SiO ₂ film, the SiN film, and the resist film are shown. The horizontal axis of FIG. 24 indicates the etching time (second), and the vertical axis of FIG. 24 indicates the etched film thickness (nm). The Nb film, NbN film and SiO ₂ film were formed by the method shown in FIGS. SiN
The film is formed by RF plasma CVD and the substrate temperature is 230
° C, SiH ₄ (monosilane): NH ₃ (ammonia): N ₂ gas flow ratio = 20: 60: 200 sccm, power 175
W and pressure were formed at 80 Pa. A commercially available positive resist was used as the resist. The etching conditions were set at 5 power using an RF parallel plate type reactive ion etching apparatus.
00W, pressure 27 Pa, SF ₆ gas flow rate 88 sccm. The etching rate can be obtained from the inclination of the etching film thickness with respect to the etching time shown in FIG. The etching rate is as follows: SiO ₂ (0.2 nm / s) << resist (1.2 nm / s) <Nb-based (1.7 nm / s) <
It can be seen that NbN-based (3.0 nm / s) <SiN (4.2 nm / s) increases in this order. Thus, it is understood that the batch etching of the Nb-based / NbN-based stacked film can be performed by using the F-based etching gas.

However, when the SiO ₂ film is used as the interlayer insulating film, the etching rate of the SiO ₂ film is NbN.
Since the etching rate is lower than that of the Nb-based and Nb-based films, it is understood that the Nb-based / NbN-based laminated film, which is the gate electrode wiring, is damaged at the time of forming the through hole.
In this regard, selective etching of the SiO ₂ film becomes possible by using CHF ₃ described below instead of SF ₆ as an etching gas. On the other hand, the etching rate of the SiN film is larger than the etching rates of the NbN-based film and the Nb-based film, but the selectivity, which is the etching rate ratio, is at most 1.4 with respect to the NbN-based film. It turns out that it is actually difficult to selectively etch the SiN film without damaging the Nb-based / NbN-based laminated film.

This indicates that it is difficult to use the SiN film as the interlayer insulating film. As described above, instead of SF ₆ gas which is a typical F-based etching gas, C
Similar results were obtained when a gas obtained by adding O ₂ to F ₄ or CF ₄ was used.

Next, FIG. 25 shows Nb-based, NbN-based and Sb-based.
The results obtained by etching the iO ₂ film with CHF ₃ gas are shown. The horizontal axis in FIG. 25 is the etching time (min).
The vertical axis in FIG. 25 indicates the etched film thickness (n
m). RF parallel plate type reactive ion etching equipment, power 550 W, pressure 6.7 Pa, C
The HF ₃ gas flow rate was 55 sccm. From this figure, SiO ₂
For a film etching rate of 23 nm / min, N
It can be seen that the b-based and NbN-based films are hardly etched. This is because CHF ₃ is a gas having a high deposition property. That is, in the etching using the CHF ₃ gas, a C—F compound is formed together with the generation of the F radical contributing to the etching in the plasma, and this is deposited on the surface of the Nb-based or NbN-based film.
The etching stops on the bN-based film.
Meanwhile, on the SiO ₂ film, because oxygen is supplied from the SiO ₂ film, etching of the SiO ₂ film progresses constantly by oxidative decomposition of C-F compounds without causing deposition of C-F compounds. Therefore, by using the CHF ₃ gas, the SiO ₂ film on the Nb-based / NbN-based laminated film can be selectively etched. From the above restrictions on the dry etching process, it is understood that an SiO ₂ film is suitable for the interlayer insulating film 110 on the gate electrode wiring 201.

FIG. 26 is a view showing the state of N using the gas shown in FIG.
FIG. 4 is a schematic cross-sectional view of an edge of an etching pattern when a b-based / NbN-based laminated film is etched. In FIG. 26, reference numeral 103 denotes a glass substrate, Nb, or a first layer 107 made of an alloy containing Nb as a main component, an Nb-based film, a nitride of Nb, and a second layer made of a nitride of an alloy containing Nb as a main component. Layer 10 of
An NbN-based film is used as 8, and 2401 denotes a resist pattern. As shown in FIG. 26A, the NbN-based film 10
In No. 8, it is considered that the etching proceeds isotropically in the thickness direction and the lateral direction of the film. Here, as described in FIG.
The etching rate a of the upper NbN-based film 108 in the b-based / NbN-based laminated film was about twice the etching rate b of the Nb-based film 107 (a> b). Therefore, FIG.
And (c), the etching rate in the film thickness direction is:
As soon as the etching has progressed to the Nb-based film side past the Nb-based / NbN-based interface, it becomes smaller. On the other hand, the etching rate in the lateral direction of the film is still governed by the etching rate a of the NbN-based film. Finally, as shown in FIG. 26 (d), the etched end is processed into a tapered shape having different angles across the Nb-based / NbN-based interface.
At this time, the relationship between the angle α formed by the upper NbN-based film and the angle β formed by the lower Nb-based film is α> β. Actual Nb system / Nb
In the etching of the N-based laminated film, the etching rate in the lateral direction of the film was not isotropic etching but tended to be slightly higher in the lateral direction of the film than in the film thickness direction. ) Is etched to a shape substantially similar to the tapered shape shown in FIG.
It could be confirmed by EM observation. Such a tapered shape can secure good surrounding characteristics of the drain electrode wiring 203 via the interlayer insulating film 110 and the inter-layer insulating film when actually applied to the gate electrode wiring, and can short-circuit between the wirings and disconnection of the drain. Failure can be prevented. That is, the wiring end shape shown in FIG. 26 is a characteristic that is indispensable as a gate electrode wiring.

As described later with reference to FIGS. 6 to 9, the complementary type (C
MOS) In the TFT part forming the inverter,
It is necessary to form a through-hole contact between the Nb-based / NbN-based laminated film serving as the gate electrode wiring and the drain wiring material.

FIG. 27 shows an Nb-based / NbN-based laminated film, a Cr film commonly used as a drain wiring electrode material, and an alloy film of Cr and Mo (hereinafter referred to as CrMo) as an example of a Cr alloy film.
) Is shown. The contact area (μ
m ² ), and the vertical axis in FIG. 27 shows the contact resistance (Ω · μm
² ) is shown. The Cr film is formed by DC magnetron sputtering at a substrate temperature of 200 ° C. and an Ar gas flow rate of 60 sc.
cm, power 4000 W, pressure 0.2 Pa. The CrMo film has a weight ratio of Cr to Mo of 50:50.
Was formed under the same conditions as those for the Cr film. In FIG. 27, the mark ○ indicates the Nb-based / NbN-based laminated film and Cr, and the mark が indicates the Nb-based / NbN-based laminated film and CrMo.
It is a measurement result in the case of. From the driving conditions of the peripheral circuit and the pixel TFT, 10 ⁶
It is required to suppress the resistance to Ωμm ² or less. From FIG. 27, it can be seen that in any combination of the Nb-based / NbN-based laminated film and Cr, and the Nb-based / NbN-based laminated film and CrMo, the obtained contact resistance is a contact area of 25 to 400 μm.
It can be seen that it is 10 ² Ωμm ² in the range of m ² . This is a value four orders of magnitude lower than the target, and it can be seen that the specification is sufficiently satisfied. Therefore, it is concluded that good contact characteristics can be ensured by using an Nb-based / NbN-based laminated film for the gate electrode wiring and a Cr and / or Cr alloy film for the drain electrode wiring material. The contact characteristics are such that at least a part of the drain electrode wiring or the source electrode wiring which is in contact with the gate electrode wiring made of the Nb-based / NbN-based laminated film is formed of chromium or an alloy film of chromium and molybdenum. You can get it. Accordingly, if this condition is satisfied, as an application example of the drain electrode wiring or the source electrode wiring, a laminated film of chromium or an alloy film of chromium and molybdenum and another metal film, for example, aluminum which is a low-resistance metal film It is also possible to use a laminated film with a divalent alloy film.

Since the wiring structure according to the present invention is excellent in thermal oxidation resistance, if the wiring is a process that is exposed to a high-temperature oxidizing atmosphere, it has a drain electrode wiring, a source electrode wiring, a common electrode, and a common electrode wiring. In such a case, the effect is exhibited even when used for a common electrode, a common electrode wiring, and the like. In particular, an example in which the present invention is applied to a gate electrode wiring of a TFT substrate will be described below.

FIG. 2 is a plan view of a unit pixel of a liquid crystal display device using a coplanar TFT according to the present invention, and FIGS. 1 and 3 are shown by xx 'and yy' in FIG. 2, respectively. It is sectional drawing which follows the sagging line.

The basic structure of the unit pixel of the liquid crystal display device is similar to that of the comparative example shown in FIG. 14, and is formed so as to cross the gate electrode wiring 202 formed on the glass substrate 103 with the base film 104. Drain electrode wiring 203
And TFT101 formed near the intersection of these electrode wires
And a pixel display area 102. The difference from the comparative example is that the first gate electrode 1401 made of polycrystalline Si
In the present invention, instead of the two-layer gate electrode structure of the second gate electrode 201 made of Al and Al, the first layer 107 made of Nb or an alloy containing Nb as a main component and the nitride film of the first layer are used. (Nb-based / Nb)
(N-based).

Therefore, as shown in FIG.
A channel region 105 made of an intrinsic polycrystalline Si film, a gate insulating film 106 formed on the channel region 105,
A stacked gate electrode 201 formed of a stacked film of a first layer 107 made of Nb or an alloy containing Nb as a main component and a second layer 108 made of a nitride film of the first layer; A drain electrode 111 and a source electrode 112 connected through a through hole to an active layer 109 in which the drain / source region of the polycrystalline Si film 105 is doped with impurities.
The pixel electrode 113 is connected to the source electrode 112 of the TFT 101. An interlayer insulating film 11 is provided between the gate electrode wiring of the TFT 101 and the source / drain electrodes.
0 is formed, and a protective insulating film 1 is formed on the TFT 101 and each wiring.
14 are formed. Reference numeral 102 denotes a pixel display area.

As in the comparative example, a portion where the gate electrode 201 is extended becomes the gate electrode wiring 202 as it is.

FIG. 3 shows an intersection between the gate electrode wiring 202 and the drain electrode wiring 203. As described above with reference to FIG. 26, Nb or the first layer 107 containing Nb as a main component is used.
The pattern end of the gate electrode wiring 202 made of a laminated film of the first layer and the second layer 108 made of a nitride film is processed into a forward tapered shape. By processing in such a tapered shape, the interlayer insulating film 11 on the gate electrode wiring 202 is formed.
Good surrounding characteristics of the zero and drain electrode wirings 203 can be secured, and short-circuiting between the wirings and disconnection of the drain electrode wirings 203 can be prevented. Further, since there is no occurrence of hillocks and whiskers as seen in the Al electrode wiring, a short-circuit failure due to a short circuit between the wirings can be further reduced.

FIG. 4 shows a gate electrode wiring forming step of the embodiment shown in FIGS. The cross-sectional structure of each step is shown. First, as shown in FIG. 4A, an island pattern 401 made of an intrinsic polycrystalline Si film is formed on a glass substrate 103 provided with a base film 104. Next, as shown in FIG. 3B, a gate insulating film 106, a first layer 107 made of Nb or an alloy containing Nb as a main component, and a second layer 108 made of the first nitride film are formed on the entire surface of the substrate. Is formed.
First layer 1 made of Nb or an alloy containing Nb as a main component
07 and a second layer 108 formed of a first layer nitride film, the nitride film is formed continuously with the first layer by using a reactive sputtering method using a mixed gas of Ar and N _2. Can be formed. Next, as shown in FIG. 3C, a gate insulating film 106 and a first layer 107 made of Nb or an alloy containing Nb as a main component, and a second layer 108 made of the first nitride film. By batch-etching the laminated film with the same pattern, the laminated gate electrode 201 and the gate insulating film 106 having substantially the same planar shape are obtained.

As described above with reference to FIG. 24, Nb or Nb
The stacked film of the first layer 107 made of an alloy containing as the main component and the second layer 108 made of the nitride film of the first layer can be easily etched at a time by using an F-based etching gas. is there.

Next, as shown in FIG.
Doping with phosphorus ions as a type dopant. At this time, a stacked pattern of the gate insulating film 106 and the stacked gate electrode 201 serves as a mask, and the channel region 105 made of an intrinsic polycrystalline Si film is formed in a self-aligned manner.

Finally, as shown in FIG. 9E, the impurity ions doped by activation annealing are activated,
An active layer 109 to be a drain / source region is formed.
For the activation annealing at this time, techniques such as thermal annealing and laser annealing are used.
Since the Nb-based / NbN-based laminated film constituting No. 1 has a high melting point and a low stress, defects such as peeling and cracking of the gate electrode pattern due to activation annealing do not occur. In addition, since the gate electrode wiring has an Nb-based / NbN-based laminated film structure, the heat-resistant oxidation resistance to an activation annealing atmosphere is improved. In the subsequent step of forming the interlayer insulating film 110, the resistance of the gate electrode wiring does not increase.

The Nb-based / NbN-based laminated film is shown in FIG.
18 has a significantly lower resistance than the gate electrode made of polycrystalline Si of the comparative example (as described by reference numerals) 1401 described in FIG. 18, so that the signal wiring in the liquid crystal display device includes only the stacked gate electrode 201. Can play a role. Therefore, the second electrode made of the low-resistance metal in the comparative example
This eliminates the need for the gate electrode wiring. Along with this, the interlayer insulating film 1501 for preventing contact between the TFT and the second gate electrode wiring film 201 becomes unnecessary, and it can be seen that the gate electrode wiring structure and the total process are greatly simplified. In other words, by applying the multilayer gate electrode wiring structure of the present invention, while utilizing the features of Nb and a metal material containing Nb as a main component, it is excellent in thermal oxidation resistance and workability, and has low resistance and low stress. Moreover, a simple gate electrode wiring structure excellent in process consistency can be realized. Eventually, TF
By greatly simplifying the T structure and the process, the cost of the liquid crystal display device can be reduced.

Further, since a short circuit due to a short circuit between the wirings at the intersection of the wirings and a disconnection of the drain electrode wirings can be prevented, the yield of the liquid crystal display device can be improved.

FIG. 5 shows an equivalent circuit of an entire active matrix type liquid crystal display device in which a driving circuit constituted by using a CMOS inverter is integrated on the same substrate 501 together with an active matrix type liquid crystal display portion.

This liquid crystal display device has a TFT as a display unit.
An active matrix 50, a vertical scanning circuit 51 for driving the matrix, a horizontal scanning circuit 53 for dividing video signals for one scanning line into a plurality of blocks and supplying them in a time-division manner; , And a switch matrix circuit 52 for supplying video signals to the active matrix side for each divided block. Here, the vertical scanning circuit 51 and the horizontal scanning circuit 53 are configured by a shift register and a buffer, and the clock signals CL1 and Cl
2, driven by CKV.

FIG. 6 is a circuit diagram when a CMOS inverter circuit formed on a substrate is formed. PMOS and NM
The OS is configured as shown in the figure, has an input terminal Vin and an output terminal Vout, and is supplied with a reference voltage Vss and a power supply voltage Vdd.

FIG. 7 shows a pattern layout of the inverter circuit shown in FIG. FIG. 8 is a cross-sectional view taken along the line xx 'in FIG. 7, and FIG. 9 is a cross-sectional view taken along the line yy' in FIG. The CMOS inverter according to the present embodiment includes a PMOS 701 as a P-type TFT and an N-type TFT as an N-type TFT.
MOS702.

As shown in FIG. 8, the gate electrodes 703 and 704 of the two TFTs 701 and 702 are connected to the input terminal Vin.
The first wiring electrode 705 and the through hole T
H is connected.

As shown in FIG. 9, an electrode for supplying a reference voltage Vss and a power supply voltage Vdd to the circuit and an output terminal Vout connecting the drain electrodes of the two TFTs are formed by a second wiring electrode 706. I have. The output terminal Vout is the input voltage of the shift register corresponding to the next scanning line.

At this time, both the wiring electrodes 705 and 706 are formed of the same layer and the same material as the drain electrode wiring of the TFT. Therefore, on the input terminal Vin side, the wiring electrode 70
5 and the gate electrodes 703 and 704 of the TFT, that is, good through-hole contact characteristics between the drain electrode wiring material and the gate electrode wiring material must be ensured. P-type transistor PMOS
Specifically, the gate electrodes 703 and 704 are used by using the TFT 701 and the TFT constituting the N-type transistor NMOS702.
Is a first layer 107 made of Nb or an alloy containing Nb as a main component, and a second layer 108 made of a nitride film of the first layer.
The wiring electrodes 705 and 706 are formed of Cr, which is a drain electrode wiring material, or an alloy film of Cr and Mo. In addition, the gate electrode 703
The interlayer insulating film 110 on the layers 704 and 704 is composed of a SiO ₂ film.

In this case, gate electrodes 703 and 704 are also N
It is composed of a b-based / NbN-based laminated film structure, and a sufficient thermal oxidation resistance is guaranteed. Therefore, the gate electrode wiring resistance does not increase after the formation of the interlayer insulating film 110 made of the SiO ₂ film.

As shown in FIG. 27, Nb and Nb nitride
Through-hole contact resistance between the layered film and Cr or CrMo is sufficiently low. Therefore, the wiring electrode 705 and the TF
In connecting the T gate electrodes 703 and 704, good through-hole contact characteristics can be ensured.

As described above with reference to FIG. 25, since the interlayer insulating film 110 can be selectively etched on the gate electrodes 703 and 704, the lower gate electrodes 703 and 704 are not damaged in the through-hole forming step. . As a result, a CMOS inverter having a simple structure and good characteristics can be obtained, so that it is easy to incorporate a peripheral circuit, and it is possible to greatly improve the performance and cost of the liquid crystal display device. In the above embodiment,
As a drain electrode and a drain electrode wiring material, Cr,
Alternatively, an alloy film of Cr and Mo is used, but a portion in contact with the gate electrode and the gate electrode wiring is formed of a first layer made of Cr or an alloy film of Cr and Mo, and a low-resistance metal film is formed thereon. By forming a drain electrode / drain electrode wiring structure in which a second layer made of an aluminum alloy film is laminated, not only a through hole contact characteristic but also a drain electrode / drain electrode wiring having low wiring resistance can be obtained.

In the above embodiment, the entire structure is formed using a coplanar type TFT, but the TFT may be an inverted stagger type or a normal stagger type. In the above embodiment, the entire structure is formed by using the vertical electric field type TFT. However, the horizontal electric field type TFT applies a horizontal electric field between the source electrode of the TFT and the common electrode formed on the same substrate. May be used. Further, the present invention can be similarly applied to a case where amorphous Si is used instead of intrinsic polycrystalline Si for the channel semiconductor layer of the TFT. The embodiment described below is an example in which the present invention is applied to an inverted staggered amorphous Si-TFT.

FIG. 10 is a plan view of a unit pixel of an active matrix liquid crystal display device according to the present invention, which is formed by using an inverted stagger type TFT.

FIGS. 11 and 12 respectively show x-
It is sectional drawing which follows the line shown by x ', yy'.

The basic structure of the present liquid crystal display device is that
4, a gate electrode wiring 202 formed on a glass substrate 103, a drain electrode wiring 203 formed to intersect the gate electrode wiring 202, a TFT 101 formed near an intersection of these electrode wirings, and a pixel display area 102. And additional capacity 10
01.

The difference from the embodiment of the coplanar TFT described with reference to FIGS. 1 to 4 is that the TFT 101 is constituted by an inverted staggered TFT, and that the active region in which the channel region 105 and the drain and source regions are doped with impurities. 109 is made of amorphous Si, and the first gate insulating film 1101 is made of a SiO ₂ film.
And a second gate insulating film 1102 made of a SiN film.

In an amorphous Si TFT, an SiN film is generally used for a gate insulating film in order to secure the stability of an interface between amorphous Si as a channel layer and the gate insulating film.

However, when the gate insulating film is composed of a single-layered SiN film, as described above, the first layer made of Nb or an alloy containing Nb as a main component located under the gate insulating film.
Layer 107 and second layer 108 made of the first nitride film
On the stacked gate electrode and the gate electrode wirings 201 and 202 composed of a stacked film (Nb-based / NbN-based)
It becomes difficult to selectively etch the gate insulating film made of the SiN film.

Therefore, in the embodiment, the first gate insulating film 1101 made of the SiO ₂ film and the S
A laminated gate insulating film structure with a second gate insulating film 1102 made of an iN film is employed, and the selective etching characteristics of the gate electrode and the gate electrode wirings 201 and 202 are SiO _2.
In the first gate insulating film 1101 made of a film, the stability of the interface with the channel layer 105 is secured by the second gate insulating film 1102 made of a SiN film.

Also in this case, the gate electrode and the gate electrode wirings 201 and 202 have a sufficient heat-resistant oxidizing property by being constituted by an Nb / NbN-based laminated film structure. Therefore, S
After the formation of the first gate insulating film 110 made of the SiO ₂ film, the gate electrode wiring resistance does not increase.

FIG. 12 shows an intersection between the gate electrode wiring 202 and the drain electrode wiring 203. By applying the present invention, Nb or the first layer 107 containing Nb as a main component is used.
If, because the pattern end portions of the gate electrode wiring 202 made of a stacked film of a second layer 108 made of a nitride film of the first layer is processed into a forward tapered shape, a SiO ₂ film on the gate electrode wiring 202 First gate insulating film 1101, Si
Good surrounding characteristics of the second gate insulating film 1102 made of N film and the drain electrode wiring 203 can be ensured.
3 can be prevented. In addition, since no hillocks or whiskers occur as in the Al electrode wiring, it goes without saying that short-circuit failure due to a short circuit between the wirings can be prevented. FIG. 13 is a schematic sectional view of an active matrix type liquid crystal display device according to the present invention. Liquid crystal layer 1
A gate electrode wiring (scanning signal wiring) 202 and a drain electrode wiring (video signal wiring) 203 are formed on the glass substrate 103 below the matrix 302 in a matrix, and are formed of ITO by TFTs formed near intersections thereof. The pixel electrode 113 is driven. A counter electrode 1306 made of ITO, a color filter 1304, a color filter protective film 1307, and a light-shielding film 1308 for forming a light-shielding black matrix pattern are formed on an opposite glass substrate 1305 facing the liquid crystal layer 1302 therebetween.

The center of FIG. 13 is a cross section of one pixel portion, the left is a cross section of a left edge portion of a pair of glass substrates 103 and 1305 where external lead-out terminals are present, and the right is a pair of glass substrates 103 and 1305. 2 shows a cross section of a portion where no external lead-out terminal is present on the right side edge portion of FIG.

The sealing materials SL shown on the left and right sides of FIG. 13 are configured to seal the liquid crystal layer 1302, and the edges of the glass substrates 103 and 1305 except for the liquid crystal filling port (not shown). It is formed along the whole.
The sealant is formed of, for example, an epoxy resin. The opposing electrode 1306 on the opposing glass substrate 1305 is connected at least at one position to an external lead wire formed on the glass substrate 103 by a silver paste material SIL. The external lead wiring is formed in the same manufacturing process as each of the gate electrode wiring 202, the source electrode 112, and the drain electrode wiring 203. Therefore, for example, the external lead-out wiring of the gate electrode wiring 202 is, specifically, Nb of the present invention.
It can be constituted by a system / NbN system laminated film structure. Each external lead wiring is made of an anisotropic conductive film (ACF: Anisot).
ropic Conductive Film) and TCP (Tape Carri
er Package) or an external drive circuit of a COG (Chip On Glass) connection method. Orientation film ORI1, ORI
2. Pixel electrode 113, protective film 114, interlayer insulating film 11
Each layer of the gate insulating film 106 made of O, SiO ₂ is formed inside the sealing material SL. Polarizing plate 1301
Are formed on the outer surfaces of the pair of glass substrates 103 and 1305, respectively.

The liquid crystal layer 1302 is sealed between a lower alignment film ORI1 for setting the direction of liquid crystal molecules and an upper alignment film ORI2, and is sealed by a sealing material SL. The lower alignment film ORI1 is a protective insulating film 1 on the glass substrate 103 side.
14 is formed at the top. The light-shielding film 1308 and the color filter 13
04, color filter protective film 1307, counter electrode 13
06 and an upper alignment film ORI2 are sequentially laminated. In this liquid crystal display device, layers on the glass substrate 103 side and the counter glass substrate 1305 side are separately formed, and then the upper and lower glass substrates 103 and 1305 are overlapped.
02 is assembled. By adjusting the transmission of light from the backlight BL at the pixel electrode 113, a TFT-driven color liquid crystal display device is configured.

As described above, the gate electrode (scanning signal wiring) 2
01 and the gate electrode wiring 202 as Nb or N
By using a laminated gate electrode wiring structure of an alloy containing b as a main component and Nb or a nitride of an alloy containing Nb as a main component, it is excellent in heat resistance oxidation property and workability, has low resistance and low stress, and has process matching. Since a simple gate wiring structure excellent in performance can be easily realized, an active matrix type liquid crystal display device excellent in throughput and yield can be easily realized.

In addition, since the incorporation of peripheral circuits is facilitated,
The performance and cost of the liquid crystal display can be significantly improved. Further, in the above embodiment, the entire structure is formed using the vertical electric field type TFT, but the same applies to the case where the horizontal electric field type TFT having the common electrode and the common electrode wiring is used.

The TFT is a coplanar type, an inverted stagger type,
Alternatively, a staggered type may be used, but in particular, in a coplanar type element, a higher-speed operation is possible because the parasitic capacitance between the gate and the source or the drain can be reduced.
This is advantageous for a liquid crystal display device with a built-in peripheral circuit.

The present invention is similarly applicable to a non-peripheral circuit built-in type liquid crystal display device using amorphous Si instead of intrinsic polycrystalline Si for the channel semiconductor layer of the TFT.

In the above-described embodiment, only the case where the laminated structure of Nb / NbN or NbN / Nb / NbN is applied to the gate electrode and the gate electrode wiring is shown. However, the drain electrode wiring, the source electrode, the common electrode, and the common electrode wiring are shown. In the case of having a common electrode and a common electrode wiring, effects such as thermal oxidation resistance, good matching with the insulating film, and good through-hole contact characteristics via the insulating film can be obtained. it can.

An alloy containing Nb as a main component and Nb
Examples of nitrides of alloys mainly containing
There are Nb alloys containing Mo, Ti, V, Si and the like in a range of several percent or less, and nitrides of these Nb alloys.

[0095]

According to the present invention, it is possible to easily obtain a wiring excellent in thermal oxidation resistance, and to realize a high-performance and low-cost liquid crystal display device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention using a coplanar TFT, and is a cross-sectional view taken along line xx ′ shown in FIG.

FIG. 2 is a plan view of a unit pixel of a liquid crystal display device according to an embodiment of the present invention configured using a coplanar TFT.

FIG. 3 is a cross-sectional view of a liquid crystal display device according to an embodiment of the present invention configured using a coplanar TFT, and is a cross-sectional view taken along line yy 'shown in FIG.

FIG. 4 is a sectional view of each step of the gate electrode wiring shown in FIG. 2;

FIG. 5 is an equivalent circuit diagram of the entire active matrix type liquid crystal display device according to the embodiment of the present invention in which a drive circuit formed using a CMOS inverter is integrated together with a display unit on the same substrate.

FIG. 6 is a configuration diagram of a CMOS inverter circuit according to an embodiment of the present invention.

FIG. 7 is a pattern layout diagram of the inverter circuit shown in FIG. 6;

FIG. 8 is a sectional view taken along the line xx ′ shown in FIG. 7;

FIG. 9 is a sectional view taken along the line yy ′ shown in FIG. 7;

FIG. 10 is a plan view of a unit pixel of an active matrix liquid crystal display device according to an embodiment of the present invention, which is configured using an inverted staggered TFT.

FIG. 11 is a sectional view taken along the line xx ′ shown in FIG. 10;

FIG. 12 is a sectional view taken along the line yy ′ shown in FIG. 10;

FIG. 13 is a schematic sectional view of an active matrix type liquid crystal display device according to an embodiment of the present invention.

FIG. 14 is a plan view of a unit pixel of an active matrix liquid crystal display device according to a comparative example of the present invention configured using a coplanar TFT.

FIG. 15 is a sectional view taken along the line xx ′ shown in FIG. 14;

FIG. 16 is a sectional view taken along the line yy ′ shown in FIG. 14;

FIG. 17 is a sectional view taken along the line zz ′ shown in FIG. 14;

18 is a cross-sectional view of each step of forming a gate electrode wiring of the comparative example of the present invention shown in FIG.

FIG. 19 is a diagram showing a change in resistance of an Nb film when heat treatment is performed at a different heat treatment temperature.

FIG. 20 is a diagram showing a change in resistance when a Nb film subjected to a surface plasma nitriding treatment is heat-treated.

[21] N ₂ amount of varied form the nitride Nb film (N
FIG. 9 is a graph showing resistance characteristics of (bN-based).

22 is an X-ray diffraction spectrum of an Nb nitride film (NbN-based) formed by changing the amount of N ₂ shown in FIG. 21.

FIG. 23 shows Nb-based /
The figure which shows the resistance change of a NbN-type laminated film.

FIG. 24 shows Nb, N when etched using SF ₆
bN, SiO _2, SiN, and graph plotting the relationship between the etching time and etching thickness of the resist film.

[Figure 25] Nb at the time of etching with CHF _3,
NbN, and graph plotting the relationship between the etching time and etching the film thickness of the SiO ₂ film.

FIG. 26 is a schematic cross-sectional view of an end portion of a wiring pattern of an Nb-based / NbN-based laminated film.

FIG. 27: Nb-based / NbN-based laminated film and Cr or Cr
The figure which shows the through-hole contact resistance with Mo.

FIG. 28 is a wiring cross-sectional view of an NbN-based / Nb-based / NbN-based laminated film.

FIG. 29 is a wiring cross-sectional view of an NbN-based / Nb-based / NbN-based laminated film.

[Explanation of symbols]

50: active matrix, 51: vertical scanning circuit,
52: switch matrix circuit, 53: horizontal scanning circuit, 101: TFT, 102: pixel display area, 103:
Glass substrate, 104 base film, 105 channel region of TFT, 106 gate insulating film, 107 Nb, or first layer made of an alloy containing Nb as a main component, 108 N
a second layer made of a nitride of b and an alloy containing Nb as a main component; 109... an active layer doped with an impurity in a drain / source region; 110 and 1501. an interlayer insulating film; 111. ... Source electrode, 11
DESCRIPTION OF SYMBOLS 3 ... Pixel electrode, 114 ... Protective insulating film, 201 ... Gate electrode, 202 ... Gate electrode wiring, 203 ... Drain electrode wiring, 401 ... Island pattern made of intrinsic polycrystalline Si film, 7
01 ... PMOS, 702 ... NMOS, 703, 704 ...
TFT gate electrode, 705... First wiring electrode, 706
... Second wiring electrode, 1001... Additional capacitance, 1101.
_A first gate insulating film composed of _two films, 1102... A second gate insulating film composed of a SiN film, 1302.
04: color filter, 1305: counter glass substrate,
1306: Counter electrode, 1307: Color filter protective film, 1308: Light shielding film, 1401: First gate electrode made of polycrystalline Si film doped with impurities, 1801: Amorphous Si film, TH: Through hole TH, SL: Seal Material, SIL ... Silver paste material, ORI1, ORI2 ...
Alignment film, BL: backlight BL.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kenichi Chahara 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd. Hitachi Research Laboratory, Ltd. No. 1-1, Hitachi, Ltd., Hitachi Research Laboratory (72) Inventor Katsura Tamura 7-1-1, Omika-cho, Hitachi City, Ibaraki Pref., Ltd. Hitachi, Ltd. Hitachi Research Laboratory

Claims (17)

[Claims] 1. A liquid crystal display device having a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates, wherein one of the pair of substrates is made of Nb or an alloy containing Nb as a main component. A liquid crystal display device comprising a wiring formed of a first layer and a second layer formed of a nitride of Nb or a nitride of an alloy containing Nb as a main component. 2. A liquid crystal display device having a pair of substrates and a liquid crystal layer sandwiched between the pair of substrates, wherein one of the pair of substrates is formed of a nitride of Nb or an alloy containing Nb as a main component. A liquid crystal display device comprising a wiring constituted by an object layer. 3. The semiconductor device according to claim 1, wherein N
A liquid crystal display device comprising a third layer formed of a nitride of b or a nitride of an alloy containing Nb as a main component. 4. The liquid crystal display device according to claim 1, wherein an insulating film made of a silicon oxide film is formed on the wiring. 5. The liquid crystal display device according to claim 1, wherein said first layer and said second layer are collectively etched in the same pattern. 6. The liquid crystal display device according to claim 3, wherein the first layer, the second layer, and the third layer are collectively etched in the same pattern. 7. A liquid crystal display device according to claim 1, wherein an end of said wiring has a forward tapered shape. 8. The device according to claim 1, wherein the first layer has a specific resistance of 20 μΩcm or less, and the second layer has a specific resistance of 1 μm or less.
A liquid crystal display device having a range of from 00 to 200 μΩcm. 9. The semiconductor device according to claim 2, wherein the specific resistance of the wiring layer made of the nitride of Nb or the nitride of an alloy containing Nb as a main component is in the range of 100 μΩcm to 200 μΩcm. Liquid crystal display. 10. The liquid crystal display device according to claim 1, wherein said second layer has a thickness of 5 to 100 nm. 11. A semiconductor device comprising: a pair of substrates; and a liquid crystal layer sandwiched between the pair of substrates. A plurality of gate electrode wirings are formed on the pair of substrates so as to intersect the plurality of gate electrode wirings. A plurality of drain electrode wirings, a plurality of thin film transistors formed corresponding to intersections of these wirings, and a plurality of source electrodes formed corresponding to the plurality of thin film transistors. When there are a plurality of gate electrode wirings, drain electrode wirings, source electrodes, common electrodes, common electrode wirings,
At least one of the common electrode and the common electrode wiring is a laminated film having a first layer made of Nb or an alloy containing Nb as a main component and a second layer made of Nb or a nitride of an alloy containing Nb as a main component. A liquid crystal display device comprising: 12. A semiconductor device comprising: a pair of substrates; and a liquid crystal layer sandwiched between the pair of substrates. The pair of substrates are formed with a plurality of gate electrode wirings and intersecting the plurality of gate electrode wirings. A plurality of drain electrode wirings, a plurality of thin film transistors formed corresponding to intersections of these wirings, and a liquid crystal display device having a plurality of source electrodes formed corresponding to the plurality of thin film transistors,
When the plurality of gate wirings, drain electrode wirings, source electrode and common electrode, and common electrode wiring are provided, at least one of the common electrode and the common electrode wiring is nitride of Nb or nitride of an alloy containing Nb as a main component. A liquid crystal display device comprising a layer film. 13. The method according to claim 11, wherein a third layer made of a nitride of Nb or a nitride of an alloy containing Nb as a main component is formed under the first layer. Liquid crystal display device. 14. An insulating film made of a silicon oxide film according to claim 11, wherein an insulating film made of a silicon oxide film is formed on a wiring made of a laminated film having said first layer and said second layer. A liquid crystal display device characterized by the above-mentioned. 15. The liquid crystal display device according to claim 14, wherein said silicon oxide film is at least a part of a gate insulating film of said thin film transistor. 16. The device according to claim 11, wherein the drain electrode wiring or the source electrode wiring is made of chromium,
Or a liquid crystal display device formed of an alloy film of chromium and molybdenum. 17. The liquid crystal display device according to claim 11, wherein at least a part of the drain electrode wiring or the source electrode wiring is formed of chromium or an alloy film containing chromium and molybdenum.