JPH11274469A - Iii-v compound semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve bondability by that an electrode layer of a III-V compound semiconductor device having an electrode on the compound semiconductor layer includes an Au containing layer in contact with the compound semiconductor layer and a surface layer having a specific group III element percentage content. SOLUTION: AuZnNi alloy is used as an underlying electrode layer for being in ohmic contact with surface layer p-type GaAs 4 in a p-type III-V compound semiconductor device. AuGeNi alloy is used as an underlying electrode layer 51 for being in ohmic contact with surface layer n-type GaAs in a n-type III-V compound semiconductor device. The electrode layers include an Au containing layer (ohmic contact layer) and a surface layer and Au is used as the preferable material for the surface layer, and the surface layer has a content ratio of group III type compound (preferably Ga) not more than 5%. If it exceeds 5%, bondability is deteriorated and the content ratio not more than 5% can improve the bondability.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a group III-V compound semiconductor device, and more particularly to a group III-V compound semiconductor device having improved bonding properties in device formation. The group III-V compound semiconductor device of the present invention is suitably used as a light source for information processing and communication.

[0002]

2. Description of the Related Art A group III-V compound semiconductor device (for example, a laser diode or a light emitting diode) is formed on a substrate by using a III-V compound semiconductor device.
After epitaxially growing a group V compound semiconductor layer,
An electrode is formed on both the substrate side and the epi side, or a plurality of electrodes are further formed on the epi side, and then cut into element sizes in a chip forming process, and after an end face coating, a bonding process and a packaging process are performed. After the product.

The above-mentioned electrodes serve as an interface when the element is incorporated into a carrier or when wiring is performed on the electrodes on the surface of the element. It is important that the electrodes have low resistance and are ohmic-connected. Then, the electrode usually has a multilayer structure including a base layer and a surface layer for making ohmic contact with the compound semiconductor layer.

Au is widely used as a material of a surface electrode layer provided on a base electrode layer (ohmic contact layer). Au has a high conductivity and does not corrode in the air, so that it can maintain a stable surface and is therefore suitable as a material for the surface electrode layer. The Au surface electrode layer is suitable not only for bonding with a carrier whose surface is coated with solder containing Au as a main component (die bonding) but also for bonding with an Au wire as described above (wire bonding). .

In a III-V compound semiconductor, since a group III element (particularly Al) easily forms an oxide, an antioxidant layer such as GaAs or GaInP is provided on the surface of the semiconductor element, and this is used as an electrode. Generally, it is a forming surface.

On the other hand, electrode materials capable of ohmic connection with GaAs or GaInP are known empirically. For example, in the case of p-type GaAs, Cr, Pt, Ti, AuZ
AuGeNi for n-type GaAs such as nNi alloy
An alloy or the like is used. In short, the electrode configuration of the semiconductor element is a layer configuration in which an Au layer is arranged on the ohmic contact layer as described above. For example, in the case of p-type GaAs,
Au / Cr, Au / Pt, Au / Ti, Au / AuNi
It has a layer structure such as an Au alloy.

In the formation of the above-mentioned electrodes, a heat treatment process called an alloy is generally applied to obtain a better ohmic contact to strengthen the bonding between the semiconductor and the electrode material. At this time, for example, Au mainly forms an alloy with a group III element. Ni forms an alloy with the group V element, and functions to increase the adhesion between the semiconductor and the electrode layer. That is, Ni in the AuZnNi alloy diffuses into the p-type semiconductor matrix and functions to make ohmic contact. Similarly, Ge of the AuGeNi alloy diffuses into the n-type semiconductor matrix, and functions to make ohmic contact. In other words, by forming the intermediate composition between the semiconductor and the electrode material, physical and electrical bonding between the semiconductor and the electrode can be obtained.

However, in the conventional III-V compound semiconductor device, especially when the alloying step is performed,
There is a problem that a sufficient bonding strength cannot be obtained in the die bonding step or the wire bonding step. The reason is considered as follows.

That is, when an impurity different from the electrode material is present in the Au electrode surface layer, the strength and strength of die bonding and wire bonding are significantly reduced. Such impurities are constituent elements of the semiconductor layer and the base electrode layer that diffuse into the electrode surface. For example, AuG on n-type GaAs
In the case of an electrode configuration in which an ohmic contact layer of an eNi alloy and an Au electrode layer for bonding are formed, Au
Ni, Ge and Ga diffuse to the surface of the electrode surface layer.
Similarly, Cr, which is a typical ohmic contact material of p-type GaAs, diffuses in the Au electrode surface layer and appears on the surface.

It is also known that impurities are deposited from the semiconductor interface on the Au electrode surface layer even without a heat treatment step (A. Hiraki, K. Shuto, S. Kim, W. Kammura).
andM. Iwami: Appl. Phys. Lett. vol. 31 (1977) p
611). For example, an Au-containing layer such as A on GaAs
When a uGeNi alloy layer is provided, GaAs and AuGeN
At the interface of the i alloy, Ga in the semiconductor is sucked out by the AuGeNi alloy layer and deposited on the surface. Ga once deposited is characterized in that it appears on the outermost surface even if an Au-containing overcoat layer is further added.

According to the above document, the forbidden band width is 2.5 e
It is described that, in the bonding of a semiconductor having a V or less and an Au-containing layer, constituent elements of the semiconductor are deposited on the surface of the Au-containing layer without going through a heat treatment step. Further, it is described that such a phenomenon occurs not only in the case of Au but also in most metal materials. This band gap of 2.5 eV is a value larger than the band gap of many practical III-V compound semiconductors. In other words, when the electrode surface of many III-V compound semiconductors, particularly the interface with the semiconductor is an Au-containing layer, the group III element that is a constituent element of the semiconductor diffuses as an impurity into the electrode surface. .

The impurities diffused from the base into the Au surface layer cause a reduction in bonding strength by forming an alloy with Au or forming an oxide.

For example, in the case of die bonding, a Au-deficient solder material such as AuSn or PbSn is applied to the carrier side, and heat is applied by bringing the solder material into contact with the Au surface electrode layer of the element. As a result, Au of the electrode layer is taken into the solder material to form a eutectic, thereby achieving bonding. At this time, if impurities are mixed in the Au surface electrode layer, a phenomenon occurs in which the eutectic temperature with the solder material shifts to a high temperature side and the die bond strength decreases. In this case, if the temperature at the time of joining is increased in order to increase the joining strength, diffusion of impurities from the base of the electrode is promoted, causing a vicious cycle. For this reason, there is a case in which an additional Au layer for improving the bonding property is laminated after the heat treatment to form an overcoat. However, the diffusion of impurities to the surface of the additional electrode layer is caused by the above-described method. It is clear from the contents described in the literature.

[0014] On the other hand, wire bonding is a process in which an Au wire is pressed against an Au surface electrode layer and ultrasonic waves are applied to perform bonding. However, as in the case of die bonding, bonding is performed when impurities exist on the Au surface. The strength is significantly reduced.

As described above, the strengths of the die bonding and the wire bonding are determined by the A of the surface electrode layer in each case.
Since it largely depends on the purity of u, diffusion of impurities from the base to the Au surface electrode layer becomes a problem. What is important here is that a sufficient bonding strength cannot be obtained unless the area content of the impurities is low, not the volume content of the impurities contained in the Au surface electrode layer. Further, a problematic point is that the above-mentioned bonding failure may or may not occur from time to time. In short, it can be said that the degree of deposition of impurities on the surface electrode layer is a delicate amount of deposition relative to bonding.

[0016]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a group III-V compound semiconductor device having an improved bonding property at the time of device fabrication. is there.

[0017]

Means for Solving the Problems The present inventors have made intensive studies to achieve the above object, and as a result, obtained the following new knowledge. (1) When an Au-containing layer is used as an electrode layer directly in contact with the compound semiconductor layer, the effect of sucking the group III element out of the compound semiconductor layer is particularly large, but the content of the group III element in the surface electrode layer is 5%. %, The bonding strength is significantly reduced. (2) Ti in the electrode layer
By providing an impurity absorption layer of a specific composition such as
It is possible to trap the group I element and suppress the content of the group III element in the surface layer to 5% or less.

The present invention has been completed based on the above findings, and a first gist thereof is a group III-V compound semiconductor device comprising an electrode layer on a compound semiconductor layer,
The electrode layer includes an Au-containing layer in contact with the compound semiconductor layer and a surface layer having a Group III element content of 5% or less.
III-V compound semiconductor devices.

A second gist of the present invention is a III-V compound semiconductor device having an electrode layer on a compound semiconductor layer, wherein the electrode layer has an Au-containing layer in contact with the compound semiconductor layer. Characterized by including an impurity absorbing layer and a surface layer
III-V compound semiconductor devices.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
A III-V compound semiconductor device of the present invention (hereinafter simply referred to as a device) is basically similar to a conventionally known device,
After epitaxially growing a group III-V compound semiconductor layer on a substrate, electrodes are formed on both the substrate side and the epi side, or a plurality of electrodes are further formed on the epi side.
The element of the present invention can be manufactured basically according to a method similar to a conventionally known method.

The types of the above substrates are GaAs, G
In addition to a III-V group compound semiconductor substrate such as aP, a heterogeneous substrate such as a sapphire substrate or a Si substrate may be used. In particular, II
When an IV group compound semiconductor substrate is used, the effect of the present invention is remarkable in that the problem of poor bonding caused by the substrate-side electrode can be prevented.

The III-V compound semiconductor layer is made of AlAs, G
It is composed of a combination of aAs, GaP, InAs, InP, AlN, GaN or a layer in which the composition, conductivity and carrier concentration of a mixed crystal thereof are controlled. Then, a contact layer made of GaAs, GaP, InP, GaN or a mixed crystal thereof is usually disposed on the surface layer of the III-V compound semiconductor layer in order to prevent oxidation of the device and form electrodes.

In many cases, each of the above epitaxially grown layers is lattice-matched to the substrate. For example, in the case of a GaAs substrate, the group III-V compound semiconductor layer is formed of AlxGa1-xAs.
(X = 0-1), (AlxGa1-x) yIn1-yP (x
= 0, 1, y = 0.5), and the surface layer of the group III-V compound semiconductor layer is often made of GaAs or Ga _0.5 In _0.5 P. The carrier concentration of the above surface layer is usually 5 ×
10 ^{17 to} 5 × 10 ¹⁹ cm ⁻³ , preferably 5 × 10 ¹⁸ to 2
× 10 ¹⁹ cm ^-3 and a thickness of usually 0.1 μm or more, preferably 0.5 to 7 μm.

An AuZnNi alloy is used as a base electrode layer (ohmic contact layer) for making ohmic contact with a surface layer (specifically, p-type GaAs, p-type GaInP, etc.) of a p-type III-V compound semiconductor. Is preferably used. The weight ratio of the constituent elements of the AuZnNi alloy is usually
Zn is about 1 to 10% and Ni is about 1 to 10%. In the case of this alloy, Zn must be contained.

On the other hand, a base electrode layer (ohmic contact layer) for making an ohmic contact with a surface layer (specifically, n-type GaAs, n-type GaInP, etc.) of an n-type III-V compound semiconductor includes: AuGeNi alloy is preferably used. The weight ratio of the constituent elements of the AuGeNi alloy is
Usually, Ge is about 1 to 10% and Ni is about 1 to 10%. In this alloy, Ge must be contained.

In the device according to the first aspect of the present invention,
The electrode layer includes the above Au-containing layer (ohmic contact layer) in contact with the compound semiconductor layer and a surface layer. As described above, Au is preferably used as the material of the surface layer. The surface layer is characterized by having a group III compound (preferably Ga) content of 5% or less.

On the other hand, in the device according to the second aspect of the present invention, the electrode layer includes an Au-containing layer (an ohmic contact layer) and a surface layer, as in the above-described device, and
It is characterized by including an impurity absorbing layer between the containing layer and the surface layer. Further, as a preferred embodiment, an impurity barrier layer is included on the impurity absorbing layer. The surface layer of the electrode layer of the device according to the second aspect of the present invention has a group III compound content of 5% or less due to the electrode configuration including the impurity absorbing layer.

That is, in the electrode of the present invention, the impurity absorbing layer and the impurity barrier layer are provided between the surface electrode layer and the underlying electrode layer without changing the material of the underlying electrode layer (ohmic contact layer) to a special material. It is an electrode that can be inserted to suppress diffusion of impurities to the surface side of the electrode.

As a material of the above-mentioned impurity absorption layer, Ti is preferable. That is, from the result of analyzing the profile of the impurity concentration in the depth direction of the Ti layer by SIMS, the impurity concentration profile from the interface between the underlayer and the Ti layer toward the surface sharply decreases toward the surface. It has been found. The fact that the impurity concentration rapidly decreases in the Ti layer indicates that the impurities are trapped and absorbed in the Ti layer. The Ti layer is a group III element (Ga, Al, In, etc.) among the constituent elements of the group III-V semiconductor.
The effect of efficiently absorbing is significant. Because Ti
This is because when there is no layer, the group III element is not completely absorbed by Au of the ohmic electrode layer and is deposited on the surface of the electrode layer.

The Ti layer is made of not only group III elements but also Ge,
It also effectively absorbs electrode material constituent elements such as Ni, Zn, and Cr. In particular, the underlying electrode layer (ohmic contact layer)
When the Au-containing layer is used, the group III element diffused to the surface of the Au-containing layer can be efficiently trapped and absorbed by the Ti absorption layer.

The thickness required for the Ti layer to sufficiently absorb impurities is usually 5 nm or more, and the upper limit thereof is preferably 1 μm or less which does not cause unnecessary distortion.

As the material of the impurity barrier layer, a metal having a melting point of 1600 ° C. or more is preferable, and the temperature is higher than a heat treatment temperature of a wafer provided with electrodes, which will be described later.
Metals that do not cause interdiffusion when brought into contact with other metal materials at temperatures up to about 0 ° C. are preferred. Examples of such a metal material include Pt, Mo, and Ta.

It is necessary that the material of the impurity barrier layer does not itself diffuse into the surface electrode layer and become an impurity. Although Pt slightly diffuses into the Au surface electrode layer, it does not appear on the surface of the surface electrode layer because the diffusion is several nm and almost zero. Further, since Pt itself is stable, it does not affect the properties of Au in the surface electrode layer. Mo and Ta are
Although it does not diffuse into the Au layer, attention must be paid to the thickness to be formed because strain is introduced into the electrode layer. Pt is advantageous in that distortion is small.

The overall structure of the preferred electrode layer is as follows. That is, on the p-side, a Ti impurity absorption layer is disposed on an AuZnNi alloy ohmic contact layer, a Pt, Mo or Ta impurity barrier layer is disposed thereon, and an Au surface electrode layer is disposed thereon. Place. On the n side, an impurity absorbing layer of Ti is arranged on an ohmic contact layer of AuGeNi alloy, an impurity barrier layer of Pt, Mo or Ta is arranged thereon, and a surface electrode layer of Au is arranged thereon. .

The electrode layer initially placed on the semiconductor wafer (semiconductor layer) is often deposited by vacuum evaporation. Vacuum deposition is a simple method in which impurities are less likely to be mixed into the interface between the semiconductor wafer and the electrode and can form an electrode layer with a uniform thickness on the surface of the semiconductor wafer. The electrodes are patterned according to the shape of the element. Such patterning is achieved by combining resist patterning and vacuum deposition technology. If a thick electrode layer is required, plating may be performed after vacuum deposition to increase the thickness. Au plating solutions include cyanide and sulfurous acid, and these plating solutions are:
It is selected according to the material of the resist forming the plating pattern. Care must be taken in selecting the plating solution because it depends on the purity of the Au electrode. In the present invention, a combination of a negative photoresist and a sulfurous acid-based plating solution is recommended.

Au on the surface electrode layer to be bonded
The thickness of the layer is usually several tens nm or more, preferably 50 nm.
To 20 μm.

In the alloying step, heat treatment is performed at a temperature up to about 500 ° C. for a time corresponding to the temperature, and alloying is performed at the interface between the semiconductor and the electrode material. Generally, if the temperature of the alloy is too low, ohmic contact cannot be made and a long processing time is required. If the alloy temperature is too high or the alloy time is too long, the constituent materials of the semiconductor and the underlying electrode layer diffuse into the surface of the surface electrode layer, roughening the surface and causing poor electrical characteristics and poor bonding.

Therefore, the alloy has an appropriate alloy temperature and alloy time depending on the semiconductor material and the electrode material, and these must be carefully selected. Depending on the combination of the semiconductor material and the electrode material, an ohmic contact can be obtained without an alloying step. For example, p-type GaAs
Ohmic contact can be obtained without alloy in combination of Ti and Ti. However, when there is no alloying step, the adhesive strength between the semiconductor and the electrode is not sufficient, so that the alloying step is generally performed.

In the coating step, usually 200 to 50
An optical thin film such as Al ₂ O ₃ is formed at a temperature of 0 ° C., preferably 250 to 450 ° C. for about several hours. Generally, the temperature of the coating process is not higher than the alloy temperature, but still, the group III element such as Ga tends to rise on the electrode surface. Group III elements such as Ga diffuse more toward the electrode surface as the temperature increases.

However, in the device of the present invention,
Even after the heat history as described above, the group III element is absorbed by the impurity absorption layer Ti and diffusion is suppressed by the impurity barrier layer, so that the group III element does not precipitate on the surface of the surface electrode layer. In other words, the effect of the device of the present invention is remarkable when the device is manufactured by coating the cleavage surface after forming the electrode.

After coating, the element is cut out and L
D chip. Generally, an LD chip has Au on its surface.
Die bonding is performed on a carrier coated with a Sn solder film or a PbSn solder film. For example, when performing die bonding to a carrier to which AuSn solder (Au 70%, Sn 30%) is applied, die bonding is performed at a temperature slightly higher than the eutectic temperature of Au and Sn. At this time, the pressing pressure is about several kg / cm ² and the pressing time is about several seconds. Carrier material is diamond, Al
A material having high heat conductivity such as N or Si is generally used. The thickness of the solder applied to the carrier is usually from several to several tens of μm, preferably in the same order as the thickness of the electrode layer.

When the bonding strength of the die bonding is weak, peeling occurs at the bonding portion due to an external force, resulting in a lack of reliability.
In addition, if the bonding is unnecessarily strengthened, stress occurs at the bonding surface, which adversely affects device characteristics and device life. Therefore, there is an appropriate range of die bonding conditions. When the bonding strength is insufficient, the solder layer and the electrode layer are separated, but when the bonding strength is sufficient, the semiconductor element often breaks.

However, since the electrode surface of the device of the present invention has very few Group III elements as impurities and almost no oxide thereof, bonding conditions can be made relatively mild. Therefore, in the device of the present invention, the die bonding does not adversely affect the characteristics and life of the assembled device.

The surface electrodes of the LD chip die-bonded to the carrier are subjected to wire bonding. Generally, the material of the wire is Au, and its wire diameter is several tens.
μm. The conditions for wire bonding are generally such that an arbitrary ultrasonic wave is applied and the pressing load is about several tens g. In the device of the present invention, similarly to die bonding, bonding conditions can be made relatively mild, so that wire bonding does not adversely affect the characteristics and life of the device.

The LD assembled as described above is subjected to a destructive inspection and a nondestructive inspection. The destructive inspection is a strength test represented by a wire pull test and a die shear test. The wire pull test is a test in which an Au wire is hooked on a hook and pulled up to break the wire, and the mode of breaking and the breaking strength of the bonding portion are measured. The die shear strength test is a test in which a chip bonded to a carrier is pushed from a lateral direction (a direction parallel to the surface of the carrier), and a mode of breaking when the chip is peeled from the carrier and a breaking strength are measured.

The electrode surface of the device of the present invention has a low concentration of Group III impurities from the underlying semiconductor of 5% or less, so that the bonding strength on the carrier and the wiring strength on the surface electrode are improved. Is done. Further, in the electrode of the device of the present invention, it is not necessary to unnecessarily harden the conditions of the die bonding and the wire bonding, so that unnecessary damage is not given to the device. For this reason, since the assembling process does not adversely affect the life and characteristics of the element, the element of the present invention has a remarkable effect when connected to the carrier by solder containing Au.

In short, the superiority of the electrode of the device of the present invention is not limited to the fact that the group III element does not appear on the electrode surface in the process of forming the electrode. Group III elements do not appear on the surface, and constituent elements of the base electrode layer do not appear on the surface. Examples of the process of giving a thermal history include the above-mentioned alloying process performed after the electrode is formed, and the above-described coating process performed on the cleavage end face after the wafer is chipped into semiconductor elements. Incidentally, the present invention, after performing the heat treatment after the electrode formation,
It can also be applied as an overcoat electrode configuration for forming an electrode again.

[0048]

EXAMPLES Hereinafter, the present invention will be described in more detail with reference to examples, but the present invention is not limited to the following examples unless it exceeds the gist of the present invention. In the accompanying drawings used in the following description, FIG. 1 is an explanatory diagram of an epi structure of a laser diode (LD) employed in the first embodiment, and FIG.
Is an explanatory diagram of a double hetero (DH) structure employed in Example 1, FIG. 3 is an explanatory diagram of an LD obtained in Example 1, and FIG. 4 is an explanatory diagram of an LD obtained in Comparative Example 1.

Example 1 As a semiconductor laser wafer, as shown in FIG. 1, an n-type Al _0.7 Ga _0.3 As was formed on the surface of an n-type GaAs substrate (1).
(A carrier concentration of 7 × 10 ¹⁷ cm ⁻³ ) and p-type GaAs (carrier concentration of 5 × 10 ¹⁷ to ³ × 10 ¹⁷ cm ⁻³ ).
A wafer having a DH structure (2) provided with a contact layer (4) composed of 2 × 10 ¹⁹ cm ⁻³ ) was used.

As shown in FIG. 2, the DH structure (2) has n-type GaAs (carrier concentration of 1 × 10 ¹⁸ cm ⁻³ ).
Buffer layer (21) made of n-type Al _0.55 Ga _0.45
Cladding layer (22) made of As (carrier concentration: 5 × 10 ¹⁷ cm ⁻³ ); undoped p-type Al _0.15 Ga _0.85
Active layer (23) made of As, p-type Al _0.55 Ga _0.45 A
The cladding layer (24) made of s (carrier concentration of 5 × 10 ¹⁷ cm ⁻³ ) is sequentially laminated.

The surface of the semiconductor laser wafer (p
Top surface of n-type GaAs contact layer) and back surface (n-type GaAs
After forming the p-side and n-side electrodes on the (upper surface of the substrate) in the following manner, a heat treatment alloy was performed to form an ohmic contact electrode having a layer configuration shown in FIG.

First, in order to form a p-side electrode layer, AuZnN, which is an Au-containing layer, is formed as an ohmic contact layer (51) on the upper surface of the p-type GaAs contact layer by a vapor deposition machine.
i alloy layer (Au 90%, Zn 5%, Ni 5%, 150n
m) is formed thereon, and Ti is formed thereon as an impurity absorbing layer (6).
A layer (90 nm) was formed, a Pt layer (60 nm) was formed thereon as an impurity barrier layer (7), and an Au layer (5000 nm) was formed thereon as a surface layer (8).
However, by further forming an Au plating layer (6 μm) on the Au layer, the thickness of the Au layer was set such that the die bonding to the carrier was easily performed. At this time, a sulfurous acid-based plating solution was used as the Au plating solution, and a negative resist was used to form a resist pattern for patterning.

Then, for forming the n-side electrode layer, nG
An AuGeNi alloy layer (Au90%, Ge5%, Ni5) is formed on the aAs substrate as an ohmic contact layer (52).
%, 150 nm), a Ti layer (90 nm) is formed thereon as an impurity absorption layer (6), and a Pt layer (60 nm) is formed thereon as an impurity barrier layer (7). Au layer (400 nm) as layer (8)
Formed.

Next, alloying was performed at 400 ° C. for 5 minutes in nitrogen to form an ohmic contact electrode. That is, an ohmic contact electrode having a structure of AuZnNi alloy layer / Ti layer / Pt layer / Au layer is formed on the p side, and an AuGeNi alloy layer / Ti layer / Pt layer / Au layer is formed on the n side. An ohmic contact electrode was formed.

Next, the semiconductor wafer on which the ohmic contact electrode was formed was cleaved in a direction perpendicular to the direction of the resonator of the semiconductor laser to obtain a bar-shaped LD array. An Al ₂ O ₃ single layer or A
This was put into a coating process for forming a l ₂ O ₃ / Si multilayer film. The purpose of the coating is to adjust the reflectance at the LD end face and to protect the end face. In the coating process, the LD bar is subjected to a thermal history of about 350 ° C. for about 4 hours. The reason for applying heat during coating is to increase the adhesion between the semiconductor and the coating film and to form a high-quality coating film. Since the coating is performed on both end faces, a heat history of about 4 hours at about 350 ° C. is applied twice.

After the coating was completed, the LD bar was further cut into one element to obtain an LD chip. The LD chip has a 3 μm AuSn solder film (Au 70% Sn
(30%) was die-bonded to an AlN carrier coated with the same. Thereafter, an Au wire having a wire diameter of 25 μm was wire-bonded to the surface electrode of the LD assembled on the carrier. Then, the following tests (analysis) (1) to (3) were performed.

(1) Wire pull test and die shear test: The above test was performed on a part of a large number of assembled LD chips, and the quality of die bond and wire bond was evaluated. Table 1 shows the results.

(2) LD characteristic evaluation and life evaluation test: The above test was performed on the remaining LD chips. As a result, the LD characteristic was normal and there was no problem with the life.

(3) AES analysis: For the n-side Au surface electrode layer, the ratio of Au and impurities present on the outermost surface was analyzed by Auger electron spectroscopy (AES). The AES method is an excellent analysis method in elemental analysis of the outermost surface of a substance. The analysis target on the n side is p
This is because Au plating is applied to the side. Table 2 shows the results.

Comparative Example 1 Example 1 was repeated except that the impurity absorbing layer (6) and the impurity barrier layer (7) on the p-side and n-side electrodes were omitted, and the Au plating layer on the p-side was omitted. In the same manner as in the above, production, bonding and testing (analysis) of an LD chip were performed.

[0061]

[Table 1]

As can be seen from Table 1, in the conventional LD chip, the breaking mode in the wire pull occurs at the junction between the surface electrode layer and the wire at 20%, whereas in the LD chip of the present invention, 100% of the wire is broken. It can be seen that the electrode and the wire are firmly connected. Also,
Thus, the average value of the breaking strength of the LD chip of the present invention is higher than that of the conventional LD chip.

On the other hand, with respect to the die shear strength, in the conventional LD chip, the mode of peeling from the bonding surface between the AuSn solder and the Au electrode is 30%, whereas in the LD chip of the present invention, the chip is broken and the bonding portion of the electrode is broken. Is a destruction mode that remains while being bonded to the carrier, and sufficient bonding strength is obtained. Also, as shown in Table 1, the LD chip of the present invention shows a large value of the breaking strength.

[0064]

[Table 2]

As can be seen from Table 2, in the case of the conventional LD chip, Ga diffuses into Au on the electrode surface.
The diffusion of Ge and Ni from the base electrode was also confirmed. That is, in the case of the conventional LD chip, Ga of the group III element is present on the surface, and it is considered that oxygen (O) is present due to oxidation of this Ga. On the other hand, in the case of the LD chip of the present invention, Ga in the electrode is below the detection limit, and O hardly exists. Note that both LDs
C detected on the chip is considered to be C contained in the adhesive tape used when handling the element.

[0066]

According to the present invention, there is provided a III-V compound semiconductor device comprising:
With a simple electrode configuration, diffusion of a Group III element such as Ga to the electrode surface is effectively prevented, sufficient bonding strength is provided, and a great industrial advantage is provided.

[Brief description of the drawings]

FIG. 1 shows a laser diode (L) employed in Example 1.
Explanatory drawing of D) epi structure

FIG. 2 is an explanatory diagram of a double hetero (DH) structure employed in Example 1.

FIG. 3 is an explanatory diagram of an LD obtained in Example 1.

FIG. 4 is an explanatory diagram of an LD obtained in Comparative Example 1.

[Explanation of symbols]

1: n-type GaAs substrate 2: DH structure 21: n-type GaAs buffer layer 22: n-type Al _0.55 Ga _0.45 As cladding layer 23: undoped p-type Al _0.15 Ga _0.85 As active layer 24: p-type Al _0.55 Ga _0.45 As Cladding layer 3: n-type Al _0.7 Ga _0.3 As block layer 4: p-type GaAs contact layer 6: impurity absorption layer (Ti layer) 7: barrier layer (Pt layer) 8: surface layer (Au layer) 51: ohmic contact layer (AuZnNi alloy layer) 52: Ohmic contact layer (AuGeNi alloy layer)

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hideki Goto 1000 Higashi-kuana-cho, Ushiku-shi, Ibaraki Mitsubishi Tsukuba Works

Claims (8)

[Claims] An electrode layer is provided on a compound semiconductor layer.
A group III-V compound semiconductor device, wherein the electrode layer includes an Au-containing layer in contact with the compound semiconductor layer and a surface layer having a group III element content of 5% or less. . 2. The group III-V compound semiconductor device according to claim 1, wherein the compound semiconductor layer contains Ga as a constituent element, and the Ga content on the surface of the electrode layer is 5% or less. 3. A semiconductor device comprising an electrode layer on a compound semiconductor layer.
A III-V compound semiconductor device, wherein the electrode layer includes an Au-containing layer, an impurity absorbing layer, and a surface layer that are in contact with the compound semiconductor layer. 4. The impurity absorbing layer contains Ti.
A III-V compound semiconductor device according to [1]. 5. The group III-V compound semiconductor device according to claim 3, wherein the electrode layer further comprises an impurity barrier layer. 6. The III-V compound semiconductor device according to claim 5, wherein the impurity barrier layer contains a metal having a melting point of 1600 ° C. or higher. 7. The method according to claim 1, wherein the cleavage plane is coated at a temperature of 200 ° C. or higher.
Group V compound semiconductor element. 8. The method according to claim 1, wherein the electrode layer is connected to the carrier by a solder containing Au.
Group V compound semiconductor element.