JPH11262243A - Driving device for voltage-driven power element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving device for voltage-driven power element which is capable of adjusting miller time through a gate control, making the serial and parallel connection of a power element easier, and suppressing the surge overvoltages. SOLUTION: A driving device for voltage-driven power element is provided with means 56 and 58, which supply on-control voltages to the gate of a power element via a gate resistor 54, means 57 and 59 which supply off-control voltage to the gate terminal of an element 50 via the gate resistor 54, means 61 and 63 which supply an additional on-control signal, having a prescribed quantity of electricity to the gate via a second gate resistor 55 at a prescribed pulse width, when the on-control voltage is supplied to the element 50 and reaches a miller voltage, and means 62 and 64 which supply an additional off-control signal to the element 50 through the second gate resistor 55, when the on-control voltage drops to the miller voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device for a voltage-driven power device comprising a MOS gate input type power semiconductor device used for a main circuit of a converter or an inverter.

[0002]

2. Description of the Related Art As a voltage-driven power semiconductor device comprising a MOS gate input power semiconductor device, a power MO is used.
S FET, IGBT (Bipolar MOS FET),
SIT (static induction type transistor), IEGT (injection promotion insulated gate bipolar transistor) and the like are known. These power semiconductor elements having MOS-structured gates are characterized in that the switching operation is performed at high speed, and in addition, the switching waveform of the element voltage (collector-emitter voltage) Vce is adjusted by controlling the gate voltage Vg. It has the feature of being able to.
In recent years, individual IGBTs and IEGTs have been commercialized with high withstand voltage and large current elements, and using them, series-connected, parallel-connected, or snubberless power conversion without deteriorating one of the characteristics of the elements. Vessels are being sought. In configuring a power converter with a high withstand voltage by connecting a plurality of power elements that perform such high-speed switching operations in series and operating as if they were a single power element, individual Since there is a characteristic difference between the power elements, it is difficult to equalize the voltage of each element during the switching operation. Even when a plurality of elements are connected in parallel to increase the current, it is difficult to equalize the current of each element for the same reason. In addition, in a power element that performs a high-speed switching operation, a large surge overvoltage occurs when the element is turned off. Therefore, a technique for suppressing the surge overvoltage is important.

A conventional power converter using a voltage-driven power element, a large-capacity converter using a parallel-connected voltage-driven power element, and a GTO connected in series
An example of a high voltage power converter using (gate turn-off thyristor) will be described.

FIG. 11 shows an example of a main circuit of a power converter constituted by voltage-driven power elements and an associated circuit thereof. In FIG. 11, two sets of voltage-driven power elements 1P and 1N form a U-phase positive arm and a negative arm in a power converter main circuit, and both arms are connected in series at an intermediate connection point Vcn to provide a DC positive power. It is connected between the voltage terminal Vp and the DC negative voltage terminal Vn. Power elements 1P and 1N each have an emitter terminal E, a collector terminal C, and a gate terminal G. Each power element 1P, 1N also has a control circuit and snubber circuit 2 of the same configuration. The snubber circuit 2 includes a snubber capacitor 3, a snubber diode 4, and a snubber resistor 5, and is connected between the emitter terminal E and the collector terminal C of the power element 1. Each power element 1P, 1N
DC power source 10 between gate terminal G and emitter terminal E
Alternatively, when the switching element 12 or 13 is turned on from the DC power supply 11, a positive or negative switching gate signal voltage Vg is applied via the gate resistor 6 and the gate signal supply conductor 7. In the power element 1P on the positive side, the switch element 12 or 1
When the switch 3 is turned on, a positive ON control signal S1 or a negative OFF control signal S2 is generated, and the switch signal is applied to the gate terminal G via the gate resistor 6. Similarly, when the switch element 12 or 13 is turned on by the switch element control signal 9 in the negative power element 1N, a positive ON control signal S1 or a negative OFF control signal S2 is generated. The voltage is applied to the gate terminal G. As is well known, basically, the switch element control signals 8, 9 are interlocked with each other so that the power elements 1P, 1N on both the positive and negative sides are not simultaneously turned on. The gate signal supply conductors 7 for the power elements 1P and 1N are formed as a twisted pair.

FIG. 12 shows n voltage-driven power devices 14.
-1 to 14-n are connected in parallel via a positive electrode common conductor 21 and a negative electrode common conductor 22 to form one arm of the power converter (FIG. 1).
(Corresponding to one power element 1P). The power elements 14-1 to 14-n are
Or 20 is turned on so that the DC resistor 17 and the gate signal supply conductor 16
ON / OFF control by a common switching gate signal voltage applied via Also in this case, the switch elements 19 and 20 are reciprocally turned on and off by the switch element control signal 8.

FIG. 13 shows a connection example when one arm of the power converter is configured by connecting n GTOs in series. In the figure, one arm (power element 1 in FIG. 11)
P) corresponds to n GTOs 23-1 to 2 connected in series.
3-n. A freewheel diode 24, a snubber circuit 25 having the same configuration, and a voltage sharing resistor 26 are connected between the anode terminal A and the cathode terminal K of each GTO. Each GTO is provided with a gate signal supply circuit that is insulated from each other. Each of the gate signal supply circuits has the same circuit configuration. When the switch element 33 is turned on by a common ON control signal from a common ON control line 28, the DC power supply 30 receives the signal through the resistor 32 and the delay element 35. GTO23-1 ~
A positive ON control signal is applied to the gate terminal G of the GTO 23-n, and the switch element 34 is turned ON by the OFF common control signal from the common OFF control line 29. A negative off control signal is applied to the gate terminals G of -1 to 23-n.

In order to suppress the switching time and surge overvoltage of a power converter using a power semiconductor device, a method of reducing the resistance value of the gate resistor 6 and increasing the capacitance of the snubber capacitor 3 of the snubber circuit 2 shown in FIG. It is generally performed in. However, with such a method, it is difficult to manage the switching time and minimize the dead time. Moreover, regarding the snubber circuit, the space factor of the snubber circuit tends to be relatively large as compared with the device capacity.

Further, in the multiple parallel connection of the voltage-driven power elements shown in FIG. 12, each of the power elements 14-1 to 14-n
As a means for equalizing the distribution of the current flowing through the common conductors, the common conductors 21 and 22 for parallel connection are arranged opposite to each other in a shape having a sufficient surface area, and apparently the wiring circuit is minimized to reduce the wiring inductance. There is a known technique for achieving this. Problems with this method include an increase in manufacturing cost, an increase in the weight of the device, and difficulty in maintenance and inspection.

In the multiple series connection of the GTOs shown in FIG. 13, in order to equalize the shared voltages of the GTOs, the shared voltages are equalized by the snubber circuit 25 and the delay elements 35 and 36 in the transient state, and are equalized in the steady state. The sharing resistor 26 equalizes the sharing voltage. In the case of a series connection of relatively low-frequency switching elements such as GTO, voltage sharing is performed by setting a large capacitance of the snubber capacitor in the snubber circuit 25 or adjusting the delay time of the delay elements 35 and 36. Can be made equal. However, the time adjustment of the delay elements 35 and 36 is, for example, 1
In addition to the maintenance / inspection work at the rate of times / year, the space factor of the snubber circuit 25 in the power converter becomes large, which is not preferable.

Although not shown, series multiplexing of small-capacity power converters is also known as a measure for increasing the withstand voltage of a power converter using a high-frequency power switching element. In this case, the necessity of an insulated power supply or the like for each power converter undesirably complicates the device and increases the cost.

[0011]

In a power converter that performs high-speed switching by connecting voltage-driven power elements in series, a snubber circuit and a low-inductance main circuit structure are indispensable. The shared voltage of each power element when connected in series depends on the converter structure and the characteristics of the element. For this reason, in a power converter that performs high-speed switching, it is important to reduce the inductance of the main circuit wiring.

However, reducing the inductance of the wiring of the power converter not only increases the cost of the power converter but also makes maintenance and inspection difficult. Also, the capacity of a snubber circuit inserted to suppress surge overvoltage and improve the shared voltage at the time of series connection must be increased in proportion to the switching speed, so that the snubber loss increases and the converter Decrease efficiency.

Accordingly, an object of the present invention is to provide a driving device for a voltage-driven power element which can adjust a mirror time by gate control, facilitate direct / parallel connection of power elements, and suppress a surge overvoltage. .

Another object of the present invention is to provide a driving device for a voltage-driven power element capable of realizing a low-loss snubber circuit.

[0015]

According to a first aspect of the present invention, a first gate resistor is provided at a gate terminal of a voltage-driven power device comprising a MOS gate input power semiconductor device. Supply the on-control voltage via the first
A second gate signal supply means for supplying an off-control voltage to the gate terminal via the first gate resistor, and a gate voltage of the power element when the on-control voltage is supplied to the power element. Threshold value detection means for outputting a mirror voltage detection signal that rises when the mirror voltage is reached and falls when the off-control voltage is supplied to the power element and the gate voltage of the power element falls to the mirror voltage; Third gate signal supply means for additionally supplying an ON control signal having a predetermined pulse width and a predetermined amount to the gate terminal through a second gate resistor in response to a rise of the detection signal; A fourth gate signal that additionally supplies an off control signal of a predetermined amount of electricity with a predetermined pulse width to a gate terminal via a second gate resistor in response to the falling edge It is characterized in that it has and a feeding means. According to the present invention, when the power element is turned on, the turn-on operation is accelerated by injecting energy to reduce the turn-on loss. At turn off,
Since the dead time can be predicted by optimizing the mirror time, the delay time can be matched with the power element of another phase in the power converter.

According to a second aspect of the present invention, in the driving device for a voltage-driven power element according to the first aspect, means for adjusting the off-gate voltage supply time of the second gate signal supply means is provided. Is what you do. According to the present invention, the energy is injected when the snubber current flows during the turn-off operation, whereby the change rate dV of the element voltage is obtained.
Control of ce / dt and suppression of surge overvoltage become possible.

The invention according to claim 3 is the invention according to claim 1 or 2
Wherein the main circuit is constituted by a plurality of voltage-driven power elements connected in parallel, and the first and second gate signal supply means are connected to each of the voltage-driven power elements. Provided common to the elements,
And a fourth gate signal supply means is provided separately for each voltage-driven power element. According to this invention, in addition to the effect of the invention described in claim 1 or 2, it is possible to equalize the sharing of the current flowing through each power element.

According to a fourth aspect of the present invention, in the driving device for a voltage-driven power element according to the third aspect, the voltage-driven power element has a main emitter and a detection emitter for detecting an emitter current, and 4 gate signal supply means,
The present invention is characterized in that it operates so as to eliminate the timing deviation at the time of turn-on and at the time of turn-off of the two voltage-driven power elements with reference to the emitter current detection signals of the adjacent two-voltage driven power elements. According to this invention as well, the sharing of the current flowing through each power element can be equalized, as in the third aspect of the invention.

The invention according to claim 5 is the invention according to claim 1 or 2
Wherein the main circuit is constituted by a plurality of voltage-driven power elements connected in series, and the first to fourth gate signal supply means are connected to each of the voltage-driven power elements. It is provided separately for the element, and the first and second gate signal supply means are driven based on a common control signal. According to the present invention, the voltage sharing of each power element can be made equal.

According to a sixth aspect of the present invention, in the driving device for a voltage-driven power element according to the fifth aspect, a snubber circuit is connected to each of the plurality of voltage-driven power elements, and the adjacent two voltage-driven power elements are connected. Current detecting means for detecting the difference between the currents flowing through the two snubber circuits attached to the power element, and the third and fourth gate signal supply means reduce the difference current detected by the differential current detecting means. As described above, the present invention is characterized in that the timing shift at the time of turn-on and at the time of turn-off of the attached voltage-driven power element is adjusted. According to the present invention as well, the voltage sharing of each power element can be made equal.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Configuration of Embodiment) (Operation of Embodiment) Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) (corresponding to claim 1) FIG. 1 shows an example of a configuration of an arm unit of a power converter according to a first embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation. It is a time chart.

The voltage-driven power element 50 shown in FIG. 1 has a collector terminal C, an emitter terminal E, and a gate terminal G. A snubber circuit 40 is connected between the collector terminal C and the emitter terminal E. The snubber circuit 40 includes a snubber diode 41 and a snubber capacitor 4 connected in series.
2 and a snubber resistor 43 connected in parallel with the diode 41. Collector terminal C is connected to DC positive voltage terminal Vp, and emitter E is connected to intermediate connection point Vcn. By turning on the switch element 56 between the gate terminal G and the emitter terminal E of the power element 50, a positive ON control signal S1 is applied from the DC power supply 58 via the gate resistor 54, and the switch element 57 is turned ON. By doing so, the negative off control signal S2 is applied from the DC power supply 59 via the gate resistor 54. The switch elements 56 and 57 are driven by the switch element control signal 60 such that the switch elements 56 and 57 perform a reciprocal operation so that when one is on, the other is off.

To the gate terminal G of the power element 50, in addition to the switching signal supplied through the gate resistor 54, a switching signal supplied through the gate resistor 55 is additionally supplied. That is, the switch element 61
Is turned on, the DC power supply 63 supplies the gate resistance 5
5, a positive ON control signal S3 is applied, and when the switch element 62 is turned ON, a negative OFF control signal S4 is applied from the DC power supply 64 via the gate resistor 55. To control the switch elements 61 and 62, a threshold detection circuit 51 including a resistor 66, a reference power supply 67 and a comparator 68 is provided.
The reference voltage from the reference power supply 67 is input to the reference input terminal of the comparator 68, and the gate voltage V from the gate terminal G of the power element 50 via the diode 65 to the comparison input terminal.
g is input. The comparator 68 detects and outputs the mirror voltage of the gate voltage Vg as a threshold value. The mirror voltage detection signal Vml is subjected to logic processing by the logic processing circuit 69, the switch element 61 is turned on by the first output signal V1 via the drive circuit 70, and the drive circuit 71 is turned on by the second output signal V2. The switch element 62 is turned on via the switch. The DC power supplies 63 and 64
Is an adjustable power supply.

In FIG. 2, (a) shows the voltage between the gate terminal G and the emitter E, that is, the gate voltage Vg, and the gate current Ig flowing through the gate terminal G of the power element 50 when an inductive load is connected to the power converter. , (B) shows the mirror voltage detection signal Vml of the threshold detection circuit 51,
(C) shows the first output signal V1 of the logic processing circuit 69, that is, the S3 control signal, and (d) shows the second output signal V2 of the logic processing circuit 69, that is, the S4 control signal. As can be seen from FIG. 2, the threshold value detection circuit 51 detects the rise of the mirror voltage at time t1 based on the gate voltage Vg, raises the mirror voltage detection signal Vml, and detects the fall to the mirror voltage at time t3. Then, the mirror voltage detection signal Vml falls. The first output signal V1 of the logic processing circuit 69 continues from a time delayed by a predetermined time (here, zero) from the rising time t1 of the mirror voltage detection signal Vml as a base and continues for a predetermined time width from there to time t2. The second output signal V2 of the logic processing circuit 69 continues for a predetermined time width from time t4, which is a predetermined time delay from the falling time t3 of the mirror voltage detection signal Vml, to time t5. Here, the predetermined time width is determined according to the amount of additional electricity injected into the gate as described later.

When the power element 50 shown in FIG. 1 is turned on, the switch element 56 is turned on, and a positive ON control signal S1 is supplied from the DC power supply 58 to the gate terminal G via the gate resistor 54, so that the power element 50 is turned on. Turn on. The gate voltage Vg is supplied to the comparator 68 via the diode 65.
, Which detects the mirror voltage when the power element 50 is turned on as a threshold, and outputs a mirror voltage detection signal Vml. The logic processing circuit 69 generates the first output signal V1 based on the rise of the mirror voltage detection signal Vml output from the comparator 68. This output signal V1 is power-amplified by the drive circuit 70 and turns on the switch element 61. When the switch element 61 is turned on, the DC power 63
The energy adjusted to an appropriate amount is supplied to the gate of the power element 50 via the gate resistor 55 as the gate control signal S3. The gate voltage Vg at this time
Is a signal supplied through a gate resistor 54 and a resistor 55
Are added at the gate terminal G.

Next, when the power element 50 is turned off, the switch element 57 is turned on to apply a negative voltage from the DC power supply 59 to the gate terminal G of the power element 50 via the gate resistor 54. At this time, the output signal of the threshold detection circuit 51 drops to zero at time t3 due to the negative OFF control signal of the gate terminal G, and the logic processing circuit 69 has a slight time delay based on the fall of this output signal. The second output signal V2 having an appropriate time width (time t4 to t5) is output. The output signal V2 is power-amplified by the drive circuit 71, and turns on the switch element 62. Switch element 6
When the power supply 2 is turned on, the energy adjusted to an appropriate amount of electricity of the DC power supply 64 is applied as a gate control signal S4 to the gate terminal G of the power element 50 via the gate resistor 55 to discharge the input capacitance. The mirror time of the power element 50 is adjusted.

As described above, when the power element 50 is turned on, the gate voltage Vg can be increased to speed up the turn-on operation of the power element 50. When the power element 50 is turned off, the turn-off time can be freely adjusted. The switching timing of the power elements constituting each arm of the power converter used as a converter can be matched. Thereby, the dead time of the power element can be minimized. (Second Embodiment) (corresponding to claim 2) FIG. 3 shows a second embodiment of the present invention, and FIG. 4 shows a time chart of control signals.

In FIG. 3, the same components as those of the driving device of FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.
Here, the switch elements 56 and 57 are not directly controlled by the control signal 60 but are indirectly controlled. In other words, the DC power supply 5 connected in series
8, 59, that is, a resistor 74, a resistor 75 and a switch element 73 are connected in series to both ends of the switch elements 56 and 57, and a switch element 72 is connected in parallel to the resistor 75 and the switch element 73. Resistance 74, 75
ON / OFF of the switch elements 56 and 57 is controlled by the voltage at the connection point of. The switch element 72 is always in the ON state, and when the switch element control signal 60 turns it “1”.
At this time, it is turned on, and when it is "0", it is turned off.
The switch element 73 outputs the output signal V of the logic processing circuit 76.
3 is turned on by the drive signal V6 obtained via the drive circuit 77. As shown in FIG. 4E, the control signal 60 is a signal that keeps the ON state from time t1 when the ON command is given to the power element 50 to time t4 when the OFF command is given. Control signal for controlling the on / off of the normally closed switch element 72 via the exclusive OR circuit 78 directly. After a fall of the control signal 60, the logic processing circuit 76 outputs the output signal V
3 and the output signal V4 at the same time or with a slight delay from that. This output signal V4 is input to the second input terminal of the exclusive OR circuit 78. The output signals V3 and V4 of the logic processing circuit 76 are related to the enhancement of the gate signal injection at the time of the OFF operation to the power element 50, and are turned off at a time t9 slightly after the falling time t8 of the control signal S4.

4A shows the gate voltage Vg and the collector-emitter voltage when an inductive load is connected, that is, the element voltage Vce, and FIG. 4B shows the mirror voltage detection signal Vml obtained as the output of the comparator 68.
(C) and (d) show output signals of the logic processing circuit 69, that is, first output signals V1 and V2 for generating the control signals S3 and S4, and (e) shows a drive signal 60 for the switch element 72, respectively. It is shown. FIG. 4F shows a drive signal V6 for the switch element 73 generated corresponding to the output signal V3 of the logic processing circuit 76.

When the power element 50 shown in FIG. 3 is turned on, the output signal V4 of the logic processing circuit 76 is "0", and the control signal 60 is turned on ("1") to output the signal via the NAND circuit 78. The switch element 72 is turned off.
As a result, the switch element 56 is turned on, and the DC power 58
To turn on the power element 50 by applying an ON control signal to the gate terminal G of the power element 50 via the gate resistor 54. Gate control of the power element 50 by the switch element 61 and the DC power supply 63 at the time of turn-on (see FIG. 4C) is the same as that of the first aspect.

When the power element 50 is turned off, the control signal 60 is turned off ("0") so that the switch element 7 is turned off.
2 is turned on, thereby turning off the switch element S1 and turning on the switch element S2. An off control signal is supplied from the direct current 59 to the gate terminal G of the power element 50 via the gate resistor 54 as in the case of claim 1. The power element 50 is turned off. At this time, adding an additional gate control signal from the DC power supply 64 by the logic processing circuit 69 (see FIG. 4D) is no different from the case of the first aspect.
The logic processing circuit 76 monitors the fall of the signal V5, and after a predetermined time, that is, a time width until the end of the rise of the element voltage Vce when the power element 50 is turned off (FIG. 4 (f): t6 to t8). ) Considering the time t
6, a pulse signal V3 is generated, and the pulse signal V3 is turned on for a while through the drive circuit 77. At the same time, the switch element 72 which has been once turned on is output via the exclusive OR circuit 78 by the output signal V4. Off, meanwhile, by the voltage dividing ratio of the voltage divider constituted by the resistor 74 and the resistor 75,
The gate voltage Vg of the power element 50 is kept at a certain value. The switch element 62 is turned on from the start of the turn-off of the element voltage Vce by the output signal V2 of the logic processing circuit 69 to the jump voltage, and the energy of the DC power supply 64 is transferred to the gate of the power element 50 via the gate resistor 55. By implanting, the rate of change dV of the element voltage Vce
By adjusting ce / dt, the jump voltage can be suppressed. (Third Embodiment) (corresponding to claim 3) FIG. 5 shows an embodiment of a driving device for a unit arm of a main circuit of multiple parallel connection. Here, MOS
A unit arm of a main circuit in which n power elements 80-1 to 80-n each composed of a gate input type power semiconductor element are multiplexed and connected via a positive-side common conductor 21 and a negative-side common conductor 22 is shown. I have. Each drive device attached to each power element has the same circuit configuration. When the switch element 82 is turned on in accordance with the on / off state of the switch element 82 or 83 controlled by the control signal 60, the gate resistance is changed from the DC power supply 84. A positive gate control signal is applied in common to the gate terminal of each power element via 81, and the switch element 83 which operates in a reciprocal manner with the switch element 82 is turned on. Is commonly applied to the gate terminals of the power devices. The mode of the on / off operation of each power element is the same as that of the first embodiment described with reference to FIG.

In the main circuit shown in FIG. 5 in which a plurality of power elements are multiplexed and connected in parallel, the gate resistance 81 is increased by a gate drive circuit including switch elements 82 and 83 and DC power supplies 84 and 85 whose output power is enhanced. The switching operation is performed all at once. With this control, when the power element is turned on, the turn-on operation is accelerated as in the first embodiment, the delay at the time of turn-on is corrected and improved, and the mirror time of the power element is simultaneously adjusted at the time of turn-off. Since the delay due to the capacitance storage time of the elements can be corrected and improved, the current imbalance between the elements at the time of multiple parallel connection of the power elements can be reduced. (Fourth Embodiment) (Corresponding to Claim 4) FIG. 6 shows three power devices 86-1 and 86- composed of a MOS gate input type power semiconductor device having a double emitter structure.
This shows an embodiment in which a unit arm is configured by connecting 2, 86-3 in parallel, and a logic processing circuit 88 corresponding to the unit arm is provided. Other circuit parts are the same as those in FIG. Power elements 86-1 to 86-3 include a main emitter through which an emitter current flows and a detection emitter for detecting an emitter current. The detection emitter of each power element is a resistor 87
The operation is performed by obtaining an operation power supply from the CPU, and the detection signal is input to the logic processing circuit 88. However, in principle, each logic processing circuit 88 receives the detection signals from the detection emitters of the two adjacent power elements, detects the operation time difference between the two elements, that is, the delay time difference, and adjusts so as to eliminate the difference. Operate. Therefore, the logic processing circuit 88 attached to the power element 86-3 includes both power elements 86-3 and 86-.
The gate current detection signals from the power elements 86-2 and 86-1 are input to the logic processing circuit 88 attached to the power element 86-2.

FIG. 7 is a time chart for explaining the operation of the device shown in FIG. 6, wherein (a) shows the gate voltage Vg in the case of an inductive load, and (b) shows the gate voltages of the power elements 86-1 and 86-2. FIG. 3C shows a state of a deviation between the element currents Ic1 and Ic2 caused by the characteristic difference, and FIG. 4C shows a delay time difference detection signal representing a delay time difference (t1 to t2) between the two element currents at the time of turn-on;
(D) is the delay time difference (t3
To t4) respectively.

In a main circuit shown in FIG. 6 in which double-emitter type power elements are multiplexed, current states of power elements adjacent to each other are compared based on an emitter current signal detected by a detection emitter to eliminate the difference. , The switching delay can be corrected in real time, and the current imbalance of the multiple parallel connection of the double-emitter power elements can be reduced. (Fifth Embodiment) (Corresponding to Claim 5) FIG. 8 shows a unit arm of a main circuit in which n power elements 89-1 to 89-n are connected in multiplex series. In the figure, a sharing resistor 90 for equalizing the sharing voltage is connected to each power element. The reference numerals of the other circuit parts are the same as in the first embodiment. In this embodiment, each of power elements 89-1 to 89-n has a common control signal 6
On / off control is performed by 0.

In the main circuit composed of n power elements constituting the unit arm shown in FIG. 8, a control circuit similar to that of FIG. 1 is attached to each of the power elements 89-1 to 89-n, and a switch is provided by a control signal 60. Power element 8 via element 56
9-1 to 89-n are simultaneously turned on, or power elements 89-1 to 89-n are simultaneously turned off via switch element 57. In that case, additional gate control similar to the embodiment of FIG. 1 is performed near the mirror voltage of the power element. By this control, at the time of turn-on, the turn-on operation of all the power elements is accelerated, and the delay at the time of turn-on is corrected and improved. At the time of turn-off, the mirror time can be adjusted at the same time. Therefore, the voltage imbalance between the power elements when a plurality of power elements are connected in multiplex series can be reduced. Although not shown, a reduction in the capacity of the snubber circuit (see FIG. 1) can be achieved by reducing the voltage imbalance. (Sixth Embodiment) (Corresponding to Claim 6) FIG. 9 shows a configuration in which three power elements 91-1 to 91-3 are connected in series to form a unit arm, and each power element is A snubber circuit 92 having the same configuration as that of the first embodiment is connected in parallel, and a resistance circuit composed of a shared voltage equalizing shared resistor 93 and a series voltage dividing resistor 94 is connected in parallel. The logic processing circuit 96 attached to each power element includes a comparator 68 related to the detection of the gate voltage Vg described above.
, A voltage signal representing the voltage at the connection point of the resistors 93 and 94, and both adjacent signals detected by a current detector 95 inserted in a circuit portion connecting the snubber circuit 92 and the corresponding power element. A current difference signal is introduced that represents the difference between the currents of the snubber circuits. Other circuit portions are the same as those of the first embodiment shown in FIG.

FIGS. 10A and 10B are time charts for explaining the control operation of the circuit device of FIG. 9, wherein FIG. 10A shows the gate voltage Vg in the case of an inductive load, and FIG. , The element voltages Vce1 of the power elements 91-1 and 91-2.
Vc shows a deviation, and (c) shows a current difference signal Is detected by the current detector 95.

The power elements 9 connected in multiplex series shown in FIG.
In the arm main circuit composed of 1-1 to 91-3, the element voltage Vce is detected by the voltage dividing resistor 94, and the unbalanced current is detected by the current detector 95. A control circuit including this and the circuit means shown in FIG. 8 is attached to each of the power elements 91-1 to 91-3, and the respective power elements are simultaneously turned on / off by the switch element control signal 60, and at the same time, The control described in the embodiment of FIG. 1 is performed near the mirror voltage. This control speeds up the turn-on operation of all power devices at turn-on, corrects and improves the delay at turn-on, and monitors the unbalance and controls the appropriate mirror time width at turn-off to enable multiple series connection of power devices. The voltage imbalance at the time can be reduced. A reduction in the capacity of the snubber circuit can be achieved accompanying a reduction in the voltage imbalance.

[0038]

According to the present invention, by controlling the device voltage and device current at the time of switching through the gate control of the power device, the turn-on time is shortened at the time of turn-on, and the mirror is controlled by controlling the mirror time width at the time of turn-off. Time can be optimized. Furthermore, by controlling the snubber operation, the surge overvoltage is suppressed, the switching delay is optimized, and the snubber circuit is reduced in capacity or snubberless.
Equalization of the voltage sharing of each element of the multiple series connection and the current sharing of the multiple parallel connection can be easily achieved with a low snubber capacity. This makes it possible to reduce the size, weight, and cost of the power converter.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing an embodiment of the invention according to claim 1;

FIG. 2 is a time chart for explaining the operation of the apparatus shown in FIG. 1;

FIG. 3 is a connection diagram showing an embodiment of the invention according to claim 2;

FIG. 4 is a time chart for explaining the operation of the device shown in FIG. 3;

FIG. 5 is a connection diagram showing an embodiment of the invention according to claim 3;

FIG. 6 is a connection diagram showing an embodiment of the invention according to claim 4;

FIG. 7 is a time chart for explaining the operation of the apparatus shown in FIG. 6;

FIG. 8 is a connection diagram showing an embodiment of the invention according to claim 5;

FIG. 9 is a connection diagram showing an embodiment of the invention according to claim 6;

FIG. 10 is a time chart for explaining the operation of the apparatus shown in FIG. 9;

FIG. 11 is a connection diagram showing a conventional driving device for a power converter.

FIG. 12 is a connection diagram of a conventional power converter including a power element in which unit arms are multiplexed and connected in parallel.

FIG. 13 is a connection diagram of a conventional power converter configured by power elements in which unit arms are connected in multiple series.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Positive-side common conductor 22 Negative-side common conductor 40 Snubber circuit 50 Voltage-driven power element 51 Threshold detection circuit 54, 55 Gate resistance 56, 57 Switch element 61, 62 Switch element 58, 59 DC power supply 60 Switch element control signal 63, 64 DC power supply 68 Comparator 69 Logic processing circuit 70, 71 Drive circuit 72, 73 Switch element 74, 75 Resistance 76 Logic processing circuit 77 Drive circuit 78 AND circuit 79 Logic processing circuit 80-1 to 80-n Voltage driven power Element 82, 83 Switching element 84, 85 DC power supply 86-1 to 86-3 Voltage driven power element 88 Logic processing circuit 89-1 to 89-n Voltage driven power element 91-1 to 91-3 Voltage driven power Element 92 Snubber circuit 95 Current detector 96 Logic processing circuit

Claims (6)

[Claims] A first gate signal supply means for supplying an on-control voltage to a gate terminal of a voltage-driven power element comprising a MOS gate input type power semiconductor element via a first gate resistor; and the gate terminal A second gate signal supply means for supplying an off control voltage to the power element via the first gate resistor, and a gate voltage of the power element reaches a mirror voltage when the on control voltage is supplied to the power element. Threshold value detection means for outputting a mirror voltage detection signal that rises when the off-control voltage is supplied to the power element and falls when the gate voltage of the power element falls to the mirror voltage, and the mirror voltage detection An ON control signal having a predetermined pulse width and a predetermined amount of electricity is additionally supplied to the gate terminal via a second gate resistor in response to a rise of the signal. And a gate signal supply means for supplying an off control signal having a predetermined pulse width and a predetermined amount to the gate terminal through the second gate resistor in response to a fall of the mirror voltage detection signal. A driving device for a voltage-driven power element, comprising: fourth gate signal supply means. 2. The voltage-driven power device driving device according to claim 1, further comprising means for adjusting an off-gate voltage supply time of said second gate signal supply means. Device driving device. 3. A driving device for a voltage-driven power element according to claim 1, wherein a main circuit is constituted by a plurality of voltage-driven power elements connected in parallel, and said first and second power-elements are connected to each other. The gate signal supply means is provided in common for each voltage-driven power element, and the third and fourth gate signal supply means are separately provided for each voltage-driven power element. A driving device for a voltage-driven power element. 4. A driving apparatus for a voltage-driven power element according to claim 3, wherein said voltage-driven power element has a main emitter and a detection emitter for detecting an emitter current, and said third and fourth gate signals. A voltage driving device, wherein the supply means operates so as to eliminate a timing deviation at the time of turn-on and at the time of turn-off of the dual-voltage driven power element with reference to an emitter current detection signal of an adjacent dual-voltage driven power element. Driving device for power devices. 5. A driving apparatus for a voltage-driven power element according to claim 1, wherein a main circuit is constituted by a plurality of voltage-driven power elements connected in series, and said first to fourth elements are connected to each other. Is provided separately for each voltage-driven power element, and the first and second gate signal supply means are driven based on a common control signal. Driving device for power element. 6. A driving device for a voltage-driven power element according to claim 5, wherein a snubber circuit is connected to each of said plurality of voltage-driven power elements, and said plurality of voltage-driven power elements are attached to adjacent two voltage-driven power elements. Current difference means for respectively detecting the difference between the currents flowing through the two snubber circuits.
And the fourth gate signal supply means adjusts the timing shift at the time of turn-on and turn-off of the attached voltage-driven power element so that the difference current detected by the difference current detection means decreases. A driving device for a voltage-driven power element.