JPH11260878A - Semiconductor device and its defect prediction mechanism - Google Patents

Abstract

PROBLEM TO BE SOLVED: To predict and avoid defect of humidity resistance and defect of electromigration, etc., of a semiconductor device by providing a defect prediction signal terminal to an outer terminal through a defect prediction circuit consisting of an Al wiring, a detection signal preparation circuit, a resistance element, etc., interposed. SOLUTION: A semiconductor element circuit part 12 is constituted and resistance elements 14a to 14d and a detection signal preparation circuit are incorporated in the semiconductor element circuit part 12. Wiring is carried out so that an Al wiring 9 passes through a part which is close to an outermost circumference of a semiconductor element 4 to the utmost and one or a plurality of wires are arranged parallel without coming into contact with each other to enclose the semiconductor element 4 almost one and half turns. For example, when an Rc-Rd Al wiring is disconnected, V1='L→H', and Vo='L' is outputted. When shortcircuiting occurs in an Al wiring, V1=V2='H' and Vo='L' is outputted. That is, when Vo='H', the device is normal and when Vo='L', it is judged something is wrong with the device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device and an electronic apparatus using the same.

[0002]

2. Description of the Related Art As a method of estimating a defect of a semiconductor device, there is a method of estimating a life by performing an accelerated test, but it is necessary to prepare a test circuit / program for each semiconductor device in order to execute a test. . In addition, it takes an enormous amount of time to obtain test results, and long-term testing is not possible for PCs (personal computers) and home appliances, where the competitiveness of the product is lost unless new parts are used early. It has begun to be omitted. On the other hand, in semiconductor devices, the miniaturization of packages and the miniaturization of processes have progressed, and new reliability problems have emerged.

[0003] At present, it is known only when a defect is found that a product such as a PC causes an abnormal operation during an inspection process or during use by a user, and it is not easy to identify a semiconductor device in which the defect has occurred.

Japanese Patent Application Laid-Open No. 9-162359 discloses a method for predicting and avoiding a reliability failure of a semiconductor device.
A reliability evaluation element composed of an S capacitor or the like is provided, and a failure is predicted / avoided based on the detection signal.

[0005]

In recent years, semiconductor devices have been increasingly miniaturized in packages and finer in process, and the reliability problems due to these have become more serious.

One of them is a problem of moisture resistance. Currently, the metal used for wiring on the chip is low resistivity / adhesion with silicon (Si) or silicon dioxide (SiO2) layer /
Aluminum (Al) is used in terms of pattern workability / ease of vapor deposition / availability / low cost. On the other hand, aluminum wiring has a disadvantage that it is broken by corrosion due to moisture. For the purpose of protecting the aluminum wiring from moisture, the upper layer of the chip is covered with a passivation layer 19 having excellent moisture resistance as shown in FIG.

In view of the miniaturization of the package of a semiconductor device, a QFP (QP) as shown in FIG.
The uad Flat Package is becoming thinner and smaller, and a BGA (Ball Grid) as shown in FIG.
Array) has recently become widely used. In these packages, since the resin thickness of the package resin 1 that mechanically protects the chip 4 is small, cracks 2 are generated in the package 1 as shown in FIGS. Or the chips themselves may crack.

[0008] The impact at this time covers the upper surface of the chip,
If the passivation film 19 is destroyed, moisture penetrates through the cracks 2 and breaks due to short circuit between chip patterns or corrosion of Al wiring. Even if the crack 2 does not occur in the package resin 1, if the passivation film 19 has a defect, if the material of the package resin 1 is a plastic package, moisture permeates, so that similar corrosion may progress. Conceivable.

In terms of miniaturization of semiconductor elements, there is FC (flip chip) mounting as shown in FIG. In the FC mounting, since the semiconductor element 4 is directly mounted on the printed circuit board 17 by the bumps 16, the semiconductor element 4 is easily affected by stress due to a difference in thermal expansion coefficient. The thermal expansion coefficient of the printed circuit board 17 is about four times that of the semiconductor element 4. In the case of FC mounting, the stress is directly applied to the bump 16 and the semiconductor element 4. Therefore, the stress is dispersed by the epoxy-based sealing resin 15. . However, due to repeated application of stress or deterioration of the sealing resin 15, the sealing resin 15
In the case where cracks occur, corrosion of the aluminum wiring due to moisture occurs as described above. Also, by repeating the stress,
Fatigue disconnection of the Al wiring called stress migration may occur.

Another problem is electromigration. The mechanism of electromigration is well known. When a current flows through the Al wiring, Al ions move in the direction in which electrons flow, and if this state is continued for a long time, voids are generated on the cathode side. It is a disconnection. Conversely, whiskers are generated on the anode side, and when the whiskers progress, eventually, dielectric breakdown (short circuit) occurs. This phenomenon progresses as the current density of the Al wiring increases.

[0013] In order to increase the degree of integration of semiconductor devices year by year, the miniaturization of the process is progressing. As the Al wiring becomes thinner and the cross-sectional area becomes smaller, the current density tends to increase.
For this reason, the problem of electromigration has been highlighted.

With respect to the above-mentioned two problems relating to the Al wiring, namely, corrosion due to moisture and electromigration, it is possible to predict a defect and specify a defective portion without using a complicated circuit or program.

As a method of predicting and avoiding a reliability failure of a semiconductor device, there is Japanese Patent Application Laid-Open No. Hei 9-162359.
A reliability evaluation element composed of an OS capacitor or the like is provided.
This detection signal is used to predict / avoid defects.
Such an element for evaluating reliability is an MO as shown in FIGS.
Since the S structure itself is used, the detection rate is, in other words, the chip area used for the detection circuit with respect to the entire chip area. In order to increase the detection rate, an enormous number of detection circuits are required, which is not practical.

[0014]

To briefly explain the outline of a typical one of the present invention, a semiconductor device has a semiconductor element circuit portion in the center of a semiconductor element, and an Al wiring / detection signal from the semiconductor element circuit. A failure prediction signal terminal is provided to an external terminal via a failure prediction circuit including a creation circuit / resistance element.

Further, according to the present invention, the Al wiring, which constitutes the failure prediction circuit, is wired so as to pass through a portion as close as possible to the outermost periphery of the semiconductor element. Multiple pieces are provided in parallel without contact.

Further, according to the present invention, the Al wiring is connected to the power supply or the ground of the semiconductor element circuit via the resistance element, and is set so that a current always flows in a fixed direction. The thickness and the current density of the Al wiring constituting the failure prediction circuit are provided to be substantially the same as the thickness and the current density of the Al wiring used in the semiconductor element portion.

A detection signal generation circuit composed of logic is provided at the terminal end of the Al wiring, and a detection signal is provided as an output thereof. The voltage of the Al wiring is set to be "H" or "L" at the logic level so as to leave the threshold voltage region of the detection signal generation circuit, and if the Al wiring is open or short-circuited with the adjacent Al wiring, It is provided to change from “H → L” or “L → H” at the level. It is provided that the detection signal is output from the detection signal generation circuit by this change.

There is a method in which the detection circuit is directly output to the outside through an input / output terminal of the semiconductor device or temporarily stored in a failure prediction bit of an internal register of the semiconductor device.
In the case of the method of temporarily storing in the failure prediction bit, the detection signal is stored in the detection signal latch circuit by the latch signal output from the detection signal reading controller, and enters the failure prediction bit in a specific register. The information of this register is provided so as to be output by a read command from outside similarly to the reading of other registers.

According to the present invention, the failure prediction bit is periodically monitored by the firmware of the product, and if any one of the plurality of semiconductor devices changes the failure prediction bit, an alarm is output via a monitor or the like. It is configured as follows.

[0020]

(Embodiment 1) FIGS. 1 and 2 are views showing a semiconductor element portion of a semiconductor device according to an embodiment of the present invention. The semiconductor element circuit portion is a part constituting a semiconductor operation circuit, and will be described below with a general CMOS structure. However, the present invention is not limited to the semiconductor device process structure. A general CMOS structure has a cross-sectional structure as shown in FIGS. 6 and 7, and forms a circuit that realizes a semiconductor function based on the CMOS structure.

The CMOS structure shown in FIGS. 6 and 7 has a G (gate) 25, an S (source) 26, and a D (drain) 27 constituting a PMOS on an n-type silicon 23, and a p-well 24.
A PMOS-NM has a G (gate) 25, an S (source) 26, and a D (drain) 27 which constitute an NMOS on the top.
Only the necessary portions of the OS are electrically connected by the interlayer insulating film 22 and the aluminum wiring 20. Aluminum wiring has low resistivity / silicon (Si) or silicon dioxide (SiO2)
Aluminum (Al) is used in terms of adhesion to the layer / pattern processability / ease of deposition / availability / low cost. On the other hand, aluminum wiring has a disadvantage that it is broken by corrosion due to moisture. As shown in FIGS. 6 and 7, the upper layer of the chip is covered with a passivation layer 19 having excellent moisture resistance for the purpose of protecting the aluminum wiring from moisture.

The semiconductor element circuit section 12 shown in FIG. 1 is constructed from the above CMOS structure, and the resistance element 14 shown in FIG.
a to 14d and a detection signal generation circuit are provided in the semiconductor element circuit section 12, and are arranged so that the Al wiring 9 passes through a portion as close as possible to the outermost periphery of the semiconductor element 4 so as to substantially surround the semiconductor element 4 around the circumference. , One or more are provided in parallel without contact. Resistance elements 14a to 14d
It is desirable that the resistance value and the Al wiring are set in the following points.

The Al wiring 9 shown in FIG.
The width of the wiring is the same as that of the Al wiring 20 of FIG. When wiring a plurality of Al wirings 9 in FIG.
Al wiring 2 of FIG. 7 wired to the semiconductor element circuit section 12
0 is the same as the wiring interval. A constant current flows in the Al wiring 9 in FIG. 1 in a fixed direction, and the current value is a value approximating the maximum value of the current density of the Al wiring 20 in FIG. The voltage of the Al wiring 9 in FIG. 1 is set so as to be outside the threshold voltage region of the detection signal generation circuit 29, that is, set to logic “H” or “L”, and the Al wiring 9 in which the Al wiring 9 is open or close to each other. When short-circuited, the logic level changes from “H → L” or “L →
H ”.

Taking the above term as an example in FIG. 2, the input characteristics of the detection signal creation circuit 29 in FIG. 2 are VIH (input high voltage),
Assuming that the current flowing through the Al wiring is I (A) and the power supply voltage is Vcc (V) as VIL (input low voltage), a resistance value that satisfies the following equation can be considered as an example.

From the current value, Vcc / (Ra + Rb) =
I, Vcc / (Rc + Rd) = I A between Rc and Rd
When the voltage of the l wiring is set to VIL or less, Rc / (Rc
+ Rd) × Vcc ≦ VIL When the voltage of the Al wiring between Ra and Rb is set to VIH or more, Rb / (Ra + Rb)
× Vcc ≧ VIH When a short circuit occurs between Al wirings,
When the voltage of the Al wiring is set to be equal to or higher than VIH,
((Rb // Rc) / (Rb // Rc) + (Ra // R
d)) × Vcc ≧ VIH. When short circuit
Since it is conceivable that an overcurrent flows in the wiring, the resistance value should be determined so as not to be damaged by heat generation or the like.

In the circuit of FIG. 2 set as described above, when the Al wiring is normal, V1 = “H”, V2 = “L”, and Vo = “H” is output. V1 = “H → L” when the Al wiring is disconnected,
Vo = “L” is output. When the Al wiring between Rc and Rd is broken, V1 changes from “L → H” and Vo =
“L” is output. When a short circuit occurs between the Al wirings, V1 = V2 = “H” and Vo = “L” is output.
That is, in the case of the circuit of FIG. 2, when Vo = "H", it is possible to determine that it is normal and when "L", it is possible to determine that an abnormality has occurred.

For the purpose of mechanically protecting the semiconductor element 4,
Like the SOP / QFP in FIG. 3 and the BGA in FIG. Every year thinner /
As the miniaturization progresses, the resin thickness of the package resin 1 is becoming thinner, and cracks 2 may occur as shown in FIGS. 3 and 4 due to heat at the time of mounting the substrate (mainly heat of reflow). The crack 2 is caused by a stress due to a difference in thermal expansion coefficient between the semiconductor element 4 or the die 5 and the package resin 1 and is generated along an edge portion between the semiconductor element 4 or the die 5 and the package resin 1.

The impact at this time covers the upper surface of the chip.
In some cases, the passivation film 19 may be destroyed.
l Disconnection due to corrosion of wiring. Even if the crack 2 does not occur in the package resin 1, the passivation film 19
In the case where there is a defect, if the material of the package resin 1 is a plastic package, moisture permeates, so that similar corrosion may proceed. It is considered that such corrosion has a high possibility that the outer peripheral portion of the semiconductor element 4 in which the crack 2 is likely to occur proceeds first, so that the Al wiring 9 in FIG. Therefore, the detection signal of FIG.
All you have to do is check if it has become.

In the case of FC (flip chip) mounting as shown in FIG.
7, it is easily affected by stress due to a difference in thermal expansion coefficient. The thermal expansion coefficient of the printed circuit board 17 is about four times that of the semiconductor element 4. In the case of FC mounting, the stress is directly applied to the bump 16 and the semiconductor element 4. Therefore, the stress is dispersed by the epoxy-based sealing resin 15. . However, when cracks occur in the sealing resin 15 due to repeated application of stress, deterioration of the sealing resin 15, and the like, corrosion of the aluminum wiring due to moisture occurs as described above. Further, due to repetition of stress, fatigue disconnection of the Al wiring called stress migration may occur. Also in this case, when moisture enters due to deterioration of the sealing resin 15, it is considered that the moisture enters from the outer peripheral portion of the semiconductor element 4, so that the Al wiring 9 in FIG. Further, even if stress migration occurs due to repetition of stress, it is considered that the Al wiring 9 in FIG. 1 is disconnected, so that a failure can be predicted only by checking whether the detection signal in FIG. 3 has become “L”.

In addition, as the degree of integration of semiconductor devices increases year by year, the miniaturization of the process progresses. As the Al wiring becomes thinner and the cross-sectional area decreases, the current density tends to increase. For this reason, the problem of electromigration has been highlighted. The mechanism of electromigration is well known. When a current flows through the Al wiring, Al ions move in the direction in which electrons flow, and if this state is continued for a long time, voids are generated on the cathode side. It is a disconnection. Conversely, whiskers are generated on the anode side, and when the whiskers progress, eventually, dielectric breakdown (short circuit) occurs. This phenomenon progresses as the current density of the Al wiring increases. A current is constantly flowing in the Al wiring 9 in FIG. 1 in a constant direction, and the current density is the same as the Al wiring 2 in FIG.
Since the Al density is set to a value approximated to the maximum value of the current density of 0 and the Al wirings 9 are arranged in parallel in proximity to each other, electromigration is likely to occur. From the above, the failure of electromigration can be predicted by checking whether the detection signal in FIG. 3 has become “L”.

As shown in FIG. 1, the detection signal 30 is output as an external terminal of the semiconductor device, and the failure can be predicted by monitoring the state.

(Embodiment 2) FIGS. 8 and 9 are diagrams showing a method for monitoring failure prediction data according to an embodiment of the present invention. The detection signal 30 shown in FIG. 3 described in the first embodiment is output from the signal detection creation circuit 29 in FIG. That is, "H" is output when normal and "L" is output when failure is predicted. This signal is periodically taken into the detection signal latch circuit 32 and set in the failure prediction bit 34 of the specific register 33 inside the semiconductor device. This storage is performed by the detection and reading controller 36, but may be performed by an external command or a timer inside the semiconductor device, and the storage method is not specified. The information of the failure prediction bit 34 can be output from the data BUS 38 by a normal register read operation.

The failure prediction bit is periodically monitored by the firmware of the product, and when any one of the plurality of semiconductor devices changes the failure prediction bit, an alarm is output via a monitor or the like.

(Embodiment 3) FIG. 10 is a view showing a wiring shape of an Al wiring based on one embodiment of the present invention. FIG. 10 is a top view showing the wiring shape of the aluminum wiring 9 of FIG. (A) shows two Al wirings 9 in parallel in a straight line,
(B) is one in which wiring is performed on unevenness, and (b) has a longer total distance of the aluminum wiring than (a), so that corrosion due to moisture is likely to occur and the detection rate can be increased.

[0035]

As described above, according to the present invention, it is possible to predict and avoid defects such as poor moisture resistance and electromigration of semiconductor devices, and stress migration caused by repeated stress. .
This is particularly effective for a semiconductor device such as a BGA package which is weak to heat at the time of mounting and an FC mounting in which a stress is directly applied to a semiconductor element. Since the present invention does not require a special inspection environment, it is useful in terms of time and cost, and it can be said that the present invention is particularly useful in computer products in which system down is not allowed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a diagram illustrating a configuration of a detection circuit portion according to an embodiment of the present invention.

FIG. 3 is a diagram showing a structure of a semiconductor device having a general SOP / QFP package.

FIG. 4 is a diagram illustrating a structure of a semiconductor device having a general BGA package.

FIG. 5 is a diagram showing a mounting structure of a general FC-mounted semiconductor device.

FIG. 6 is a diagram showing a structure of a general CMOS semiconductor.

FIG. 7 is a diagram showing a structure of a general CMOS semiconductor.

FIG. 8 is a diagram illustrating a configuration of a semiconductor device according to an embodiment of the present invention;

FIG. 9 is a diagram showing a configuration of a system according to an embodiment of the present invention.

FIG. 10 is a diagram showing a shape of an Al wiring according to an embodiment of the present invention.

[Explanation of symbols]

1 ... package resin, 2 ... crack,
3 Lead, 4 Semiconductor element, 5 Die, 6 Wire, 7 Carrier, 8 Solder ball, 9 Aluminum wiring, 10 Bonding pad, 11 Detection signal generation circuit,
14a-d: resistance element, 15: sealing resin,
16: bump, 17: printed circuit board,
18: detection signal wire, 19: passivation film, 20: aluminum wiring, 21: gate oxide film, 22: interlayer insulating film, 23 ...
n-type silicon, 24 ... p well, 25
... G (gate), 26 ... S (source), 27 ... D (drain), 28 ... infiltration of water, 29 ... detection signal generation circuit, 30
... Detection signal, 31 ... Semiconductor device, 3
2 ... detection signal latch circuit, 33 ... register,
34: failure prediction bit, 35: I / O controller, 36: detection signal reading controller, 37: failure prediction information, 38: data BUS, 39: address BUS, 40
... Command signal, 41 ... System firmware, 4
2: Latch signal.

Claims (9)

[Claims] An aluminum wiring having a resistance element connected to one end thereof,
A resistance element is also connected to the other end, and both resistance elements are connected so as to generate a potential difference. A constant current flows through the aluminum wiring, and a failure to predict the occurrence of a failure by monitoring the voltage of the aluminum wiring. A semiconductor device comprising a prediction mechanism. 2. The semiconductor device according to claim 1, wherein said plurality of aluminum wirings and resistance elements are provided.
A semiconductor device characterized by having a failure prediction mechanism for predicting the occurrence of a failure by monitoring the aforementioned voltage in parallel so that the aluminum wirings do not come into contact with each other. 3. The aluminum wiring is routed so as to pass through a portion as close as possible to the outermost periphery of the semiconductor element and so as to substantially surround the semiconductor element, and the above-described voltage monitoring is performed to predict occurrence of a defect. A semiconductor device provided with a failure prediction mechanism. 4. A semiconductor device characterized in that an aluminum wiring wired so as to surround said semiconductor element has the same width as an aluminum wiring in a semiconductor circuit portion, and a failure prediction mechanism for increasing a failure prediction rate is provided. 5. A failure prediction mechanism wherein a current flowing through an aluminum wiring wired so as to surround said semiconductor element is substantially equal to a current density of aluminum wiring in a semiconductor circuit portion, and a failure prediction mechanism for increasing a failure prediction rate is provided. Semiconductor device. 6. The total wiring distance is lengthened by forming an aluminum wiring which is wired so as to surround said semiconductor element to have an uneven shape.
A semiconductor device, comprising: a failure prediction mechanism for increasing a failure prediction rate. 7. The method according to claim 7, wherein said voltage monitoring is performed by using a logic circuit.
1. A semiconductor device, comprising: a failure prediction mechanism that makes a determination and outputs the result to an external terminal of the semiconductor device as a detection signal. 8. A failure prediction mechanism which periodically stores the failure prediction signal in a specific bit of an internal specification register of the semiconductor device and externally reads defect prediction information using a general-purpose interface. Semiconductor device. 9. An electronic apparatus, comprising: a failure prediction system that monitors the failure prediction information of a plurality of semiconductor devices by system firmware and performs a failure prediction as a product system.