JPH1125699A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can monitor internal signals in the mold state. SOLUTION: A test signal generator circuit 40 generates test signals. In response to a test signal, a monitor circuit 20 realizes a condition in which a node N1 through which a sense amplifier activating signal So passes, a node N2 through which a column decoder activating signal CDE passes, or a node N3 through which the output control signal OEM passes is connected with the /WE pin. On the other hand, an output control circuit 55 receives the write enable signal /WE at the H level from a control circuit 30 at the time of the test mode of an internal signal monitor. By this, it is possible to monitor internal signals about the access path from the /WE pin.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of monitoring internal signals in a molded state.

[0002]

2. Description of the Related Art As a test method for evaluating electric characteristics of a semiconductor memory device in a molded state, there is a method of measuring a timing of a potential change at an external connection terminal.

[0003]

However, the above-described test method has a problem that the timing of measurement is limited.

Therefore, when it is necessary to perform a more detailed evaluation, a method of opening the mold resin to expose the chip, and monitoring the internal signal inside the chip by probing is adopted.

However, the test method in which the mold resin is unsealed takes a long time to evaluate the electrical characteristics, and the unsealing of the mold resin causes damage to the chip. In addition, during the mass production test after the assembly, the internal signal of the chip cannot be monitored.

Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor memory device capable of monitoring an internal signal inside a chip in a molded state. .

[0007]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: an external connection terminal; a memory array including a plurality of memory cells arranged in a matrix in a plurality of rows and a plurality of columns; An internal circuit for reading data from a cell or writing data to a memory cell, and activation signal generating means for outputting an activation signal for activating the internal circuit according to a plurality of control signals received from outside;
In the test mode, there are provided test signal generating means for generating a test signal, and monitor means for monitoring an activation signal from an external connection terminal in response to the test signal output from the test signal generating means.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the internal circuit receives the activation signal from the activation signal generating means via the first signal line, and The means includes switch means, a second signal line connecting the switch means to the external connection terminal, and a third signal line connecting the first signal line and the switch means. In response to the signal, the second signal line and the third signal line are connected.

A semiconductor memory device according to a third aspect is the semiconductor memory device according to the second aspect, wherein the internal circuit is a sense amplifier, and the activation signal is a sense amplifier activation signal for activating the sense amplifier. It is.

A semiconductor memory device according to a fourth aspect is the semiconductor memory device according to the second aspect, wherein the internal circuit is a decoder for selecting a column of the memory array, and the activation signal is
A decoder activation signal for activating the decoder.

A semiconductor memory device according to a fifth aspect is the semiconductor memory device according to the second aspect, wherein the internal circuit is an output buffer, and the activation signal is an output control signal for activating the output buffer. .

A semiconductor memory device according to a sixth aspect is the semiconductor memory device according to the second aspect, wherein the internal circuit includes a sense amplifier, a decoder, and an output buffer, and the activation signal includes a sense amplifier. A sense amplifier activation signal for activating, a decoder activation signal for activating the decoder,
And an output control signal for activating the output buffer.

A semiconductor memory device according to a seventh aspect is the semiconductor memory device according to the second aspect, wherein the internal circuit is an internal circuit for reading data from a memory cell, and the external connection terminal is / WE. The monitor means further includes control means for supplying an H level write enable signal / WE to the activation signal generating means.

According to an eighth aspect of the present invention, in the semiconductor memory device of the first aspect, the test signal generating means generates a test signal in response to an input of an address pin in the WCBR mode.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION

[Embodiment 1] Embodiment 1 of the present invention makes it possible to monitor internal signals of a chip in a molded state in a semiconductor memory device.

For reference, a conventional semiconductor memory device 200
Will be described briefly. FIG. 1 is a block diagram showing a basic configuration of a conventional semiconductor memory device 200. Referring to FIG. 1, a conventional semiconductor memory device 200 includes a memory array 50, a row decoder 51, an address buffer 52, a column decoder 54, and a sense amplifier 53.

The memory array 50 includes a plurality of memory cells (not shown) arranged in a matrix in a plurality of rows and a plurality of columns. The plurality of memory cells arranged in the row direction are connected to corresponding word lines, respectively.
Further, the plurality of memory cells arranged in the column direction are connected to corresponding bit lines, respectively.

The address buffer 52 includes an address pin A
In accordance with an external address signal ADD input from 0 to A7, an internal address signal (more specifically, an internal row address signal RAi and an internal column address signal CAi) is output.

The row decoder 51 includes an address buffer 5
Receiving the internal row address signal RAi output from No. 2, one word line is selected.

Column decoder 54 sets one bit line to a selected state based on an internal column address signal CAi output from address buffer 52 in accordance with a column decoder activation signal CDE output from clock generator 56 described later.

The sense amplifier 53 has a sense amplifier activating signal S also output from the clock generator 56.
o, amplify the data of the selected memory cell,
Output to data line DLINE.

The conventional semiconductor memory device 200 further includes an output control circuit 55, an output buffer 57, and a clock generator 56.

The output control circuit 55 is connected to the / WE pin via a signal line LINE4. The output control circuit 55
H level write enable signal / WE from / WE pin
In response, an output control signal OEM is generated. The output control signal OEM is transmitted to the output buffer 57 via the signal line LINE3.

Output buffer 57 receives a data line DLIN in accordance with an output control signal OEM received from output control circuit 55.
The data obtained via E is transmitted to the data input / output pin DQ. Data read from the memory array 50 is
The data is output to the outside of the chip via the data input / output pin DQ.

Clock generator 56 receives a row address strobe signal / RAS from a / RAS pin, and further receives a column address strobe signal / RAS from a / CAS pin.
In response to CAS, various activation signals including a sense amplifier activation signal So and a column decoder activation signal CDE are generated. The sense amplifier activation signal So is connected to the signal line LINE.
1 is transmitted to the sense amplifier 53. Column decoder activation signal CDE is transmitted to column decoder 54 via signal line LINE2.

Next, the semiconductor memory device 100 according to the first embodiment of the present invention will be described. FIG. 2 is a block diagram showing a basic configuration of the semiconductor memory device 100 according to the first embodiment of the present invention. The same components as those of the conventional semiconductor memory device 200 shown in FIG. ,
The description is omitted.

Referring to FIG. 2, semiconductor memory device 100 according to the first embodiment of the present invention is different from conventional semiconductor memory device 200 shown in FIG. 1 in that monitor circuit 20 for monitoring internal signals is provided. , A test signal generation circuit 40 for controlling the monitor circuit 20, and a control circuit 30 for controlling the output control circuit 55.

The configuration and operation of test signal generation circuit 40 will be described. The test signal generation circuit 40
Test signals φ1, φ2, and φ3 are generated based on inputs from address pins A0 to A7 in the R mode. When any one of the test signals φ1, φ2, φ3 goes to the H level, an internal signal can be monitored by the monitor circuit 20 described later (this state is hereinafter referred to as an internal signal monitor test mode).

FIG. 3 is a block diagram showing a basic configuration of test signal generation circuit 40 according to the first embodiment of the present invention. Referring to FIG. 3, test signal generation circuit 40
It includes a BR detector 41, a row address buffer 42, an overvoltage detector 43, a test address latch 44, a generator 45, and an inverter circuit 46.

WCBR detector 41 outputs a row address strobe signal / RAS from a / RAS pin to a / CAS signal.
A WCBR mode is detected by receiving a column address strobe signal / CAS from a pin and a write enable signal / WE from a / WE pin. WCBR detector 4
1 generates and outputs a WCBR signal and a TE signal as detection results.

Here, the WCBR mode means that the column address signal / CAS and the write enable signal / RAS are output before the row address strobe signal / RAS goes low.
This refers to the state where WE is at the L level.

Row address buffer 42 outputs an internal row address signal RAi according to an external address signal ADD received from address pins A0-A7.

The over-voltage detector 43 receives an input of a high voltage level (a level higher than a normal operating voltage) outside the specification (where Aj is one of the address pins A0 to A7). Corresponding). When the input to the address pin Aj is at a high voltage, an OVAj signal indicating the address pin Aj is generated.

The test address latch 44 receives the internal row address signal R output from the row address buffer 42.
Ai and the OVAj signal output from the overvoltage detector 43 are latched. The latched internal row address signal RAi is transferred to a generator 45 described later as an XAi signal. Also, the latched OV
The Aj signal is transferred to the generator 45 as an XOVAj signal. The transfer timing of the XAi signal and the XOVAj signal follows the WCBR signal output from the WCBR detector 41.

Generator 45 generates test signals φ1, φ2, φ3 based on the XAi signal and XOVAj signal output from test address latch 44. The timing of starting generation of the test signals φ1, φ2, φ3 is
According to the TE signal output from the WCBR detector 41.

Any of test signals φ1, φ2, φ3 is H
The level is determined by the relationship between the internal row address signal RAi and the address pin Aj to which the high voltage level has been input. Note that if any one of the test signals φ1, φ2, and φ3 is at the H level, the others are at the L level.

The inverter circuit 46 generates test signals φ1,
receives φ2 and φ3 and inverts them to generate an inverted test signal / φ
1, / φ2 and / φ3 are generated.

Next, the operation of test signal generation circuit 40 will be described. FIG. 4 is a timing chart of various signals for explaining the operation of test signal generation circuit 40 according to the first embodiment of the present invention. Referring to FIGS. 3 and 4, at time t1, row address buffer 42
Output the internal row address signal RAi. On the other hand, the overvoltage detector 43 is connected to the address pin Aj.
Is detected as a high voltage level out of the specification, and outputs an OVAj signal.

At time t2, column address strobe signal / CAS and write enable signal / WE
Falls to the L level. Row address strobe signal / RAS is at H level.

At time t3, the WCBR detector 4
1 indicates the start timing of the WCBR mode (before the row address strobe signal / RAS goes low, the column address signal / CAS and the write enable signal / W
E becomes L level), and WCBR of H level is detected.
Generate a signal.

At time t4, test address latch 44 receiving the WCBR signal at the H level outputs XAi signal and XOVAj signal.

At time t5, row address strobe signal / RAS falls to L level, and at time t6, column address strobe signal / CAS and write enable signal / WE rise to H level.

At time t7, when row address strobe signal / RAS rises to H level, WCBR signal falls to L level. Based on this, the TE signal rises to the H level.

At time t8, generator 45 receiving the H-level TE signal outputs XAi signal and OVAj.
Based on the signals, test signals φ1, φ2, and φ3 are generated and output. In this case, for example, as shown in FIG. 4, the test signal φ1 goes high and the test signals φ2 and φ3 go low.

Further, at time t9, the inverter circuit 4
6, the inverted test signals / φ1, / φ2, / φ3 are output. In this case, the inverted test signal / φ1 goes low, and the inverted test signals / φ2 and / φ3 go high.

Subsequently, the first embodiment of the present invention shown in FIG.
Will be described. In accordance with test signals φ1, φ2, φ3 and inverted test signals / φ1, / φ2, / φ3, monitor circuit 20 sense amplifier activation signal So related to the access path, column decoder activation signal CDE, and output control signal OEM. Can be monitored from the / WE pin.

FIG. 5 is a circuit diagram showing an example of a basic configuration of monitor circuit 20 according to the first embodiment of the present invention. Referring to FIG. 5, monitor circuit 20 includes switch 1, switch 2, and switch 3. The switch 1 is a circuit for monitoring the sense amplifier activation signal So.
Switch 2 is a circuit for monitoring column decoder activation signal CDE. The switch 3 is a circuit for monitoring the output control signal OEM.

The switch 1 will be described. Switch 1
Includes a PMOS transistor PT1 and an NMOS transistor NT1. One of the conductive terminals is connected to the signal line LINE11, and the other conductive terminal is connected to the signal line LINE12. PMOS transistor P
The gate electrode of T1 receives the inverted test signal / φ1,
The gate electrode of MOS transistor NT1 receives test signal φ1.

Signal line LINE11 is connected to node N1, and signal line LINE12 is connected to the / WE pin. Note that, as shown in FIG. 2, the signal line LINE11 is connected to the signal line LINE1 at the node N1.

The switch 2 will be described with reference to FIG. Switch 2 includes a PMOS transistor PT2 and an NMOS transistor NT2. One conduction terminal of each of the PMOS transistor PT2 and the NMOS transistor NT2 is connected to the signal line LINE21, and the other conduction terminal of each of the PMOS transistor PT2 and the NMOS transistor NT2 is connected to the signal line LINE22.
Connected to The gate electrode of PMOS transistor PT2 receives inverted test signal / φ2, and the gate electrode of NMOS transistor NT2 receives test signal φ2.

Signal line LINE21 is connected to node N2, and signal line LINE22 is connected to the / WE pin. Note that, as shown in FIG. 2, the signal line LINE21 is connected to the signal line LINE2 at the node N2.

The switch 3 will be described with reference to FIG. The switch 3 includes a PMOS transistor PT3,
Includes NMOS transistor NT3. One conductive terminal of each of the PMOS transistor PT3 and the NMOS transistor NT3 is connected to the signal line LINE31, and the other conductive terminal is connected to the signal line LINE32.
Connected to The gate electrode of PMOS transistor PT3 receives inverted test signal / φ3, and the gate electrode of NMOS transistor NT3 receives test signal φ3.

Signal line LINE31 is connected to node N3, and signal line LINE32 is connected to the / WE pin. Note that, as shown in FIG. 2, the signal line LINE31 is connected to the signal line LINE3 at the node N3.

Next, the operation of the switches 1, 2, and 3 will be described. As described above, in the internal signal monitor test mode, any one of the test signals φ1, φ2, φ3
One rises to the H level. Thereby, the switch 1,
One of 2 and 3 is turned on (conductive state). For example, when the switch 1 is turned on, the / WE pin and the node N1 are electrically connected. As a result, / WE
The signal on the node N1 can be monitored from the pin.

Thus, when test signal φ1 is set to the H level and set to the read operation mode, the transition of sense amplifier activation signal So appearing on node N1 (ie, LINE1) can be monitored from / WE pin. It becomes possible.

Similarly, the test signal φ2 is set to the H level,
In addition, when the read operation mode is set, the transition of the column decoder activation signal CDE appearing on the node N2 (that is, LINE2) can be monitored from the / WE pin. Further, when the test signal φ3 is set to the H level and the read operation mode is set, the transition of the output control signal OEM appearing on the node N3 (that is, LINE3) can be monitored from the / WE pin.

Next, the control circuit 30 according to the first embodiment of the present invention shown in FIG. 2 will be described. Control circuit 30
Is a high level write enable signal / WE to the output control circuit 55 in the internal signal monitor test mode.
Is transmitted.

FIG. 6 is a circuit diagram showing an example of the basic configuration of control circuit 30 according to the first embodiment of the present invention, and also shows the connection relationship with output control circuit 55. FIG.
Referring to, control circuit 30 includes an AND circuit 5, an inverter circuit 6, PMOS transistors PT4 and PT5, and an NMOS transistor NT4.

The AND circuit 5 has an inversion test signal /
Receive φ1, / φ2, / φ3. The inverter circuit 6
The output of the AND circuit 5 is received at the input. One conduction terminal of each of the PMOS transistor PT4 and the NMOS transistor NT4 is connected to the signal line LINE41. Further, each other conductive terminal is connected to a signal line LI.
Connected to NE42. The gate electrode of PMOS transistor PT4 receives the output of AND circuit 5. NMOS
The gate electrode of the transistor NT4 is connected to the inverter circuit 6
Receive the output of PMOS transistor PT5 is connected between internal power supply voltage VCC and signal line LINE41, and has a gate electrode receiving the output of inverter circuit 6.

Signal line LINE41 is connected to node N4, and signal line LINE42 is connected to the / WE pin. Here, the node N4 corresponds to an input node of the output control circuit 55, and the output control circuit 55 receives the write enable signal / WE from the node N4.

Next, the operation of the control circuit 30 will be briefly described. FIG. 7 is a timing chart of various signals for describing the operation of control circuit 30 in the first embodiment of the present invention.

First, the operation of the control circuit 30 in the internal signal monitor test mode will be described. For simplicity, test signal φ1 is set at H level.

Referring to FIGS. 6 and 7, at time t1, inverted test signal / φ1 attains L level (inverted test signals / φ2 and / φ3 are at H level). In this case, as described above, the / WE pin is connected to node N1.

At time t2, AND circuit 5 receives L-level inverted test signal / φ1 and outputs an H-level signal. Further, at time t3, inverter circuit 6 receives an H level signal from AND circuit 5,
An L level signal is output.

As a result, the PMOS transistor PT4
And the NMOS transistor NT4 is turned off. As a result, the signal lines LINE41 and LINE4
2 is disconnected.

At time t4, PMOS transistor PT5 is turned on upon receiving the L-level signal from inverter circuit 6. As a result, the node N4 is charged to the H level based on the internal power supply voltage VCC.

That is, in the internal signal monitor test mode, output control circuit 55 of semiconductor memory device 100 receives H level write enable signal / WE regardless of the potential of / WE pin. As a result, the output control circuit 55 can generate and output the output control signal OEM.

On the other hand, in modes other than the internal signal monitor test mode, the inverted test signals / φ1, / φ2, / φ3 are all at H level, the output of the AND circuit 5 is at L level, and the output of the inverter circuit 6 is at H level. Becomes This allows P
MOS transistor PT4 and NMOS transistor NT4 are turned on. Further, the PMOS transistor PT5 is turned off. As a result, the output control circuit 55 of the semiconductor memory device 100 receives a signal from the / WE pin as in the case of the conventional semiconductor memory device 200 shown in FIG.

As described above, the semiconductor memory device 100
In the molded state, it becomes possible to monitor the activation signal related to the access path from the / WE pin.

Next, an electric characteristic evaluation test in semiconductor memory device 100 according to the first embodiment of the present invention will be described.

For reference, an electrical characteristic evaluation test on a conventional semiconductor memory device 200 in a molded state will be described.

As described above, the electrical characteristics of the conventional semiconductor memory device 200 without the monitor circuit 20 are evaluated by measuring the potential change of the external connection terminal. More specifically, based on the data output timing from the data input / output pin DQ, the t _RAC period, t
_{The CAA} period and the t _CAC period are measured.

[0073] easy, t _RAC period, which is part of the measurement object, t _CAA period, and for t _CAC period is described.

FIG. 8 shows transitions of various signals in the read operation mode, and t _RAC period, t _CAA period,
6 is a timing chart showing a t _CAC period.

Referring to FIG. 8, at time t1, an external address signal ADD received from address pins A0 to A7 is provided.
, An internal row address signal RAi is output.

At time t2, row address strobe signal / RAS received from / RAS pin falls to L level.

At time t3, address pins A0-A
7, an internal column address signal CAi is generated based on the external address signal ADD.

At time t4, column address strobe signal / CAS received from / CAS pin falls to L level, and write enable signal / WE received from / WE pin is at the H level.

In response, at time t5, data DOUT is output from data input / output pin DQ.

Here, the period from time t2 to time t5 is defined as t
_The period from time t3 to time t5 is referred to as _RAC period, and t _CAA
A period from time t4 to time t5 is referred to as a period.
_{Called CAC} .

Next, the conventional semiconductor memory device 20 will be described for reference.
The procedure of the electrical characteristic evaluation test for 0 will be described.

FIG. 9 is a flowchart showing a procedure of an electrical characteristic evaluation test on a conventional semiconductor memory device 200. Referring to FIG. 9, in step s1, implementing t _RAC test to measure the t _RAC period. In step s2, the measurement result of step s1 is compared with the specified time, and chips that do not satisfy the measurement result are selected.

[0083] In step s3, met the standard in step s2 relative (PASS) chip, to implement t _CAC test to measure the t _CAC period. In step s4, the measurement result in step s3 is compared with the standard time, and chips that do not satisfy the standard are selected.

In step s5, t _CAA for measuring the t _CAA period for the chip satisfying the standard in step s4
Conduct a test. In step s6, the measurement result of step s5 is compared with the standard time, and chips that do not satisfy the standard are selected.

Hereinafter, tests at various timings (for example, a t _CEA test, etc.) are performed in the same procedure.

As described above, the conventional semiconductor memory device 20
For 0, pins (/ RAS pin, / CAS pin, address pins A0 to A0) that control the operation of the chip with reference to the data output timing at the data input / output pin DQ.
The electrical characteristics are evaluated by measuring the timing of the potential change in A7).

Next, the procedure of an electrical characteristic evaluation test on semiconductor memory device 100 according to the first embodiment of the present invention will be described.

FIGS. 10 to 11 show Embodiment 1 of the present invention.
5 is a flowchart showing a procedure of an electrical evaluation test for the semiconductor memory device 100 in FIG. 10 to 11
In step s10, the test signal φ1 is set to H level.
Get up to level.

In step s11, the activation start time of the sense amplifier activation signal So at the time of t _RAC is measured. In step s12, the measurement result of step s11 is compared with the standard time, and chips that do not satisfy the standard are selected.

At step s13, the test signal φ2 is set to H level.
Get up to level. In step s14, step s1
For a chip that satisfies the standard at 2 (PASS), t
The activation start time of the column decoder activation signal CDE at the _RAC timing is measured. In step S15, the measurement result of step s14 is compared with the standard time, and chips that do not satisfy the standard are selected.

At step s16, test signal φ3
To the H level. In step s17, the chip satisfying the standards in step s15, measuring the output control signal OEM activity start time of the time t _{RA C} timing. In step s18, the measurement result of step s17 is compared with the standard time, and chips that do not satisfy the standard are selected.

Subsequently, in step s19, step s
The chip that meet standards 18, to implement the t _RAC test to measure the t _RAC period. In step s20,
The measurement result of step s19 is compared with the standard time, and chips that do not satisfy the standard are selected.

Others, t _CAA test, t _CAC test, t _CAA test
_{The CEA} test and the like are performed in the same procedure.

As described above, the semiconductor memory device 100 according to the first embodiment of the present invention can monitor internal signals in a molded state, so that it is possible to evaluate electrical characteristics in more detail.

The output pin to be monitored is not limited to the / WE pin, but may be a no connection pin or a data input / output pin. The internal signals are not limited to the sense amplifier activating signal So, the column decoder activating signal CDE, and the output control signal OEM.

[0096]

As described above, according to the semiconductor memory device according to the first and second aspects, the activation signal can be monitored from the external connection terminal in response to the test signal. Monitoring can be performed from the outside, and more detailed evaluation of electrical characteristics can be performed.

Further, according to the semiconductor memory device of the third aspect, it is possible to externally monitor the sense amplifier activating signal So, which is a main signal related to the access path, from the outside.

Further, according to the semiconductor memory device of the fourth aspect, the column decoder activation signal CDE, which is a particularly main signal on the access path, can be monitored from the outside.

Further, according to the semiconductor memory device of the fifth aspect, it is possible to externally monitor the output control signal OEM which is a particularly main signal concerning the access path.

Further, according to the semiconductor memory device of the sixth aspect, the sense amplifier activating signal So, the column decoder activating signal CDE, and the output control signal, which are the main signals related to the access path, are provided in response to the test signal. The OEM can be monitored externally.

Further, according to the semiconductor memory device of the seventh aspect, it is possible to monitor main internal signals from the / WE pin in the read operation.

Further, according to the semiconductor memory device of the eighth aspect, the test mode for monitoring the internal signal can be set using the WCBR mode.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a conventional semiconductor memory device 200.

FIG. 2 is a block diagram showing a basic configuration of the semiconductor memory device 100 according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a basic configuration of a test signal generation circuit 40 according to the first embodiment of the present invention.

FIG. 4 is a timing chart of various signals for describing an operation of the test signal generation circuit 40 according to the first embodiment of the present invention.

FIG. 5 is a monitor circuit 2 according to the first embodiment of the present invention.
FIG. 2 is a circuit diagram illustrating an example of a basic configuration of a zero.

FIG. 6 shows a control circuit 30 according to the first embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of the basic configuration of FIG.

FIG. 7 is a control circuit 30 according to the first embodiment of the present invention.
3 is a timing chart of various signals for explaining the operation of FIG.

FIG. 8 shows transition of various signals in a read operation mode;
T to be measured _RACPeriod, t_CAAPeriod, t_CACperiod
FIG.

FIG. 9 is a flowchart showing a procedure of an electrical characteristic evaluation test for a conventional semiconductor memory device 200.

FIG. 10 is a flowchart showing a procedure of an electrical characteristic evaluation test of the semiconductor memory device 100 according to the first embodiment of the present invention.

FIG. 11 is a flowchart showing a procedure of an electrical characteristic evaluation test of the semiconductor memory device 100 according to the first embodiment of the present invention.

[Description of Signs] 1, 2, 3 switch, 30 control circuit, 5 AND circuit, 6, 46 inverter circuit, 20 monitor circuit, 4
0 test signal generation circuit, 41 WCBR detector,
42 row address buffer, 43 over voltage detector, 44 test address latch, 45 generator, 50 memory array, 51 row decoder,
52 address buffer, 53 sense amplifier, 54
Column decoder, 55 output control circuit, 56 clock generator, 57 output buffer, PT1 to PT5
PMOS transistor, NT1 to NT4 NMOS transistor, LINE1 to 3, LINE11, LINE
12, LINE21, LINE22, LINE31, L
INE32, LINE41, LINE42 signal line, 1
00 Semiconductor storage device.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI G11C 11/34 371K

Claims (8)

[Claims] An external connection terminal; a memory array including a plurality of memory cells arranged in a matrix in a plurality of rows and a plurality of columns; reading data from the memory cells, or storing data in the memory cells; An internal circuit for writing, activation signal generating means for outputting an activation signal for activating the internal circuit in accordance with a plurality of control signals received from outside, and a test signal for generating a test signal in a test mode A semiconductor memory device comprising: a generation unit; and a monitoring unit that monitors the activation signal from the external connection terminal in response to the test signal output from the test signal generation unit. 2. The internal circuit receives the activating signal from the activating signal generating means via a first signal line, and the monitoring means comprises: a switching means; a switching means; and the external connection terminal. Connect the second
A third signal line connecting the first signal line and the switch means.
Wherein the switch means connects the second signal line and the third signal line in response to the test signal,
The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 2, wherein said internal circuit is a sense amplifier, and said activation signal is a sense amplifier activation signal for activating said sense amplifier. 4. The semiconductor memory device according to claim 2, wherein said internal circuit is a decoder for selecting a column of said memory array, and said activation signal is a decoder activation signal for activating said decoder. 5. The semiconductor memory device according to claim 2, wherein said internal circuit is an output buffer, and said activation signal is an output control signal for activating said output buffer. 6. The internal circuit includes a sense amplifier, a decoder, and an output buffer, wherein the activating signal is: a sense amplifier activating signal for activating the sense amplifier; and a decoder for activating the decoder. An activation signal; and an output control signal for activating the output buffer.
The semiconductor memory device according to claim 2. 7. The internal circuit is an internal circuit for reading data from the memory cell, the external connection terminal is a / WE pin, and the monitor means further includes an activation signal generation means. 3. The semiconductor memory device according to claim 2, further comprising control means for applying an H level write enable signal / WE. 8. The semiconductor memory device according to claim 1, wherein said test signal generation means generates said test signal in response to an input of an address pin in a WCBR mode.