JPH1125687A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a defect relieving circuit in which high integration and high speed operation are realized by providing a decoder for redundancy forming a selecting signal of a redundant word line or a redundant bit line at the position adjacent to a decoding circuit forming a selecting signal of a word line or a bit line. SOLUTION: One redundant main work line RMRLB is provided for one memory mat MARY. Redundant circuits XR0-XR31 are provided corresponding to the main word lines MWLB0-MWLB31. In the redundant circuits XR0-XR31, selecting signals of the redundant main word lines RMRLB are formed by utilizing selecting signals MSB0-MSB31 formed in a X decoder XD as they are. Thereby, since the redundant circuits XR0-XR31 and the X decoder circuit XD are arranged adjacently and switching between a defective main word line of the normal circuit and the redundant main word line RMRLB by the shortest path can be performed, high speed operation can be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technology effective when used as a defect relief technology in a dynamic RAM (random access memory).

[0002]

2. Description of the Related Art A dynamic RAM having a large storage capacity such as 64 Mbits or 256 Mbits is disclosed in "Nikkei Electronics" No. 641, pp. 99-214, published on July 31, 1995 by Nikkei McGraw-Hill. is there.

[0003]

When a laser cutter is used for cutting a fuse as in the prior art, the size of the fuse cannot be reduced because the laser spot size is large. Also, it takes time to cut it,
When a large number of fuses are mounted, a correspondingly long time is required for cutting (programming). In addition, after cutting, the cut surface of the fuse is not covered with the insulating film, so a guard ring is required, which also contributes to the inability to reduce the size of the fuse and to the part below the lead frame. Cannot be placed.

[0004] As described above, in an open fuse such as a case using a laser cutter, in order to prevent the fuse portion from being corroded by water entering through a gap between the lead frame and the resin, the fuse is not overlapped with the lead frame. It is arranged near the non-wrapped bonding pad area. For this reason, the signal path detours through an address decoding unit disposed adjacent to the memory array unit and a redundant circuit including a fuse disposed at a position distant from the address decoding unit, which is a factor hindering high-speed operation. Has become. In addition, a comparison circuit for comparing with a defective address is required, and the integration degree is reduced due to the large occupation area of the fuse.

An object of the present invention is to provide a semiconductor memory device provided with a defect relieving circuit that achieves high integration and high-speed operation. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a non-opening fuse which is provided adjacent to a decode circuit for forming a word line or bit line selection signal and is provided in one-to-one correspondence with the word line or bit line and is selectively cut off, A fuse circuit comprising a switch circuit that is controlled in accordance with the presence or absence of disconnection of the redundant word line or redundant bit by taking a logical sum signal of a selection signal of a normal word line or a bit line passed through the switch circuit; A redundant decoder for forming a line selection signal is provided.

[0007]

FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor memory device according to the present invention.
Although not particularly limited, the semiconductor memory device of this embodiment is
It is directed to an SDRAM (synchronous DRAM), and is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The SDRAM of this embodiment has four sets (× 4) of memory cell arrays MARY constituting memory banks (Bank) 0 to memory bank 3. The memory cell array MARY includes dynamic memory cells arranged in a matrix. According to the drawing, the selection terminals of the memory cells arranged in the vertical direction are connected to word lines (not shown) for each column. The data input / output terminals of the memory cells arranged in the same row in the horizontal direction are coupled to complementary bit lines for each row.

A word line (not shown) of the memory cell array MARY is substantially driven to a selected level by a word driver WD in accordance with a row timing signal (not shown) as a result of decoding of an X address signal by an X decoder XD. A complementary bit line (not shown) of the memory cell array MARY is coupled to the sense amplifier SA. The sense amplifier SA is provided with a column selection circuit as described later. The sense amplifier detects and amplifies a minute potential difference appearing on each complementary bit line by reading data from a memory cell by selecting a word line. The column switch circuit in (1) selects complementary bit lines individually and conducts them to complementary common input / output lines. Column switch circuit is Y
The selection operation is performed according to the result of decoding the column address signal by the decoder YDEC. The X decoder XD, the word driver WD, and the Y decoder YDEC as described above are provided for each of the four sets of memory cell arrays MARY.

In FIG. 1, Y as a defect relief circuit
A system redundant bit line RBL is provided. The redundant bit line RBL is connected to the Y decoder YDEC included in the Y decoder YDEC.
When there is a memory access to the defective bit line by the redundant circuit YR, the redundant bit line RBL is selected by the redundant decoder YRS instead of the defective bit line. Although not shown in the figure, a redundant word line is also provided in the memory cell array MARY, and an X redundant circuit XR is provided in the X decoder CD corresponding to the redundant word line.
The defective word line is switched to the redundant word line. The redundant circuits YR and XR are provided with non-opening fuses as described later.

The complementary common input / output line is connected to the input of the data output control circuit DOC and the output terminal of the write control circuit WCC. The output signal of the data output control circuit DOC is output to an external terminal (not shown) through the data output buffer DOB. A write signal input from an external terminal (not shown) is supplied to an input terminal of a data input buffer DIB, and an output signal of the data input buffer DIB is supplied to an input terminal of the write control circuit WCC. Although not particularly limited, an external terminal for transmitting the read signal and an external terminal for inputting the write signal are shared, and input / output is performed in units of a plurality of bits, for example, 16 bits.

An address signal supplied from an address input terminal (not shown) is supplied to a row address buffer circuit RADB
And are taken into the column address buffer CADB in the address multiplex format. The supplied address signals are held in respective address buffers RADB and CADB. For example, the row address buffer RADB and the column address buffer CADB respectively hold the fetched address signals over one memory cycle period.

In the refresh operation mode, the row address buffer RADB serves as a refresh control circuit R.
The refresh address signal output from the FC is taken in as a row address signal. In this embodiment, although not particularly limited, the refresh address signal is taken in as a row address signal via a clock generation circuit CKG. Column address buffer CADB
Is supplied as preset data to a column address counter included in the control circuit CONT. The column address counter outputs a column address signal as the preset data or a value obtained by sequentially incrementing the column address signal to the Y decoder YDEC in accordance with an operation mode specified by a command or the like described later.

Although the control circuit CONT is not particularly limited,
A clock signal CLK, a clock enable signal CKE,
A chip select signal / CS, a column address strobe signal / CAS (symbol / means that a signal added thereto is a row enable signal), a row address strobe signal / RAS, a write enable signal / WE,
An external control signal such as a data input / output mask control signal DQM and an address signal corresponding to a memory bank are supplied, and various control signals such as an operation mode of the SDRAM are provided based on a change or timing of the level of the signal. Various timing signals corresponding to the timing signals are formed, and a control logic and a mode register for that are provided. When the chip select signal / CS is at a high level (a chip is not selected) and other inputs have no meaning. However, internal operations such as a memory bank selection state and a burst operation, which will be described later, are not affected by the change to the chip non-selection state. Each of the signals / RAS, / CAS, and / WE has a different function from the corresponding signal in a normal DRAM, and is a significant signal when defining a command cycle described later.

The clock signal CLK is a master clock of the SDRAM, and other external input signals are made significant in synchronization with the rising edge of the internal clock signal. The chip select signal / CS instructs the start of a command input cycle by its low level. The clock generation circuit CKG generates an internal clock signal synchronized with a clock signal supplied from an external terminal.
It is composed of a PLL circuit, a DLL circuit, or a synchronization circuit that synchronizes a clock signal supplied from an external terminal with a delay of two cycles.

The clock enable signal CKE is a signal indicating the validity of the next clock signal.
If E is at the high level, the next rising edge of the clock signal CLK is valid, and if it is at the low level, it is invalid. Further, in the read mode, an external control signal DQM for controlling output enable to the data output buffer DOB is also supplied to the control circuit CONT. When the signal DQM is at a high level, for example, the data output buffer DOB is set to a high output impedance state. You. The test circuit TSTC is activated when a test mode is designated, and performs test operations such as batch write and batch read comparison.

The row address signal is a clock signal C
It is defined by the level of an address signal in a later-described row address strobe / bank active command cycle synchronized with a rising edge of LK (internal clock signal). The input of the two most significant bits is regarded as a bank selection signal in the row address strobe / bank active command cycle. That is, the four memory banks 0 to 3 are determined by the combination of the two bits.
Is selected. Memory bank selection control
Although not particularly limited, activation of only the row decoder on the selected memory bank side, all deselection of the column switch circuits on the unselected memory bank side, connection to the data input buffer DIB and data output buffer DOB only on the selected memory bank side, etc. Can be performed.

The input of a specific address signal in a precharge command cycle to be described later indicates a mode of a precharge operation for a complementary bit line or the like, and its high level indicates that precharge targets are both memory banks. The low level indicates that one memory bank specified by the address signal designating the memory bank is to be precharged. The column address signal is defined by the level of the address signal in a read or write command (column address read command, column address write command described later) cycle synchronized with the rising edge of the clock signal CLK (internal clock). The column address defined in this way is used as a start address for burst access.

Next, the SDR specified by the command
The main operation mode of the AM will be described. (1) Mode register set command (Mo) This command is used to set the mode register.
The command is designated by CS, / RAS, / CAS, / WE = low level, and data to be set (register set data) is given via an address terminal.
Although not particularly limited, the register set data is set to a burst length, a CAS latency, a write mode, or the like. Although not particularly limited, the settable burst length is 1, 2, 4, 8, and full page, the settable CAS latency is 1, 2, 3, and the settable write modes are burst write and Single light.

The above-mentioned CAS latency indicates how many cycles of the internal clock signal should be spent from the fall of / CAS to the output operation of data output buffer DOB in the read operation specified by a column address read command described later. Is what you do. Until the read data is determined, an internal operation time for data read is required, and this is set in accordance with the operating frequency of the internal clock signal. In other words, when using a high-frequency internal clock signal, set the CAS latency to a relatively large value, and when using a low-frequency internal clock signal, set the CAS latency to a relatively small value. I do. Although not particularly limited, in an image processing operation to be described later, the CAS latency can be set to a large value if necessary in order to secure a word line switching time.

(2) Row address strobe / bank active command (Ac) This is a command for validating a row address strobe instruction and selecting a memory bank by an address signal. / CS, / RAS = low level, / CAS , / WE
= High level, where the address supplied to the address terminals excluding the most significant two bits is a row address signal, and the signal supplied to the most significant two bits address terminal is a memory bank selection signal. It is captured. The fetch operation is performed in synchronization with the rising edge of the internal clock signal as described above. For example,
When the command is specified, the word line in the memory bank specified by the command is selected, and the memory cells connected to the word line are electrically connected to the corresponding complementary bit lines.

(3) Column Address Read Command (Re) This command is a command necessary for starting a burst read operation and a command for giving an instruction of a column address strobe. / CS, / CAS =
Instructed by low level, / RAS, / WE = high level. At this time, a column address supplied to an address signal input from a predetermined address terminal assigned to the Y address is taken in as a column address signal. The fetched column address signal is supplied to the column address counter as a burst start address.

In the burst read operation instructed thereby, a memory bank and a word line in the memory bank are selected in a row address strobe / bank active command cycle, and the memory cell of the selected word line is In accordance with the address signal output from the column address counter in synchronization with the internal clock signal, the data is sequentially selected and continuously read. The number of data to be continuously read is the number specified by the burst length. The start of reading data from the data output buffer DOB is performed after waiting for the number of cycles of the internal clock signal defined by the CAS latency.

(4) Column Address Write Command (Wr) When a burst write is set in the mode register as a mode of the write operation, it is a command necessary to start the burst write operation, and the mode of the write operation When single write is set in the mode register, the command is a command necessary to start the single write operation. Further, the command gives an instruction of a column address strobe in single write and burst write. The command is / CS, / CA
S, / WE = low level, / RAS = high level. At this time, the address signal assigned to the Y address is taken in as a column address signal. The fetched column address signal is supplied to the column address counter as a burst start address in burst write. The procedure of the burst write operation instructed in this way is performed in the same manner as the burst read operation. However, there is no CAS latency in the write operation, and the capture of write data is started from the column address / write command cycle.

(5) Precharge command (Pr) This is a command to start a precharge operation for the memory bank selected by A10 and A11.
Instructed by CS, / RAS, / WE = low level, / CAS = high level.

(6) Auto-refresh command This command is required to start auto-refresh, and includes / CS, / RAS, / CA
Instructed by S = low level, / WE, CKE = high level.

(7) Burst stop in full page command This command is required to stop the burst operation for a full page for all memory banks, and is ignored in burst operations other than the full page. This command is for / CS, / WE = low level, / RAS, / CA
Indicated by S = high level.

(8) No operation command (No
p) This is a command instructing that no substantial operation is performed, / CS = low level, / RAS, / CAS, / W
It is indicated by the high level of E.

In the SDRAM, when a burst operation is performed in one memory bank, another memory bank is designated during the burst operation and a row address strobe / bank active command is supplied. The row address operation in the other memory bank is enabled without affecting the operation in one memory bank.

Therefore, as long as data does not collide at the data input / output terminal, during execution of a command whose processing has not been completed, a precharge command or row command for a memory bank different from the memory bank to be processed by the command being executed is executed. An internal operation can be started in advance by issuing an address strobe / bank active command.

Since an SDRAM can input and output data, addresses, and control signals in synchronization with a clock signal CLK (internal clock signal), it is possible to operate a large-capacity memory similar to a DRAM at a high speed comparable to an SRAM. ,
Also, by specifying how many data are to be accessed for one selected word line by burst length, the selection state of the column system is sequentially switched by the built-in column address counter, so that a plurality of data can be read. It will be appreciated that they can be read or written continuously.

FIG. 2 is a schematic layout diagram of one embodiment of a dynamic RAM on which a defect repair circuit (redundant circuit) according to the present invention is mounted. In this figure, four memory banks are provided corresponding to the embodiment of FIG. In FIG. 1, the configuration of the memory mat of the dynamic RAM is mainly shown so as to be understood, and the general configuration of the peripheral circuit is simplified.

In this embodiment, although not particularly limited, the memory array is divided into four as a whole corresponding to banks 0-3. Four memory cell arrays are arranged in a row in the longitudinal direction of the semiconductor chip. Since one memory bank has four memory cell arrays as described above, 16 memory cell arrays are configured in the entire chip. The central portion between the bank 2 and the bank 1 is an indirect circuit area, and bondin bads indicated by squares in a vertical line are exemplarily shown. In the indirect circuit area, an address buffer circuit, a data input buffer, a data output buffer, a clock generation circuit, and the like are appropriately formed corresponding to the bonding pads.

As described above, in each of the memory arrays consisting of a total of four, two in each of the left and right directions with respect to the longitudinal direction of the semiconductor chip, and a total of sixteen in each of the four vertically, The main word line selection circuit MWD and the X redundancy circuit XR are provided in the central portion divided into two at the upper and lower central portions. Although not shown, main word drivers (not shown) are formed above and below each memory cell array of the main word selection circuit MWD, and main word lines extended so as to penetrate the memory arrays divided into the above and below are respectively provided. To be driven. A Y selection circuit Y is provided between the memory cell arrays assigned to the banks 0 and 1 and the banks 2 and 3.
D and Y redundant circuits YR are provided.

In the memory cell array, a plurality of memory mats are arranged in the longitudinal direction and the direction perpendicular thereto. That is, one memory cell is divided into eight in the longitudinal direction to provide eight memory mats, and divided into sixteen in the perpendicular direction to provide sixteen memory mats. In other words, the word line is divided into eight and the bit line is divided into one.
It is divided into six. As a result, the number of memory cells provided in one memory mat is divided into eight and sixteen as described above, and the speed of memory access is increased. In the memory mat described above, sense amplifier regions are arranged on the left and right sides of the memory mat, and sub-word driver regions SWD are arranged on the upper and lower sides of the memory mat as described later. The sense amplifiers SA provided in the sense amplifier area are configured by a shared sense method, and except for the sense amplifiers SA arranged at both ends of the memory cell array, complementary bit lines are provided right and left around the sense amplifier SA, It is selectively connected to the complementary bit line of one of the left and right memory mats.

One memory mat surrounded by the sense amplifier SA and the sub-word driver SWD indicated by a thick line has 256 sub-word lines (not shown), and has complementary bit lines (or data lines) orthogonal thereto. There are 512 pairs. In one memory array, 16 memory mats are provided in the bit line direction, so that about 8K sub word lines are provided as a whole, and 16K are provided as a whole chip. Further, in the one memory array, the memory mat has eight memory mats in the word line direction.
Since a plurality of complementary bit lines are provided, a total of about 4K complementary bit lines are provided. Since four such memory arrays are provided in total, 16K complementary data lines are provided as a whole, and the total storage capacity is 16K × 16K = 256.
It has a large storage capacity such as M bits.

The one memory cell array is divided into eight in the main word line direction. A sub-word driver (sub-word line driving circuit) is provided for each of the divided memory cell arrays 15. The sub-word driver is divided into １ ／ length with respect to the main word line,
A selection signal for a sub-word line extending in parallel with this is formed. In this embodiment, in order to reduce the number of main word lines, in other words, to reduce the wiring pitch of the main word lines, there is no particular limitation. Are arranged four sub-word lines. Thus, one of the sub-word lines divided into eight in the main word line direction and four in the complementary bit line direction is assigned.
In order to select one of the sub-word lines, a sub-word selection driver is provided. This sub-word selection driver
A selection signal for selecting one of the four sub-word selection lines extending in the arrangement direction of the sub-word drivers is formed.

Focusing on the one memory cell array, one memory cell array to be selected from the eight memory cell arrays allocated to one main word line is included.
In the sub-word driver corresponding to one memory mat, one sub-word selection line is selected, and as a result, one sub-word line is selected from 8 × 4 = 32 sub-word lines belonging to one main word line. . As described above, 4K (4096) memory cells are provided in the main word line direction.
/ 8 = 512 memory cells are connected.
Although not particularly limited, in a refresh operation (for example, a self-refresh mode), eight sub-word lines corresponding to one main word line are selected.

As described above, one memory array has a storage capacity of 4K bits in the complementary bit line direction. However, if as many as 4K memory cells are connected to one complementary bit line, the parasitic capacitance of the complementary bit line increases, and a signal level that is read out cannot be obtained due to the capacitance ratio with a fine information storage capacitor. To
It is also divided into 16 in the complementary bit line direction. That is,
The complementary bit lines are divided into 16 by a sense amplifier arranged between the memory mats. Although not particularly limited, the sense amplifier is configured by the shared sense method as described above, and complementary bit lines are provided on the left and right around the sense amplifier 16, except for the sense amplifiers arranged at both ends of the memory cell array. It is selectively connected to either the left or right complementary bit line.

FIG. 3 is a main block diagram for explaining the relationship between the main word line and the sub word line of the memory mat. In FIG.
Two main word lines MWL0 and MWL1 are shown. These main word lines MWL0 are selected by a main word driver MWD0. A main word line MWL1 is also selected by a similar main word driver.

The one main word line MWL0 has:
Eight sets of sub-word lines are provided in the extending direction. FIG. 2 exemplarily shows two sets of the sub-word lines as representatives. As the sub-word lines SWL, a total of eight sub-word lines of even numbers 0 to 6 and odd numbers 1 to 7 are alternately arranged in one memory mat. Except for even numbers 0 to 6 adjacent to the main word driver and odd numbers 1 to 7 arranged on the far end side (opposite side of the word driver) of the main word line, the sub word drivers SWD arranged between the memory mats are: A selection signal for the sub-word lines of the left and right memory mats centering on this is formed.

As described above, the memory mat is divided into eight in the main word line direction. However, as described above, the sub word lines corresponding to the two memory mats are simultaneously selected by the sub word driver SWD substantially. ,
It is practically divided into four. In the configuration in which the sub-word lines are divided into even numbers 0 to 6 and even numbers 1 to 7 as described above, and the sub-word drivers SWD are arranged on both sides of the memory mat, respectively, the sub-word lines SWL arranged at high density according to the arrangement of the memory cells Can be relaxed twice in the sub-word driver SWD, and the sub-word driver SWD and the sub-word line SWL0 can be efficiently laid out.

The main word driver MWD drives a main word line as a selection signal commonly to the four sub word lines 0 to 6 (1 to 7). A sub-word selection line FX for selecting one sub-word line from the four sub-word lines is provided. The sub-word selection lines FX are composed of eight lines, such as FX0 to FX7, of which the even-numbered sub-word selection lines FX0 to FX6 are supplied to the sub-word drivers 0 to 6 in the even-numbered columns, and the odd-numbered sub-word selection lines FX1 to FX7 are The odd-numbered sub-word drivers are supplied to the sub-word drivers 1-7. Although not particularly limited, the sub-word select lines FX0 to FX7 are formed by the second metal wiring layer M2 in the peripheral portion of the array, and the main word lines MWL0 to MWL0 also formed by the second metal wiring layer M2. At the intersection of MWLn, the third
It is constituted by the metal wiring layer M3 of the layer.

FIG. 4 is a main block diagram for explaining the relationship between the main word line and the sense amplifier. In the figure, one main word line MWL is shown as a representative. This main word line MWL
Is selected by the main word driver MWD. A sub-word driver SWD corresponding to the even-numbered sub-word line is provided adjacent to the main word driver.

Although not shown in the figure, a complementary bit line (Pair Bit Line) is provided so as to be orthogonal to a sub-word line arranged in parallel with the main word line MWL.
In this embodiment, although not particularly limited, the complementary bit lines are also divided into even columns and odd columns, and the sense amplifiers SA are distributed to the left and right corresponding to each of the memory mats. Although the sense amplifier SA is of a shared sense type, the sense amplifier SA at the end does not have a substantially complementary bit line.

In the configuration in which the sense amplifiers SA are dispersedly arranged on both sides of the memory mat as described above, since the complementary bit lines are allocated to the odd columns and the even columns, the pitch of the sense amplifier columns can be reduced. it can. In other words, it is possible to secure element areas for forming the sense amplifiers SA while arranging complementary bit lines at high density. Local input / output lines are arranged along the arrangement of the sense amplifiers SA on both sides, and each has two pairs of local input / output lines. As described above, one column selection line Y
Column switch MOSFET controlled by S
T, two pairs of complementary bit lines are selected corresponding to the sense amplifiers arranged on both sides of the memory mat.
Connected to local I / O lines for each pair.

A total of four pairs of local input / output lines are connected to four pairs of main input / output lines via a main switch circuit that is switch-controlled by a mat select signal.
The gate of the column switch MOSFET is connected to the one corresponding column selection line YS to which a selection signal of a column decoder (COLUMN DECORDER) is transmitted. The column selection line YS is provided so as to extend through the memory mats divided into 16 as shown in FIG. 2, and a corresponding column switch M of each memory mat is provided.
It is commonly connected to the gate of the OSFET.

FIG. 5 is a main part circuit diagram of an embodiment of the sense amplifier section of the SDRAM according to the present invention.
FIG. 1 exemplarily shows a sense amplifier and one memory mat (memory array) associated therewith. The memory mat arranged on the left side of the sense amplifier is omitted, and the shared switch MOSFETs (Q1, Q2) connected to the complementary bit line are illustrated by way of example.

The dynamic memory cells are exemplarily represented by four normal circuits and four redundant circuits corresponding to the sub-word lines SWL0 and SWL1 provided in the right memory mat. . The dynamic memory cell includes an address selection MOSFET Qm and an information storage capacitor Cs. MOSF for address selection
The gate of ETQm is connected to sub-word line SWL0, and the drain of MOSFET Qm is connected to complementary bit line B
One of the LT and the BLB is connected to the BLT, and the source is connected to the information storage capacitor Cs. The other electrode of the information storage capacitor Cs is shared and supplied with a plate voltage.

The pair of complementary bit lines BLT and BLB are arranged in parallel as shown in the figure, and are appropriately crossed as needed to balance the capacitance of the bit lines.
The complementary bit lines BLB and BLT are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q3 and Q4. The unit circuit of the sense amplifier includes N-channel MOSFETs Q5, Q6 and P-channel MOSFETs Q7, Q8, whose gates and drains are cross-connected to form a latch. The sources of the N-channel MOSFETs Q5 and Q6 are connected to a common source line SAN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line SA.
Connected to P. The common source lines SAN and SAP have an N-channel MOSFET and a P-channel MOSFET.
A power switch MOSFET of each SFET is provided, and the power switch MOSFET is turned on by an activation signal of the sense amplifier to supply a voltage necessary for the operation of the sense amplifier.

A MOSFET Q11 for short-circuiting the complementary bit line is provided at the input / output node of the unit circuit of the sense amplifier.
And a precharge circuit comprising switch MOSFETs Q9 and Q10 for supplying a half precharge voltage HVC to the complementary bit line. These MOSFET Q9
The precharge signal PC is commonly supplied to the gates of Q11 to Q11.

The MOSFETs Q12 and Q13 form a column switch that is switch-controlled by the column selection signal YS. In this embodiment, one column selection signal YS
Thus, two pairs of bit lines can be selected. When the sub-word line SWL0 of the memory mat on the right side is selected, the sense amplifier similarly arranged on the right side with respect to the memory mat is also activated. A column switch MO similar to the above is also provided in the right sense amplifier (not shown).
An SFET is provided, and two pairs of bit lines are selected. Therefore, focusing on one memory mat, a total of four pairs of complementary bit lines are selected.

That is, focusing on the memory mat described above, two sense amplifiers are arranged on both sides of the bit line,
Two pairs are alternately connected corresponding to the two sense amplifiers. The column selection signal YS is supplied to two pairs of bit lines BLT and B which are exemplarily shown by a sense amplifier.
A total of four pairs of complementary bit lines corresponding to the LB and the like and the remaining two pairs of bit lines (not shown) provided in the sense amplifier (not shown) can be selected. These two pairs of complementary bit lines are connected to local input / output lines SIO0B, SIOB
OOT and SIO1B, SIO1T, and the local input / output line S
It is connected to IO2B, SIO2T and SIO3B, SIO3T, and is connected to a total of four pairs of main input / output lines by a mat select signal. Similarly to the above, the sense amplifier and the redundant bit line RB are also provided for the redundant column selection line RYS.
LT, RBLB, etc. are provided.

FIG. 6 is a schematic layout diagram showing one embodiment of a dynamic RAM on which a defect repair circuit (redundant circuit) according to the present invention is mounted. The configuration of the memory array MARY of the dynamic RAM shown in FIG. 11 corresponds to that of the embodiment of FIG. In the figure,
A layout centered on the above-mentioned redundant circuit is shown together with its access path.

In this embodiment, the memory array MARY is
As a whole, four chips are allocated in the longitudinal direction of the chip corresponding to the banks 0 to 3 as described above. As described above, in the memory array MARY corresponding to one memory bank, a Y redundant circuit YR is provided at a central portion with a Y decoder YD interposed between adjacent banks 0, 1, 2, and 3. The Y redundant circuit YR is provided with a fuse circuit FUSE described later. The central portion in the longitudinal direction as described above is an indirect circuit area, and peripheral circuits such as the bond pad and the address buffer circuit ADB, which are vertically arranged, are arranged.

As described above, in the memory array MARY constituting each of the memory banks 0 to 3, the memory array MARY is divided into two at the upper and lower center portions in the longitudinal direction of the chip, and each of the memory arrays MARY is divided into two. In a central portion, a main word line selection circuit MWD and an X redundancy circuit XR
Is provided. The main word line selection circuit MWD includes an X decoder XD. That is, the main word selection circuit MWD includes the X decoder XD and a main word driver for driving the main word line MWL. The X redundancy circuit XR is configured to be sandwiched between two main word line selection circuits MWD corresponding to the memory arrays MARY arranged above and below. The X redundant circuit XR includes a fuse circuit F as described later.
USE is provided.

In the arrangement of the redundant circuits XR and YR as in this embodiment, the address signal input from the address buffer ADB is applied to the respective address selection circuits XD and XD.
Since the YD and the redundant circuits XR and YR can be configured to be the shortest distance, the signal delay there can be minimized, and the operation can be speeded up while performing defect repair.

FIG. 7 is a block diagram for explaining a redundant system according to the present invention. FIG. 1A shows an X-system circuit, and FIG. 1B shows a Y-system circuit. (C) shows an example of a redundant circuit in the case of using an open fuse that is cut by a laser cutter.

In the redundancy system as shown in (a), an address signal input from an address pad XADB is supplied to an address buffer XADB, and is predecoded by a predecoder XPD. Supplied. In the redundant circuit XR, if a defective address is determined, the selection of a defective word line is prohibited for the adjacent X decoder XD, and the redundant word line is selected by driving the redundant decoder XRS. Similarly, in (b), the address signal input from the address pad YADB is supplied to the address buffer YADB, and the predecoder Y
Each of them is pre-decoded by the PD, and the Y decoder Y
D and supplied to the redundant circuit YR to switch the defective bit line to the redundant bit line in the same manner as described above.

On the other hand, when a conventional open fuse is used, the predecoder arranged adjacent to the memory array is different from the fuse circuit FUSE provided near the address pad due to layout restrictions. The selection signal from the PD is returned to the address pad side, and a signal for prohibiting the selection operation is sent to the predecoder based on the result of the comparison of the defective address. Since the bit line is selected, the signal transmission path is lengthened, the load is increased, and high-speed operation is hindered.

FIG. 8 is a circuit diagram of a redundant circuit according to one embodiment of the redundant system according to the present invention. FIG.
The system circuit is shown. In this embodiment, although not particularly limited, an example is shown in which one redundant main word line RMRLB is provided for one memory array MARY. That is, the memory array MARY has a total of 3
Two main word lines MWLB0 to MWLB31 and 1
It has one redundant main word line RMWLB. Since eight sub-word lines are assigned to each of the main word lines MWLB0 to MWLB31, 32 × 8 = 256 sub-word lines are provided in one memory mat. A selection signal for selecting one of the 32 main word lines MWLB0 to MWLB31 is formed by the X decoder XD.

In this embodiment, each of the main word lines M
Redundant circuits XR0-X corresponding to WLB0-MWLB31
R31 is provided. These redundant circuits XR0 to XR31
Among them, XR0, XR1, XR15, XR16 and XR
Circuits 30 and XR31 are illustratively shown as representatives. These redundant circuits XR0 to XR31 include a fuse F1 and a fuse F1 as represented by one redundant circuit XR0.
A MOSFET Q1 for reading the data, a MOSFET Q2 for latching stored information, and a CMOS switch MOSFET Q3 switch-controlled by the stored information.
And Q4.

One end of the fuse F1 is connected to a power supply terminal, and between the other end and the ground potential of the circuit, there is provided a MOSFET Q1 which is turned on by a signal FSET which is temporarily set to a high level when the power is turned on. . Fuse F above
1 is supplied to the input of the inverter circuit N1, and its output signal is supplied to the gate of the MOSFET Q2 provided in parallel with the MOSFET Q1 to latch the low level when the fuse F1 is blown. To form a latch circuit. The inverter circuit N1 is used to form a latch circuit as described above and to form a complementary signal between its input and output. The inverter circuit N1 has a P-channel MOSFET Q4 and an N-channel MOSFET Q4.
3 as a control signal for the CMOS switch. The other redundant circuits XR1 to XR31 have the same configuration as above.

When the fuse F1 is not cut, a high level is supplied to the input of the inverter circuit N1 through the fuse F1 to form a low level output signal. As a result, the MOSFET Q2 is turned off, and the CMOS switch MOSFETs Q3 and Q4 are also turned off. Therefore, in a state where the fuse F1 and the like are not blown, the current is consumed only during the period when the set signal FSET is temporarily set to the high level.

X decoder XD receives a predecode signal (not shown) and receives the main word select signals MSB0 to MSB0.
The MSB 31 is formed. These selection signals MSB0-M
Of the SBs 31, the one corresponding to the main word line MWLB to be selected is set to the low level. Select signals MSB0 to MSB31 formed by X decoder circuit XD
Is transmitted to the main word driver MWD, and one of the selection signals MSB0 to MSB31 corresponding to the low level is set to the low level selection state.

The switch circuits of the redundancy circuits XR0 to XR31 transmit selection signals MSB0 to MSB31 formed by the X decoder circuit XD, respectively. That is, in the redundant circuit XR of this embodiment, the selection signal of the redundant main word line EMWLB is formed by using the selection signal as it is in the X decoder circuit XD. For example, when a defect exists in the main word line MWLB0, the fuse F1 of the corresponding redundant circuit XR0 is cut. Thereby, MOSFET
Q2 is turned on and MOSFE of the CMOS switch is turned on.
TQ3 and Q4 are turned on to transmit the selection signal WSB0 of the X decoder circuit XD.

The redundant decoder circuit XRD includes a non-gate circuit G1 and an inverter circuit N3.
A selection signal for a redundant main word line RMWLB is formed in response to a low-level selection signal from the redundancy circuit XR0. At the same time, the NOR gate circuit G3 provided in the main word driver is controlled by setting the output signal of the NAND gate circuit G1 to the high level, and the output signal is forcibly set to the low level, and the defective main word line MWLB
0 is forcibly set to a high-level non-selection state. As a result, the redundant main word line RMWLB is set to the low level selected state in place of the defective main word line MWLB0.

Since the NAND gate circuit G1 transmits a signal through the switch circuit,
It can be composed of a wired-OR logic circuit. That is, the output side of the redundant circuits XR0 to XR31 may be connected in common to provide a pull-up resistor, and the signal of the pull-up resistor may be output through the inverter circuit. In this configuration, the main word lines MWLB0-3
When there is no defect in 1, none of the fuses is blown, and the switch circuits of the redundant circuits XR0 to XR31 are turned off. Therefore, a high-level non-selection signal is formed by the pull-up resistor, and the redundant main word line RMWLB is set to a high-level non-selection state through the inverter circuit and the inverter circuit N3 as a driver.

When one of the fuses is blown and the X-decoder circuit XD generates a low-level selection signal so as to select the corresponding main word line,
Since a low-level signal is generated by the pull-up resistor according to the selection signal, the operation of selecting a defective main word line is inhibited as described above, and the redundant make-in word line RMWLB is set to a low-level selection state. In this configuration, the switching between the defective main word line and the redundant main word line is performed depending on whether the decoding result of the X decoder circuit XD is transmitted as it is through the switch circuit, and the redundant circuit XR and the decoder circuit XD are switched. Are arranged adjacent to each other, and the operation of the normal circuit can be switched between the defective main word line and the redundant main word line by the shortest signal path.

FIG. 9 is a circuit diagram of a redundant circuit according to another embodiment of the redundant system according to the present invention. FIG. 1 shows a Y-related circuit. In this embodiment, although not particularly limited, an example is shown in which one redundant column selection line RYS is provided for one memory array MARY. That is, the memory array MARY has a total of 1
It has 28 column selection lines YS0 to YS127 and one redundant column selection line RYS. Each of the above column selection lines YS0
To YS127, four pairs of complementary bit lines are selected, so that 128 × 4 = 5 in one memory mat
Complementary bit lines such as 12 pairs will be provided.

In this embodiment, the redundancy circuits YR0 to YR0 corresponding to the respective column selection lines YS0 to YS127 are similarly provided.
YR127 is provided. These redundant circuits YR0 to YR
Of the 127, YR0, YR1 and YR126 and YR1
Twenty-seven circuits are illustratively shown as representatives. These redundant circuits YR0 to YR127 are connected to one redundant circuit YR.
0, a fuse F2 similar to the X-system redundant circuit XR0 and a MOSFE for reading the fuse F2.
It comprises a TQ5, a MOSFET Q6 for latching stored information, and CMOS switch MOSFETs Q7 and Q8 which are switch-controlled by the stored information. The other redundant circuits YR1 to YR127 have the same configuration as described above.

The Y decoder YD receives a predecode signal (not shown), and receives the column selection lines YS0 to YS127.
To form a selection signal corresponding to. Also in the redundant circuit YR of this embodiment, the selection signal of the redundant column selection line RYS is formed by using the selection signal as it is in the Y decoder circuit YD in the same manner as described above. For example, when a defect exists in the column selection line YS0, the fuse F1 of the corresponding redundant circuit YR0 is cut. As a result, the MOSFET Q6 is turned on, and the CMOS
The switch MOSFETs Q7 and Q8 are turned on to transmit the selection signal of the Y decoder circuit YD, and the redundant decoder circuit YRD supplies the redundant column selection line RYS.
Is formed. At the same time, by controlling the output signal of the NAND gate circuit G2 of the redundant decoder circuit YRD to a high level, a similar NOR gate circuit (not shown) provided in the column-selected driver YSD is controlled.
The output signal is forced to the low level, and the defective column selection line YS0 is forcibly set to the high-level non-selection state. Thus, the redundant column selection line RYS can be set to the low-level selection state in place of the defective column selection line YS0.

Also in this embodiment, the NAND gate circuit G
Since the signal 2 is transmitted through the switch circuit, it can be constituted by a wired-OR logic circuit. That is, the output side of the redundant circuits YR0 to YR127 may be connected in common to provide a pull-up resistor, and the signal of the pull-up resistor may be output through the inverter circuit. With this configuration, when no defect exists in the column selection lines YS0 to YS127 of the memory mat,
Since none of the fuses is blown, the switch circuits of the redundant circuits YR0 to 127 are turned off. Therefore, since the high-level non-selection signal is formed by the pull-up resistor, the redundant column selection line RYS is set to the high-level non-selection state through the inverter circuit and the inverter circuit N4 as a driver.

FIG. 10 is a cross-sectional structural view of an element for explaining a non-open fuse used in the above redundant circuit. In the step (a), a final (uppermost) metal wiring layer M3 forming an electronic circuit having a desired circuit function is processed and formed. The metal wiring layer M3 is formed of a third aluminum layer formed on an interlayer insulating film INS4 that is electrically separated from wirings and the like below the metal wiring layer M3.
It constitutes a part of a wiring path of the electronic circuit, and constitutes a program cutting portion HP in which the function of the electronic circuit is changed by selective cutting thereof, and a pad (such as a bonding pad) used for connection with an external terminal.

In the step (b), a first insulating film INS5 is formed except for the surface of the pad portion. This first insulating film INS5 is formed of the same as the final passivation film in the conventional semiconductor integrated circuit device. For example, as the insulating layer INS5, hydrogen annealing is performed after depositing a silicon oxide film 0.3 μm by plasma CVD using tetraethoxysilane as a raw material. This hydrogen annealing is performed to reduce the interface order of the MOSFET,
As the process temperature, for example, about 450 ° C. is used. In each of the steps described below, the process temperature is 45
The temperature can be suppressed to 0 ° C. or less, and the effect of annealing can be maintained. Subsequently, a silicon nitride film 1.0 μm deposited by a plasma CVD method is laminated. This first insulating film INS5
Has a role of preventing the wiring and the program cutting portion HP from being damaged at the time of the probe or being deteriorated by moisture.

As described above, unlike the final passivation film in the conventional semiconductor integrated circuit device, the first insulating film INS5 is formed by the metal wiring layer M3 during the electrical test of the electronic circuit formed on the semiconductor wafer. It temporarily protects the wiring and program cutting portions, or omits the silicon nitride film deposited by the plasma CVD method to facilitate the selective opening formation in the next step (c). It may be. When the semiconductor integrated circuit device is a memory circuit such as a dynamic RAM, the operation of memory cells of all bits is tested to check the address of a defective memory cell. Then, it is checked whether the defective memory cell can be replaced with the redundant memory cell by the row replacement, the column replacement, or the bit-by-bit replacement method described in detail later. Although not particularly limited, in the case of a wafer probe, if the prober is a ball type, metal damage to the pad portion can be reduced.

In the step (c), if the chip can be made a good product by replacement, the row address or the column address of the defective memory cell is programmed by selectively cutting the fuse HP by the following method. . The fuse HP is formed by using the final wiring layer M3. A resist is applied to the wafer on which the wafer probe has been completed, and E
Fuse HP to be cut by B (electron beam) lithography
Open the upper resist.

In the step (d), the first insulating film INS5 is dry-etched using the resist as a mask, and the fuse H
The etching is stopped when the cut portion of P is exposed.

In the step (e), the exposed fuse H
The cut portion of P is etched and cut. For example, dry etching is used for these etchings. The processing size is the third layer M3 which is the uppermost layer.
Since the pitch of the third layer M3 itself is not very fine, in other words, the wiring width and the pitch cannot be finely formed in the upper layer in the multilayer wiring structure. The power of the plasma can be reduced, and the damage to the device can be reduced.

In the step (f), after depositing a second insulating layer INS6 as a final passivation film on the entire surface, the second insulating film INS6 in the bonding pad portion is removed. The second insulating film INS6 is composed of, for example, a laminated film of a 0.3 μm silicon oxide film and a PIQ deposited by a plasma CVD method. If it is desired to enhance the function of preventing intrusion of moisture, a silicon nitride film 1um deposited by a plasma CVD method before the PIQ may be further laminated. Although not shown in the figure, the semiconductor wafer is diced for each chip and assembled into a package.

According to the present invention, the size of the fuse can be reduced to about the minimum wiring width of the uppermost wiring layer M3, and the pitch of the fuses HP can be reduced.
The minimum pitch can be reduced to 3. Therefore, even when a large number of such fuses HP are mounted, the chip area can be reduced. This is because EB lithography is used when forming the above-mentioned cutting opening, so that fine processing can be performed as compared with a laser beam, and since the cut portion of the fuse HP is covered with an insulating layer, moisture is applied to the wafer. This is because there is little intrusion and an extra guard ring is unnecessary. Due to such a feature, a redundant circuit can be formed in accordance with the pitch of the main word line and the column selection line and adjacent to the decoder circuit below the lead because of the non-opening.

Unlike the general photolithography, the EB lithography does not require a mask. Therefore, it is possible to easily program whether or not a fuse is cut by changing the exposure pattern data of the EB. Further, in EB lithography, the time required for exposing a cut portion of one fuse is extremely high, on the order of microseconds. Therefore, even if the time required for resist coating and etching is taken into consideration, the subsequent opening and cutting steps are not required. Since the processing is performed collectively in units of semiconductor wafers, the number of fuses in one chip is provided in large numbers corresponding to the main word lines and column selection lines as described above, and is cut one by one by laser. The fuse blowing process can be performed much faster than it does.

FIG. 11 is a plan view showing one embodiment of the fuse circuit according to the present invention. In the figure, (a)
Shows a lower layer pattern, and (b) shows an upper layer (uppermost layer wiring) pattern. AA ′ in FIG.
FIG. 12A is a cross-sectional view, and FIG.
2 (b). Hereinafter, the fuse circuit will be described with reference to FIGS.

L is a MOSFET composed of n + regions
FG, which extends in the lateral direction so as to be sandwiched between them, is a gate electrode, and constitutes the MOSFET Q1 and the like. M
Reference numeral 1 denotes a first-layer metal wiring, M2 denotes a second-layer metal wiring, and M3 denotes a third-layer (uppermost-layer) metal wiring. Active region (source) sandwiched between the pair of word lines
Are two MOSFETs corresponding to the pair of word lines.
Are connected in common to the above-mentioned M1 via a contact hole CONT, and are supplied with the ground potential Vss of the circuit.

The drain side of the MOSFET is connected to a first metal layer M1 through a contact hole CONT, and this metal layer M1 is connected to a second metal layer M1 through a through hole TC1.
The third metal layer M3 is connected to the third metal layer M2 via the through hole TC2. In the cross-sectional view of FIG. 7, INS1 is an interlayer insulating film for separating the active region L or FG from M1.
S2, IN3 An interlayer insulating film separating M1 and M2, INS4 is an interlayer insulating film separating M2 and M3, and INS5 and INS5 are protective films of M3.

In FIG. 11B, the M3 and TC
Two patterns are shown. The above-mentioned M3 is used as a power supply line, and a portion surrounded by oblique lines is a cutting region and forms a fuse HP. FIG. 1 shows that the through-hole TC2 indicated by the arrow overlaps in the direction perpendicular to the substrate.
1 (a) is stacked below (b). In other words, one of the fuses HP is connected to the third metal layer M3 extending in the vertical direction that constitutes the power supply line, and the other end is connected to the second metal layer M2 via the through hole TC2. The metal layer M2 is connected to the first metal layer M1 via the through hole TC1. The first metal layer M1 is connected to an active region L (drain) such as the MOSFET Q1 via a contact hole CONT.

FIG. 13 is a sectional view of a DRAM memory cell. SN is a lower electrode of the storage capacitor, INC is a capacitive insulating film (dielectric) of the storage capacitor, and TG is a plate electrode of the storage capacitor. SCONT is a through hole that connects the source and drain (active region L) of the selection MOSFET and the storage capacitor lower electrode SN. INS2 is an interlayer insulating film separating M1 and SN, and INS3 is an interlayer insulating film separating TG and M2. As described above, the open fuse according to the present invention can be obtained by simply adding the EB lithography of the final metal layer to the DRAM process of FIG. 13 without adding other layers, as is clear from the comparison with FIG. Can be created.

FIG. 14 is a flowchart for explaining a method of manufacturing a semiconductor integrated circuit device having the above-mentioned fuse element. In the step (a), an uppermost layer (for example, M3) is formed. That is, in the step of forming the uppermost layer M3, the wiring program element (fuse) is also formed. In this step (a), a surface protection film (the first insulating film) is formed except on the bonding pad.
In the step (b), an operation test using a wafer probe is performed. In the step (b), when the surface protective film does not have sufficient water resistance, the operation test is performed in a dry atmosphere.

In the step (c), processing of the program element, that is, an opening is formed in the resist above the wiring program element to be cut by the EB lithography EB in accordance with the above test result, and the opening is subjected to dry etching as a mask. The cut portion of the wiring program element is exposed, and the exposed cut portion of the wiring program element is etched and cut.
In the step (d), an insulating film is formed as a surface protective film except for the bonding pad portion. In step (e),
Dicing is performed, and the semiconductor chips formed on the wafer are divided individually. In the step (f), the divided semiconductor chips are sorted out and packaged as non-defective products. In the step (g), initial defects are washed out by aging or burn-in, and those which are determined to be good by the final test are shipped.

The operation and effect obtained from the above embodiment are as follows. (1) A non-open fuse which is provided adjacent to the word line or the bit line in a one-to-one correspondence with a decode circuit for forming a word line or a bit line selection signal and is selectively cut off A fuse circuit comprising a switch circuit that is switch-controlled in accordance with whether the fuse is cut or not, taking a logical sum signal of a selection signal of a normal word line or a bit line passed through the switch circuit, and Alternatively, by providing a redundancy decoder for forming a selection signal for a redundant bit line, the effect is obtained that the access path can be minimized and the operation can be speeded up.

(2) The redundancy word line or redundancy bit line selection signal formed by the redundancy decoder is also used to inhibit the normal word line or normal bit line selection operation. The effect that a defective word line or a defective bit line with a simple configuration can be switched to a redundant word line or a redundant bit line can be obtained.

(3) A plurality of word lines are arranged in a main word line and a length divided in an extending direction of the main word line, and a plurality of word lines are arranged in a bit line direction crossing the main word line. A hierarchical word line composed of sub-word lines connected to address select terminals of a plurality of dynamic memory cells or a divided word line system, and the fuse circuits are provided in one-to-one correspondence with the main word lines. By doing so
The effect is obtained that a non-open fuse forming region using a relatively wide pitch can be secured.

(4) As the non-opening fuse, a program having a cut surface constituted by the uppermost wiring layer and having been etched and removed by using a selective opening of the first insulating film formed thereon. The surface of the first insulating film excluding the wiring portion and the upper surface of the pad, the cut surface of the program wiring portion, and the photosensitive portion which is used for the cutting and is irradiated with an electron beam or a light spot corresponding to the test result By using the second insulating film covering the opening surface of the opening formed by using the resist film opening corresponding to the above, the device can be formed with a fine element size and can be selectively cut in a short time. In addition, there is an effect that a redundant circuit can be arranged adjacent to a word line or bit line selection circuit.

(5) Since the uppermost wiring layer is a metal wiring layer and a wiring layer formed in the same step as the bonding pad is used, the processing size is relatively large, and EB lithography is used. Cutting can be easily performed, and the effect that water resistance as a surface protective film can be ensured by using the second insulating film as a final passivation film is obtained.

(6) By using a dry etching technique for selectively cutting the fuse, since the wiring portion is the uppermost metal layer, the plasma power can be reduced, and the damage to the device can be reduced. The effect is obtained.

Although the invention made by the present inventors has been specifically described based on the embodiments, the invention of the present application is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, FIG.
In the above, the memory bank may have a two-bank configuration such that a bank 0 and a bank 1 are provided on both sides of the indirect circuit area. The layout configuration on the semiconductor substrate is not limited to the configuration shown in FIG. 2 and can take various embodiments. The selection level of a word line or a column selection line may be a low level or a high level as a selection level. Depending on such a selection level, a logic circuit of a logic gate of the redundant circuit may be used. Is determined, and a pull-down resistor or the like is provided in the wired logic. The non-opening fuse may be any as long as it is the above-mentioned non-opening fuse. According to the present invention, in addition to the dynamic RAM and the synchronous DRAM, a ferroelectric film employing a ferroelectric film as an information storage capacitor is provided.
It can be widely used for a defect relief circuit of various semiconductor memory devices such as a RAM or a static RAM.

[0097]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a non-opening fuse which is provided adjacent to a decode circuit for forming a word line or bit line selection signal and is provided in one-to-one correspondence with the word line or bit line and is selectively cut off, A fuse circuit comprising a switch circuit that is controlled in accordance with the presence or absence of disconnection of the redundant word line or redundant bit by taking a logical sum signal of a selection signal of a normal word line or a bit line passed through the switch circuit; By providing a redundant decoder for forming a line selection signal,
The access path can be minimized, and the operation can be speeded up.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a schematic layout diagram showing an embodiment of a dynamic RAM on which a defect relief circuit according to the present invention is mounted.

FIG. 3 is a main block diagram for explaining a relationship between a main word line and a sub word line of the memory mat of FIG. 2;

FIG. 4 is a main block diagram for explaining a relationship between a main word line and a sense amplifier in FIG. 2;

FIG. 5 is a main part circuit diagram showing one embodiment of a sense amplifier section of the SDRAM according to the present invention;

FIG. 6 is a schematic layout diagram showing one embodiment of a dynamic RAM on which a defect relief circuit (redundant circuit) according to the present invention is mounted.

FIG. 7 is a block diagram for explaining a redundant system according to the present invention.

FIG. 8 is a circuit diagram of a redundant circuit showing one embodiment of a redundant system according to the present invention.

FIG. 9 is a circuit diagram of a redundant circuit showing another embodiment of the redundant system according to the present invention.

FIG. 10 is an element cross-sectional structure diagram of an embodiment for explaining a non-opening fuse used in the redundant circuit.

FIG. 11 is a plan view showing one embodiment of a fuse circuit according to the present invention.

FIG. 12 is a sectional view of the fuse circuit of FIG. 11;

FIG. 13 is a sectional view of an element structure of a memory cell portion.

FIG. 14 is a flowchart for explaining a method of manufacturing a semiconductor integrated circuit device provided with the fuse element.

[Explanation of symbols]

MARY: memory array, XD: X decoder, WD: word driver, SA: sense amplifier, XRD, YPD ...
Predecoder circuit, YDEC: Y decoder, DOC: Data output control circuit, DOB: Data output buffer, DI
B: Data input buffer, RADB: Row address buffer, CADB: Column address buffer, CONT ...
Control circuit, TSTC: Test circuit, CKG: Clock generation circuit, YR, XR: Redundancy circuit, REF: Refresh control circuit, MWD: Main word driver, YD: Column decoder, SWD: Sub-word driver, YSD: Column driver, YPD ... Predecoder, F1 to F2 fuse, Q1 to Q13 MOSFET, N1 to N5 inverter circuit, G1 to G3 gate circuit, TC1 to TC
2: Through hole, FG: First polysilicon layer, M
1 ... first metal layer, M2 ... second metal layer, M3 ... 3
Layer metal layer, HP: fuse element, INS1 to INS
6 ... Insulating film.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/8242 H01L 27/10 621B 681F 681A

Claims (8)

[Claims] A memory mat comprising a plurality of memory cells provided at intersections between a plurality of normal word lines and redundant word lines and a plurality of bit lines arranged to intersect the word lines; A non-opening fuse which is arranged adjacent to a decode circuit for forming a selection signal, is provided in one-to-one correspondence with the normal word line, and is selectively cut corresponding to a defective word line, and An X-redundant circuit including a switch circuit that is switch-controlled in accordance with the presence / absence of disconnection; and a row that takes a logical sum signal of a normal word line select signal passed through the switch circuit and forms the redundant word line select signal A semiconductor memory device comprising a redundancy decoder. 2. The semiconductor device according to claim 1, wherein the redundancy word line selection signal formed by said row redundancy decoder is also used to inhibit the normal word line selection operation. Storage device. 3. The word line has a main word line and a length divided in an extension direction of the main word line, and a plurality of word lines are arranged in a bit line direction intersecting the main word line. And a sub-word line to which address selection terminals of a plurality of dynamic memory cells are connected. One of the plurality of sub-word lines assigned to the one main word line is a main word line selection signal. And a selection signal of a sub word selection line. The fuse circuit is provided in one-to-one correspondence with the main word line. 3. The semiconductor memory device according to claim 1 or 2. 4. A memory mat comprising a plurality of memory cells provided at intersections between a plurality of word lines and a plurality of normal bit lines and redundant bit lines arranged so as to intersect with each other; A non-open fuse which is arranged adjacent to a decode circuit for forming a select signal of the bit line select signal and which is provided in one-to-one correspondence with the bit line select signal and which is selectively cut off corresponding to a defective bit line; A column that takes a logical sum signal of a bit line selection signal passed through the switch circuit and forms a redundant bit line selection signal, including a Y redundant circuit including a switch circuit that is controlled in accordance with the presence / absence of a fuse cut; A semiconductor memory device comprising a redundancy decoder. 5. A semiconductor device according to claim 4, wherein the redundant bit line selection signal formed by said column redundancy decoder is also used to inhibit the normal bit line selection operation. Storage device. 6. The non-open fuse according to claim 1, wherein said non-open fuse comprises a top wiring layer, and has a cut surface etched and removed by using a selective opening of a first insulating film formed thereon. Part, the surface of the first insulating film excluding the upper surface of the pad, the cut surface of the program wiring part, and the photosensitive part used for cutting the same and irradiated with an electron beam or a light spot corresponding to the test result. And a second insulating film that covers an opening surface of the opening formed by using a resist film opening corresponding to (1), (2) and (3). The semiconductor memory device according to claim 4 or claim 5. 7. The semiconductor memory device according to claim 6, wherein said uppermost wiring layer is a metal wiring layer, and said second insulating film is a final passivation film. 8. The method of selectively cutting the non-opening fuse, comprising:
7. The semiconductor memory device according to claim 6, wherein the device is based on a dry etching technique.