JPH11224488A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory which can perform erasing operation independently. SOLUTION: This device is constituted by arranging plural memory cells consisting of non-volatile memory elements being electrically erasable in a matrix state, and dividing them into plural memory blocks in the direction of word line. In this case, this device is provided with a writing mode writing information in a memory cell, a read-out mode reading out a state of threshold voltage of a memory cell, and an erasing mode performing erasing operation applying voltage for keeping threshold voltage of a memory cell in one memory block out of plural memory blocks in the prescribed range and operation reading out a state of threshold voltage of a memory cell in a memory block, also provided with an erasing control circuit performing continuation and stop of erasing operation based on information at the time of read-out operation in an erasing mode. And the erasing control circuit comprises an address generating circuit OSC1 for selecting a memory cell in a memory block.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having an electric batch erase function, and more particularly to a nonvolatile semiconductor memory device capable of suppressing variation in threshold voltage after a batch erase operation.

[0002]

2. Description of the Related Art Conventionally, nonvolatile semiconductor memory devices whose storage contents can be rewritten include EPROM and EE.
PROMs have been widely used. EPROMs have been characterized by high integration and the associated low cost, and EEPROMs have been characterized by high functionality (ease of use) in which the stored contents can be rewritten electrically (that is, mounted on the device) bit by bit. However, there is a strong demand for a nonvolatile semiconductor memory device having both of these features. The flash type EEPROM has a strong requirement that the electrical rewriting function is limited to a chip (or a block) for erasing. Numerous storage elements with a new structure have been proposed which are positioned as satisfying the requirements, and for achieving this.

The memory element disclosed in Japanese Patent Application Laid-Open No. 62-276878 is a typical example. Hereinafter, this storage element is referred to as a FAST (Floating gate Asymmetric Sourc
e and drain Tunnel oxide) type. FIG.
FIG. 2 is a view schematically showing a cross-sectional structure thereof. This storage element has one element / same as the FAMOS type storage element of EPROM.
It has a bit floating gate type field effect transistor structure and is excellent in high integration.

Writing is performed on the drain 1 as in the EPROM.
This is performed by injecting hot carriers generated near the junction into the floating gate 2. By writing, the threshold value as viewed from the control gate 4 of the memory cell increases. On the other hand, in erasing, the control gate 4 is grounded, and a high voltage is applied to the source 3 to generate a high electric field between the floating gate 2 and the source 3, and the floating is performed using a tunnel phenomenon through the thin oxide film 5. This is performed by extracting the electrons stored in the gate 2 to the source 3. The threshold value seen from the control gate 4 is lowered by the erasing. In reading, a low voltage of about 1 V is applied to the drain 1 so that weak writing hardly occurs, and about 5 V is applied to the control gate 4 so that the magnitude of the flowing channel current corresponds to information 0 and 1. In the figure, 6 is a p-type silicon substrate, 7 is an n-type diffusion layer, 8 is a low concentration n-type diffusion layer, and 9 is a p-type diffusion layer.

[0005] In a memory element that performs an erasing operation by electron tunneling as described above, how to minimize the capacitive coupling between the region to which the erasing voltage is applied (here, the source region) and the floating gate electrode is determined by the cell. This is a point for achieving both miniaturization and low voltage for erasure. In the FAST type memory element, the gate oxide film under the floating gate electrode is entirely thinned (made into a tunnel oxide film), and the overlapping portion of the floating gate electrode and the source region is self-aligned by diffusion and wraparound of the same region. Thus, the electron tunnel region is miniaturized to the utmost, thereby reducing the capacitive coupling.

Proceedings of the IEEE 1989 International Solid-State Circuits Conference, pages 140-141 (IEEE 1nt. Solid-St)
ateCircuits Conference, Digest of Technical Paper
s, p.140-141, Feb., 1989) describes a 1 Mb flash EEP using a storage element similar to the above-mentioned FAST type storage element.
A ROM chip batch electrical erase characteristic is disclosed.

[0007]

The above prior art F
In a flash EEPROM using an AST-type storage element, it is important to ensure controllability of the "1" state threshold voltage (threshold voltage is low) realized by an electric batch erase operation. This is because if the threshold voltage after erasing is too high or too low, a subsequent read operation will fail.

If the threshold voltage after erasing is too high,
Since the current required for reading "1" is insufficient, the lower limit of the read power supply voltage or the read speed is deteriorated.
That is, as a matter of course, the erasing operation must not be insufficient.

On the other hand, if the threshold voltage after erasure is low and the cell is in the debit state, current flows to the storage element in which the word line is not selected at the time of reading. Impossible.
Since the FAST type storage element has no selection transistor, over-erasing cannot be performed.

As a result, in a flash EEPROM using a FAST type storage element, in order to apply an erasing voltage to a common source line and simultaneously erase a large number of storage elements at once, the erasing characteristics of each storage element must be changed. An important precondition is that there is no variation, or at least the variation is kept small.

However, in reality, when the batch erase operation is performed at the LSI level due to various factors such as a variation in the element structure or a variation in the characteristics of the tunnel oxide film, a large variation appears between the erase characteristics. How to make use of this is a major design problem.

An object of the present invention is to provide a nonvolatile semiconductor memory device using the above-mentioned FAST type storage element, and a threshold after erasing even if there is a large variation between the erasing characteristics of the storage elements performing a batch erasing operation. It is an object of the present invention to provide a nonvolatile semiconductor memory device capable of sufficiently suppressing a variation in value voltage.

[0013]

A new aspect of the present invention is that a plurality of memory cells each composed of an electrically erasable nonvolatile memory element are arranged in a matrix and divided into a plurality of memory blocks in a word line direction. In the nonvolatile semiconductor memory device, a write mode for writing information to a memory cell, a read mode for reading a threshold voltage state of a memory cell, and a threshold voltage of a memory cell in one of a plurality of memory blocks are set. An erase mode for applying a voltage for setting the voltage to fall within a predetermined range; and an erase mode for performing an operation of reading a threshold voltage state of the memory cell in the memory block. An erasing control circuit for continuing or stopping the erasing operation based on the erasing control circuit, and the erasing control circuit selects a memory cell in the memory block. Characterized in that it comprises an address generating circuit for.

That is, as shown in FIG. 8, a specific circuit of the present invention forms an address for an erasing operation in the memory in the present invention. It can independently control the erasing operation.

It is also an object of the present invention that the substantial end point of the collective erasing operation is individually determined for each storage element or for each group of several storage elements, depending on the individual erasing speed of each storage element. This is realized by controlling
Specifically, as shown in FIG. 1, this is realized by combining the means described below.

FIG. 1 shows that the memory array M-ARRAY
It is divided into one or more blocks (MB1 to MB4 in FIG. 1). Each block is composed of at least one storage element, and means (ED1 to ED4 in the figure) for performing electrical erasure independently for each block. Have.

Second, whether the threshold voltage of all the storage elements in the block is low and the erasure is not necessary or whether there is at least one element having a high threshold voltage for each block prior to the electrical erasure. (In the figure, a reading device SA).

Third, there is provided a means for preventing application of an erase voltage so that the erase operation of the batch erase is not performed when the threshold voltage of all the storage elements in the block is low and there is no need to erase. That is, it has a function of determining whether or not to apply an erase voltage in response to the output of SA to ED1 to ED4.

Finally, when the necessary and sufficient erasing operation has been performed for all the target storage elements, the batch erasing is completed. This may be determined inside the device or by an external control device.

FIG. 1 shows a memory array (M-ARRAY)
Shows a case where the number of the readout devices SA is one.
A total of eight or sixteen sets of memory arrays and read devices SA are provided so that reading and writing can be performed in bit units or 16 bit units. In the case of eight sets, the configuration is as shown in FIG.

In FIG. 1, the memory array M-ARRA
Although it is assumed that the entire Y is erased, a partial erase may be performed in which only a part of the Y is erased. That is, when simultaneously erasing blocks MB1 and MB2,
2 is a block constituting it.

According to the above means, the batch erasing operation as a chip is continued until the slowest erasing of all the target storage elements is completed. No further substantial erasure is performed on the storage element that has been erased to the level. As a result, even if there is a variation in the erasing characteristics of the storage elements to be collectively erased, the threshold voltage after erasing can be accurately adjusted to a desired value.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following examples, the technologies listed below will be described.

1. In a memory array in which a plurality of electrically erasable nonvolatile memory elements are arranged in a matrix, a negative voltage is applied to a control gate of the memory cell, and information charges stored in a floating gate are applied. A non-volatile semiconductor memory device in which a threshold voltage is changed by pulling out a voltage to a source, a drain or a well.

2. In a memory array in which a plurality of electrically erasable nonvolatile memory elements are arranged in a matrix, the memory array is divided in a word line direction and has a plurality of the memory cells. A nonvolatile semiconductor memory device having a plurality of blocks and having a common source line common to each of the plurality of memory blocks.

3. A memory array in which a plurality of electrically erasable nonvolatile memory elements are arranged in a matrix, and a negative voltage generating circuit for applying a negative voltage to a word line connected to the gate of the memory cell Wherein the negative voltage generating circuit is of a charge-pump type.

4. A memory array in which a plurality of electrically erasable nonvolatile memory elements are arranged in a matrix, and a negative voltage generating circuit for applying a negative voltage to a word line connected to the gate of the memory cell A non-volatile semiconductor circuit device comprising: an address decoder connected to the negative voltage generation circuit via the word line; and a transistor connected between the word line and the address decoder. .

5. A first power supply line, a second power supply line, a first MOSFET of a first conductivity type having a source electrode connected to a fixed potential and a gate electrode connected to an input line,
A second conductivity type second MOSFET having a drain electrode connected to the drain electrode of the first MOSFET, a source electrode connected to the first power supply line, and a gate electrode connected to the control line; Is connected to the control line, and its drain electrode is connected to the second MOSFET.
A third MOSFET of the first conductivity type, the source electrode of which is connected to a fixed potential, the source electrode of which is connected to the input line, and the gate electrode of which is connected to the drain electrode of the third MOSFET. , A fourth conductive type MO having its drain electrode connected to the output line.
The SFET and the drain electrode are the fourth MOSFET
And a fifth MOSFET of a second conductivity type having a source electrode connected to the second power supply line and a gate electrode connected to a fixed potential.

6. In a nonvolatile semiconductor memory device in which a plurality of electrically erasable nonvolatile memory elements are arranged in a matrix and divided into a plurality of memory blocks in a word line direction, a write operation for writing information to the memory cells is performed. Read mode for reading the state of the threshold voltage of the memory cell, erasing by applying a voltage for setting the threshold voltage of the memory cell in one of the plurality of memory blocks within a predetermined range. An erasing mode for performing an operation and an operation of reading a threshold voltage state of the memory cell in the memory block, wherein the erasing operation is continued or stopped based on information at the time of the reading operation in the erasing mode. An erasing control circuit, wherein the erasing control circuit selects an memory cell in the memory block. The nonvolatile semiconductor memory device which comprises a less generator.

[7] A write mode for writing information to a memory cell composed of a nonvolatile memory element electrically erasable, a read mode for reading a threshold voltage of the memory cell, and a threshold voltage of the memory cell within a predetermined range. And an erasing mode for performing an erasing operation for applying a voltage for setting the threshold voltage of the memory cell and an operation for reading a threshold voltage state of the memory cell. The erasing mode is connected to the gate of the memory cell during the reading operation in the erasing mode. The nonvolatile semiconductor memory device according to claim 1, wherein a voltage applied to the word line is lower than a voltage applied to the word line in the read mode.

8. In a nonvolatile semiconductor memory device including a plurality of memory cells each including an electrically erasable nonvolatile memory element, a voltage for changing a threshold voltage of the plurality of memory cells within a predetermined range is applied. An erase mode for performing an erase operation and a read operation for sequentially reading the state of the threshold voltage of the memory cell is provided. During the read operation in the erase mode, a memory cell whose threshold voltage is not within the predetermined range is detected. A non-volatile semiconductor memory device wherein the read operation is stopped at the point in time and the operation is shifted to the erase operation.

(Embodiment 1) An embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the memory cell shown in FIG. 3 is assumed. That is, erasing is performed by grounding the gate and applying a high voltage to the source.

Although each circuit element in the figure is not particularly limited, it is formed on a single semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique.

Although not particularly limited, the integrated circuit is a single crystal p
It is formed on a semiconductor substrate made of mold silicon. The n-channel MOSFET is formed of polysilicon formed on the semiconductor substrate between the source and drain regions and the source and drain regions with a thin gate insulating film formed between the source and drain regions. It is composed of a gate electrode.

The p-channel MOSFET is formed in an n-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate forms a common substrate gate of the plurality of n-channel MOSFETs formed thereon, and the ground potential of the circuit is supplied. The common substrate gate of the p-channel MOSFET, that is, the n-type well region is connected to the power supply voltage Vcc. Alternatively, in the case of a high voltage circuit, it is connected to an externally applied high voltage Vpp, an internally generated high voltage, or the like. Alternatively, the integrated circuit may be formed over a semiconductor substrate made of single-crystal n-type silicon. In this case, n channel MOSFE
T is formed in the p-type well region.

Although not particularly limited, the EEP of this embodiment
The ROM stores address signals AX and A supplied from external terminals.
The complementary address signal formed through the address buffer ADB receiving Y receives the address decoders XDCR and YDC.
Supplied to R. Although not particularly limited, the address buffers XADB and YADB are connected to the internal chip select signal $ ce.
, And address signals AX,
AY is taken in, and a complementary address signal composed of an internal address signal having the same phase as the address signal supplied from the external terminal and a reverse address signal is formed.

The row address decoder XDCR is activated by the address decoder activation signal DE, and forms a selection signal for the word line W of the memory array M-ARRAY according to the complementary address signal of the address buffer XADB.

The column address decoder YDCR is activated by an address decoder activating signal DE, and the memory array M according to the complementary address signal of the address buffer ADB.
-Generate selection signals for the ARRAY data lines D1 to D4.

The memory array M-ARRAY exemplarily shows two memory blocks MB1 and MB2 as representatives. The memory block MB1 includes storage elements (memory cells) M1 to M8, word lines W1 to W4, and data lines D
1 to D2, the memory block MB2 becomes the storage element M
9 to M16, word lines W1 to W4, and data lines D3 to D
4.

In the memory block, the gates of the storage elements arranged in the same row are connected to corresponding word lines, respectively, and the drains of the storage elements arranged in the same column are connected to corresponding data lines. The source of the storage element is coupled to source lines CS1 and CS2. In this embodiment, the source lines CS1 and CS2 are provided with erase control circuits ED1 and ED2.

Although not particularly limited, as described above, 8
Since writing / reading is performed in units of bits or 16 bits, the memory array has a total of 8 sets or 16 sets.
It is constituted so that it may be provided.

Each of the data lines D1 to D4 constituting the one memory array M-ARRAY is connected to a common data line C via a column selection switch MOSFET Q1 to Q4 which receives a selection signal formed by the address decoder YDCR.
D is connected. An external terminal I / O is connected to the common data line CD.
MOS that turns on the output terminal of the write data input buffer DIB which receives a write signal input from the memory during writing.
Connected via FET Q5. Similarly, a column selection switch MOSFET similar to the above is provided for other memory arrays, and a selection signal is formed by an address decoder corresponding to the same.

A common data line CD provided corresponding to the memory array M-ARRAY has a switch MOSF
Coupled to sense amplifier SA via ETQ6.

FIG. 5 shows a circuit of the sense amplifier SA.
The common data line CD is connected to the source of an n-channel MOSFET Q7 whose source is connected via a MOSFET Q6 which is turned on by a read control signal re. Between the drain of the n-channel MOSFET Q7 and the power supply voltage terminal Vcc, a p-channel load MOSFET Q to which the ground potential of the circuit is applied to the gate.
8 are provided. The load MOSFET Q8 performs an operation of flowing a precharge current to the common data line CD for a read operation.

In order to increase the sensitivity of the MOSFET Q7 and to keep the data line potential at a substantially constant low voltage to prevent weak writing during reading, a switch MOSF is used.
The potential of the common data line CD via the ETQ6 is divided into an n-channel drive MOSFET Q9 and a p-channel load MOSFET.
Drive M which is the input of the inverting amplifier circuit composed of FET Q10
It is supplied to the gate of OSFET Q9.

The output voltage of this inverting amplifier circuit is
It is supplied to the gate of FET Q7. In order to prevent unnecessary power consumption during the non-operating period of the sense amplifier, the above MOS is used.
An n-channel MOSFET Q11 is provided between the gate of the FET Q7 and the ground potential point of the circuit. This MOS
The operation timing signal #sc of the sense amplifier is commonly supplied to the gates of the FET Q11 and the p-type MOSFET Q10.

Although the timing control circuit CNTR is not particularly limited, a chip enable signal, an output enable signal, a write enable signal, an erase enable signal, and a write enable signal supplied to the external terminals $ CE, $ OE, $ WE, $ EE and Vpp are provided. / Timing signals such as internal control signals $ ce and $ sc according to the high voltage for erasing, and low voltage Vc for reading selectively supplied to address decoders and the like
c / Generates a high voltage Vpp for writing and the like. For example, assuming a relationship between each mode and an external signal as shown in FIG. 6, a timing control circuit CNTR for realizing this is shown in FIG. 7 as an example.

In the read mode, the internal signal $ ce is at a low level, DE and re are at a high level, and $ sc is at a low level. Address decoder circuits XDCR, YDCR
Is activated, and one word line and one data line are selected. The address decoder circuits XDCR and YDCR and the data input circuit DIB have a low voltage Vc as their operating voltage.
c is supplied. MOSFET Q10 is turned on,
OSFET Q11 is turned off.

The memory cell has a high threshold value or a low threshold value with respect to the word line selection level in accordance with previously written data. Each address decoder XDC
When the threshold value of the memory cell selected by R and YDCR is high and the word line is turned off despite being at the selected level, the common data line CD is supplied by current supply from MOSFETs Q8 and Q7. Relatively high level. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to a relatively low level.

In this case, the high level of the common data line CD is limited to a relatively low potential by being supplied to the gate of the relatively low-level output voltage MOSFET Q7 formed by the inverting amplifier circuit receiving it. On the other hand, the low level of the common data line CD is limited to a relatively high potential by supplying a relatively high level output voltage formed by an inverting amplifier circuit receiving the same to the gate of the MOSFET Q7.

The amplifying MOSFET Q7 performs an amplifying operation of a common-gate type source input, and transmits its output signal to the CMOS inverter circuit INVI. The output signal is shaped by the inverter INV2.
The signal SO has a high level when the threshold value of the memory is high, and has a low level when the threshold value is low. Although not particularly limited by the corresponding data output buffer DOB, the data is amplified and transmitted from the external terminal I / O. This data output buffer DOB is supplied with a data output buffer control signal DO,.
Controlled by DO. DO goes high in the read mode and the verify mode after writing, activates the data output buffer DOB, and sends data to the I / O terminal. A read circuit including a sense amplifier and a data output buffer similar to those described above is provided between a common data line corresponding to another memory block and an external terminal.

In the write mode, the internal signal $ ce is at a low level, DE, wr, and $ se are at a high level.
e and DO are set to low level. The address decoder circuits XDCR and YDCR are activated, and one word line, one
One data line is selected. Address decoder circuit XD
The high voltage Vpp is supplied as an operation voltage to the CR, YDCR and data input circuit DIB. MOSFET Q6
Is turned off, and the data output buffer DOB and the sense amplifier are inactivated. The voltage of the word line on which writing is performed becomes the high voltage Vpp. The data line connected to the storage element to which electrons are to be injected into the floating gate is MOSFE
Connected to high voltage Vpp via TQ5 and DIB. Thereby, writing is performed on the storage element. In the memory element in the written state, electrons are accumulated in the floating gate, the threshold voltage becomes high, and no drain current flows even when a word line is selected. When electrons are not injected, the threshold voltage is low and a current flows when a word line is selected. Between the common data line corresponding to the other memory block and the external terminal, a similar input stage circuit and a write circuit including a data input buffer are provided.

In the verify mode after writing, the state is the same as in the read mode except that a high voltage is applied to the Vpp terminal. Address decoder circuit, XDCR, YDC
R and the data input circuit DIB are switched from the high voltage Vpp to Vcc and supplied as the operating voltage. The user confirms whether or not the data has been written.

In the write / erase inhibit mode, each decoder is activated, but a high voltage for writing / erasing is not supplied to each decoder.

The erasing mode will be described with reference to FIGS. FIG. 8 shows the erase control circuit ECNT shown in FIG.
FIG. 9 shows the erase voltage application circuit ED in FIG.
Is an address buffer circuit ADB decoder circuit XDCR,
FIG. 11 shows a timing chart of the erase mode.

In the erase mode, the control signals DE, wr, r
e and DO become low level and sc become high level.

When モ ー ド EE0 changes from the high level to the low level, the erase mode starts. First, the reset pulse RST goes high for a time determined by the delay circuit D1, and the erase voltage application circuit ED is reset. Next, flip-flop circuit FF is set, and the block to be erased is read. During this time, the read mode signal EV before erasure is set to low level, the oscillator OSC starts oscillating, and generates an internal address. The signals A0I, A1I, and A2I sequentially divided by the binary counter BC are supplied to the address buffer ADB.
One column select switch is selected. At this time, since EE1 is at a high level, the address buffer ADB removes A3,
Does not accept external input. The address signal A3 is externally applied and is used for selecting the internal block MB1 or MB2.

When the memory selected by the internal address is read, the result is fed back to erase voltage applying circuit ED. As shown in FIG. 9, the memory block MB1
When the output SO of the sense amplifier SA is determined to be at the high level when the oscillation pulse OS is at the low level while either of the column selection signals Y1 and Y2 is at the high level, that is, when the threshold voltage of the memory cell is determined to be high, the flip-flop Is set, and a high voltage is not applied to the common source line CS1 even if the erase pulse #EP goes low during an erase period described later. When reading is completed for all memory cells in the memory block, the read completion signal ER goes high, resetting the flip-flop FF,
To low level. Next, the erasing period starts, and the delay circuit D
After the lapse of the period determined in step 2, the erase pulse EP goes low, all word lines go low, and a high voltage is applied to the source of the memory that is not sufficiently erased.

In the case shown in FIG. 4, 1 is assigned to the memory block.
Since there is only one erase voltage application circuit ED, optimization is performed for each of eight or sixteen I / Os (memory arrays). When erasing the entire chip, optimization is further performed for each of the memory blocks MB1 and MB2.

In the above read operation, a normal read voltage (for example, 5 V) is applied to the sense amplifier SA and the decoder circuits XDCR and YDCR in order to secure an operating power supply voltage margin.
A lower voltage Vev, for example 3.5V, is provided. This is preferably generated within the storage device, but may be provided externally.

FIG. 18 shows the effect of the present invention. The vertical axis shows the threshold voltage variation in the device after erasing, and the horizontal axis shows the number of storage elements in one memory block. Here, eight memory arrays M-ARRAY are present in the numerical values, and writing and reading in units of 8 bits are performed. It goes without saying that the smaller the storage element in the memory block is, the larger the effect is, but the peripheral circuit becomes complicated. The size of the memory block may be determined in consideration of the effect of suppressing the threshold voltage variation and the complexity of the peripheral circuit.

In this embodiment, the case where reading before erasing is performed for all the storage elements in the memory block has been described, but the present invention is not limited to this. In the case of a configuration including eight read / write units, reading may be stopped when a memory cell having a high threshold voltage is detected in all the read / write units, and the erase operation may be started. Thus, the read time before erasing can be reduced.

Although the present embodiment is directed to the case where writing / erasing is performed using an externally applied high voltage Vpp, the present invention is not limited to this. If the current flowing at the time of writing / erasing is small, a desired high voltage may be generated from Vcc inside the device and used for writing / erasing. Further, the internal boosted power supply may be used together with the external high voltage Vpp.

It is needless to say that the present invention is not limited to the above embodiment. The configuration of a circuit portion for controlling normal writing / reading and the like and a circuit portion for controlling erasing may be any configuration as long as the above principle is realized.

(Embodiment 2) FIG. 1 shows a second embodiment of the present invention.
This will be described with reference to FIGS.

FIG. 12 is an internal block diagram of the nonvolatile memory device according to the present embodiment, and corresponds to FIG. 4 of the first embodiment. Here, as a memory cell, a negative voltage is applied to the gate at the time of erasing, a positive voltage (here, an external power supply Vcc) is applied to the source, and electrons in the floating gate are applied to the source by a high electric field between the gate and the source. Memory is used.

Except for this erasing operation, this embodiment is the same as the first embodiment.
Since there is no essential operation difference, only differences from the first embodiment will be described.

The transistors Q12 to Q15 are depletion-type pMOSFETs, and serve to prevent a negative voltage applied to the hood line from being applied to the decoder circuit during erasing. At the same time, during read / write operation, the transistor is of a depletion type in order to prevent a voltage drop and a speed drop in this transistor.

The erase voltage application circuits ED1 and ED2 are shown in FIG.
9 is the same as FIG. 9 except for the final stage. In FIG. 9, Vpp is applied to the common source line CS1, but in this case, Vcc is applied.

FIG. 14 shows a circuit of the negative voltage application circuit NEG. This is a so-called charge pump circuit. When the erasing signal $ EP goes low, the signal $ EPDLY goes low after a lapse of time determined by the delay circuit D3, and the decoder disconnection signal SET goes high.
As a result, the row decoder circuit XDCR is electrically disconnected from the word line. Next, the oscillator OSC2 starts oscillating, generating complementary pulse signals PU1 and PU2, thereby generating a negative voltage Vppn by the principle of a charge pump. This is further applied to the word line using the pulse PU1 according to the principle of the charge pump. When the erase signal $ EP is set to the high level, the pulses PU1 and PU2 are stopped. However, during the period until the signal $ EPDLY goes to the high level, the negative voltage reset signals PRST and ERST change the node of the negative potential from 0 V to a positive voltage. And stop the erasure.

The operation in the erasing mode in this embodiment is executed in the same manner as in the first embodiment. In the first embodiment, erasing was performed by applying a high voltage to the source.
The difference is that a negative voltage is applied to cc and the gate.

(Embodiment 3) FIG. 1 shows a third embodiment of the present invention.
This will be described with reference to FIGS.

FIG. 15 is an internal block diagram of the nonvolatile memory device according to the present embodiment, which corresponds to FIG. 4 of the first embodiment and FIG. 12 of the second embodiment. Here, as in the case of the second embodiment, a negative voltage is applied to the gate during erasing and a positive voltage (Vc which is an external power
c) is applied, and a memory in which electrons in the floating gate are drawn out to the source by a high electric field between the gate and the source is used.

Although there is no essential operational difference from the second embodiment,
The difference is that the memory block is determined not only by the source but also by the source and the word line. Hereinafter, only differences from the first and second embodiments will be described.

FIG. 16 shows a circuit of the negative voltage application circuit NEG, which is different from FIG. 14 in that a decoding function for selecting a memory block is incorporated.

The address buffer circuit differs in that external inputs A1 and A3 are used for selecting a block as shown in FIG. Further, selection of a memory block in the word direction, that is, memory blocks MB1 and MB3, MB2 and MB
4 to select the address buffer circuit ADB.
The memory block can be selected even when the A0 input section and the row decoder XDCR erase voltage are applied. That is, a0 and $ a0 both become low level, and the two word outputs WI1 and WI determined by the A1 address input.
2, or WI3 and WI4 become high level. The outputs WI1 to WI4 are supplied to a negative voltage application circuit NEG. However, due to the operation of transistors Q12-Q15, the output of the decoder circuit at the time of erasure is word lines W1-W.
No. 4 is not applied.

The operation in the erasing mode in this embodiment is executed in the same manner as in the second embodiment. However, Example 2
In contrast, one stage of the binary counter BC in FIG.

[0078]

According to the present invention, an electrically rewritable fine nonvolatile memory cell which consumes less current during an erase operation and has excellent reliability can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a semiconductor memory device for explaining the principle of the present invention.

FIG. 2 is a block diagram of a semiconductor memory device for explaining the principle of the present invention.

FIG. 3 is a cross-sectional view of a semiconductor element included in a memory cell.

FIG. 4 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 5 is a partial circuit diagram of the semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is an explanatory diagram showing a relationship between an operation mode of the device according to the embodiment of the present invention and an external signal.

FIG. 7 is a circuit diagram of a timing control circuit in the semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a circuit diagram of an erase control circuit in the semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is a circuit diagram of an erase voltage application circuit in the semiconductor memory device according to the embodiment of the present invention.

FIG. 10 is a circuit diagram of an address buffer circuit and a decoder circuit in the semiconductor memory device according to the embodiment of the present invention.

FIG. 11 is an operation timing chart in the erase mode of the semiconductor memory device according to the embodiment of the present invention.

FIG. 12 is a schematic circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 13 is a partial circuit diagram of the semiconductor memory device according to the embodiment of the present invention.

FIG. 14 is a partial circuit diagram of the semiconductor memory device according to the embodiment of the present invention.

FIG. 15 is a schematic circuit diagram of a semiconductor memory device according to an example of the present invention.

FIG. 16 is a partial circuit diagram of the semiconductor memory device according to the embodiment of the present invention.

FIG. 17 is a partial circuit diagram of the semiconductor memory device according to the embodiment of the present invention.

FIG. 18 is a graph showing a relationship between the number of storage elements in a memory block and a variation in a threshold after erasing in a semiconductor memory device according to an example of the present invention.

[Explanation of symbols]

ADB: address buffer, XDCR: row address decoder, YDCR: column address decoder, M1 to M16 ...
Memory array, CNTR ... Timing control circuit, ECN
TR: erase control circuit, ED1, ED2: erase voltage applying circuit, DOB: data output buffer, DIB: data input buffer, CS1 to CS2: common source line, CD: common data line, SA: sense amplifier, MB1 to MB4 ... Memory block.

Claims (6)

[Claims] A plurality of memory cells each comprising an electrically erasable nonvolatile memory element are arranged in a matrix;
In a nonvolatile semiconductor memory device divided into a plurality of memory blocks, a write mode for writing information to the memory cell, a read mode for reading a state of a threshold voltage of the memory cell,
An erase operation of applying a voltage for setting a threshold voltage of the memory cell in one memory block of the plurality of memory blocks within a predetermined range, and a state of the threshold voltage of the memory cell in the memory block. An erase mode for performing a read operation; and an erase control circuit for continuing and stopping the erase operation based on information at the time of the read operation in the erase mode. A nonvolatile semiconductor memory device comprising an address generation circuit for selecting the memory cell. 2. A voltage applied to a word line connected to a gate of the memory cell during a read operation in the erase mode is different from a voltage applied to the word line in the read mode. A nonvolatile semiconductor memory device characterized by the above-mentioned. 3. The memory cell according to claim 1, wherein the memory cell has a two-layer gate structure of a floating gate and a control gate.
3. The non-volatile memory according to claim 1, wherein the FET is electrically erasable by extracting information charges accumulated in a floating gate to a source, a drain or a well by utilizing a tunnel phenomenon. Semiconductor memory device. 4. The memory cell according to claim 1, wherein said memory cell has a two-layer gate structure of a floating gate and a control gate.
FET, the source or drain is shared in the memory block, the gate is set to the ground potential,
Electrical erasing is performed by applying a voltage to a common source or drain and extracting information charges accumulated in the floating gate to the source, drain or well using the tunnel phenomenon. 3. The semiconductor nonvolatile memory device according to claim 1, wherein 5. The memory cell according to claim 1, wherein said memory cell has a two-layer gate structure of a floating gate and a control gate.
In the memory block, a source or a drain is shared, a negative voltage is applied to the gate, a voltage is applied to the shared source or drain, and the information charge stored in the floating gate is a FET. 3. The semiconductor non-volatile memory device according to claim 1, wherein electrical erasing is performed by pulling out the source, drain, or well using a tunnel phenomenon. 6. The memory cell according to claim 1, wherein said memory cell has a two-layer gate structure of a floating gate and a control gate.
A source having a common source or drain in the memory block and a means for applying a negative voltage only to a word line connected to a gate of a memory cell belonging to the memory block; Electrical erasing by applying a negative voltage to the word line, applying a voltage to the common source or drain, and drawing out information charges stored in the floating gate to the source, drain or well using the tunnel phenomenon 3. The semiconductor nonvolatile memory device according to claim 1, wherein